bissen21/Marlin_Firmware
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188 Commits

Author SHA1 Message Date
Scott Lahteine
ee53f7d813 Revert header reorg. 2018-10-02 22:09:41 -05:00
Scott Lahteine
0dedb3e139
Reorganize some core headers (#11983) 2018-10-02 04:25:46 -05:00
Scott Lahteine
11ac75edcb
Use PGM_P for PSTR pointers (#11977) 2018-09-30 23:44:33 -05:00
Scott Lahteine
ad21a4f07b Tweaks to HAL format and order 2018-09-28 15:59:50 -05:00
Holger Müller
1a6f2b29b8 Add support for Triple-Z steppers/endstops 2018-09-16 00:35:58 -05:00
Scott Lahteine
6a3207391f Remove obsolete HAL_timer_restrain 2018-08-31 16:17:22 -05:00
Scott Lahteine
a317bb4991 Remove stray tab 2018-08-24 17:35:13 -05:00
Scott Lahteine
ba1919c1eb HAL tweaks to LPC1768 main 2018-08-22 17:16:18 -05:00
Scott Lahteine
0987ed2a18 Use American English 2018-08-22 17:16:18 -05:00
Chris Pepper
5573ef62c6 [2.0.x] PersistentStore update followup (#11549) 2018-08-14 17:54:12 -05:00
Scott Lahteine
834ea7fcea Remove 'const' from PersistentStore::capacity 2018-08-14 04:46:10 -05:00
Dave Johnson
c64199941e Compile only selected PIO environment (#11519) 2018-08-14 03:28:52 -05:00
Andy Shaw
5be2559eda Use flash memory to emulate EEPROM (#11500) 
Use a sector of the LPC flash memory to emulate EEPROM storage, removing the need to have an SD card to store system parameters.
 2018-08-14 01:19:34 -05:00
Scott Lahteine
865ee5985f Followup persistent store with heading, const 2018-08-13 23:55:33 -05:00
Chris Pepper
66d2b48b59 Update PersistentStore api (#11538) 
- Clean up the API to use a `static` class instance to adhere to Marlin convention
- Add `const` position data access for read/write
- Add Storage capacity to the interface
 2018-08-13 17:30:25 -05:00
Scott Lahteine
15d68cb496 Pre-override of ST7920 delays before HAL.h 2018-07-26 23:33:18 -05:00
Andy Shaw
624986d423 Ensure ADC conversion is complete before reading (#11336) 
The current Marlin implementation relies on a timer interrupt to start the ADC conversion and read it. However in some circumstances the interrupt can be delayed resulting in insufficient time being available for the ADC conversion. This results in a bad reading and false temperature fluctuations. These changes make sure that the conversion is complete (by checking the ADC hardware via the HAL) before reading a value.

See: https://github.com/MarlinFirmware/Marlin/issues/11323
 2018-07-26 03:59:19 -05:00
teemuatlut
fbcdf5eaeb Simplify stepper driver per-axis selection 2018-07-25 02:47:43 -05:00
teemuatlut
f38c81cdde LPC176x: Expand HW SPI class 2018-07-14 19:06:27 +03:00
teemuatlut
3b5dec4b13 Add new LPC include folder 2018-07-14 18:58:56 +03:00
Chris Pepper
55f4744e54 [LPC176x] Endstop Interrupts Feature (#11202) 
Enable the endstop interrupts feature for LPC176x boards. Although Smoothieboard chose to use non-interrupt capable pins for their endstops, and this has been copied by clones, so they can't use it.
 2018-07-04 17:51:45 -05:00
Chris Pepper
5abf5bc8a7 [LPC176x] Fix Interrupt forward declarations (#11200) 2018-07-04 17:43:14 -05:00
Chris Pepper
5616581eb1 [LPC176x] Update fastio _GET_INPUT, _GET_OUTPUT macros (#11168) 2018-07-01 23:02:38 -05:00
Scott Lahteine
d86f25ab63 Fix Serial ISR priority for LPC1768 
Co-Authored-By: p3p <p3p@p3psoft.co.uk>
 2018-06-25 12:15:41 -04:00
Scott Lahteine
99591dc20c
Filter endstops state at all times (#11066) 2018-06-21 20:14:16 -05:00
Chris Pepper
0312c42f9d [2.0.x] LPC176x Serial cleanup (#11032) 2018-06-16 20:59:22 -05:00
Chris Pepper
f88adcbfd5 [2.0.x][LPC176x] Fix binary linking broken by pio update (#11026) 2018-06-15 15:32:51 -05:00
etagle
a215725df6 Fix stepper pulse timing 
Always honor minimum period on stepper pulse generation, and fix timing calculations

Signed-off-by: etagle <ejtagle@hotmail.com>
 2018-06-12 21:34:24 -05:00
Scott Lahteine
4dbec774b5 HAL_*_TIMER_RATE => *_TIMER_RATE 2018-06-12 16:39:12 -05:00
Eduardo José Tagle
d3c02410a8 [2.0.x] Small assorted collection of fixes and improvements (#10911) 
* Misc fixes and improvements

- Get rid of most critical sections on the Serial port drivers for AVR and DUE. Proper usage of FIFOs should allow interrupts to stay enabled without harm to queuing and dequeuing.
  Also, with 8-bit indices (for AVR) and up to 32-bit indices (for ARM), there is no need to protect reads and writes to those indices.
- Simplify the XON/XOFF logic quite a bit. Much cleaner now (both for AVR and ARM)
- Prevent a race condition (edge case) that could happen when estimating the proper value for the stepper timer (by reading it) and writing the calculated value for the time to the next ISR by disabling interrupts in those critical and small sections of the code - The problem could lead to lost steps.
- Fix dual endstops not properly homing bug (maybe).

* Set position immediately when possible
 2018-06-01 19:02:22 -05:00
Chris Pepper
d87257f63c [2.0.x][LPC176x] Fix PIO build flags (#10909) 
Don't build and link with different flags, the binary may not work.
 2018-05-31 19:08:31 -05:00
Chris Pepper
f89f7c4a82 [2.0.x][LPC176x][Build] Force single precision constants, disable freestanding (#10892) 2018-05-28 19:38:22 -05:00
Scott Lahteine
9b9b62b218 delay(SERVO_DELAY) => safe_delay(servo_delay[servo_index]) 2018-05-28 03:44:32 -05:00
Bob-the-Kuhn
1c0ad8bbae wrong type of exit method 2018-05-26 08:17:03 -05:00
Bob Kuhn
235facd545 install AVRDUDE 5.10, faster disk find for LPC1768 (#10849) 2018-05-25 20:26:48 -05:00
Bob Kuhn
e2db509d58 [2.0.x] Update/Fix LPC1768 extra script upload_extra_script.py (#10843) 
* Use a different method to find the volume info in Windows
 2018-05-25 04:31:18 -05:00
Scott Lahteine
5f8591528e Remove #pragmas that don't help c files 2018-05-23 23:47:16 -05:00
Scott Lahteine
c89649b46e Suppress U8glib build warnings 2018-05-23 02:47:36 -05:00
Bob Kuhn
6dfbb39f83 [LPC1768] Add error-handling to upload script, update autobuild.py (#10802) 2018-05-20 21:22:04 -05:00
etagle
569df3fc0c Fix interrupt-based endstop detection 
- Also implemented real endstop reading on interrupt.
 2018-05-20 07:10:24 -05:00
etagle
0566badcef Add memory barrier, optimal interrupt on-off 
Disabling an ISR on ARM has 3 instructions of latency. A Memory barrier is REQUIRED to ensure proper and predictable disabling. Memory barriers are expensive, so avoid disabling if already disabled (See https://mcuoneclipse.com/2015/10/16/nvic-disabling-interrupts-on-arm-cortex-m-and-the-need-for-a-memory-barrier-instruction/)
 2018-05-20 02:39:34 -05:00
Scott Lahteine
206014a957 Fix LPC176x timer functions 
Co-Authored-By: ejtagle <ejtagle@hotmail.com>
 2018-05-20 01:58:51 -05:00
Chris Pepper
9b64fdbc3a [LPC176x] HAL: Add missing program space definition (#10776) 2018-05-19 15:37:54 -05:00
Scott Lahteine
50270b53a0 Clear up some more compile warnings 2018-05-17 18:40:49 -05:00
etagle
40d7e12827 Removing warnings from compilation 2018-05-17 18:04:22 -05:00
Scott Lahteine
fb608938f8 Prevent compilation of unused u8g-oriented code 2018-05-14 13:31:04 -05:00
Scott Lahteine
37b15fe4cf Reorder HAL timer header items 2018-05-13 16:50:39 -05:00
Scott Lahteine
99ecdf59af Smarter MIN, MAX, ABS macros 
Use macros that explicitly avoid double-evaluation and can be used for any datatype, replacing `min`, `max`, `abs`, `fabs`, `labs`, and `FABS`.

Co-Authored-By: ejtagle <ejtagle@hotmail.com>
 2018-05-13 04:52:56 -05:00
etagle
9d98a62699 Followup to HAL optimizations and delays 
- Cleanups, fixes for Due HAL code.
- TC_IER is write-only. Use TC_IMR to test ISR state.
 2018-05-13 00:46:23 -05:00
Scott Lahteine
a1062eec5b
Better handling of DELAY_NS and DELAY_US (#10716) 
Co-Authored-By: ejtagle <ejtagle@hotmail.com>
 2018-05-12 08:34:04 -05:00