Add gitignore
create motor_controller source files.
This commit is contained in:
1
.gitignore
vendored
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1
.gitignore
vendored
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@@ -0,0 +1 @@
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|||||||
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build/*
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||||||
25
.mxproject
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25
.mxproject
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File diff suppressed because one or more lines are too long
@@ -164,8 +164,8 @@ ProjectManager.MainLocation=Core/Src
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|||||||
ProjectManager.NoMain=false
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ProjectManager.NoMain=false
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||||||
ProjectManager.PreviousToolchain=
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ProjectManager.PreviousToolchain=
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ProjectManager.ProjectBuild=false
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ProjectManager.ProjectBuild=false
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ProjectManager.ProjectFileName=CustomCode.ioc
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ProjectManager.ProjectFileName=BLDC-Motor-Controller.ioc
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ProjectManager.ProjectName=CustomCode
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ProjectManager.ProjectName=BLDC-Motor-Controller
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ProjectManager.ProjectStructure=
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ProjectManager.ProjectStructure=
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ProjectManager.RegisterCallBack=
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ProjectManager.RegisterCallBack=
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ProjectManager.StackSize=0x400
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ProjectManager.StackSize=0x400
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||||||
@@ -174,7 +174,7 @@ ProjectManager.ToolChainLocation=
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ProjectManager.UAScriptAfterPath=
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ProjectManager.UAScriptAfterPath=
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ProjectManager.UAScriptBeforePath=
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ProjectManager.UAScriptBeforePath=
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ProjectManager.UnderRoot=false
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ProjectManager.UnderRoot=false
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ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_USART1_UART_Init-USART1-false-HAL-true,5-MX_TIM3_Init-TIM3-false-HAL-true,6-MX_ADC_Init-ADC-false-HAL-true,7-MX_TIM1_Init-TIM1-false-HAL-true
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ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_USART1_UART_Init-USART1-false-HAL-true,5-MX_TIM3_Init-TIM3-false-HAL-true,6-MX_ADC_Init-ADC-false-HAL-true,7-MX_TIM1_Init-TIM1-false-HAL-true,8-MX_TIM2_Init-TIM2-false-HAL-true
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ProjectManager.iocOrigin=MotorControl
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ProjectManager.iocOrigin=MotorControl
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RCC.AHBFreq_Value=32000000
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RCC.AHBFreq_Value=32000000
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RCC.APB1Freq_Value=32000000
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RCC.APB1Freq_Value=32000000
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@@ -210,9 +210,9 @@ TIM1.BreakState=TIM_BREAK_DISABLE
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TIM1.Channel-PWM\ Generation1\ CH1\ CH1N=TIM_CHANNEL_1
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TIM1.Channel-PWM\ Generation1\ CH1\ CH1N=TIM_CHANNEL_1
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TIM1.Channel-PWM\ Generation2\ CH2\ CH2N=TIM_CHANNEL_2
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TIM1.Channel-PWM\ Generation2\ CH2\ CH2N=TIM_CHANNEL_2
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TIM1.Channel-PWM\ Generation3\ CH3\ CH3N=TIM_CHANNEL_3
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TIM1.Channel-PWM\ Generation3\ CH3\ CH3N=TIM_CHANNEL_3
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TIM1.DeadTime=32
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TIM1.DeadTime=PWM_DEADTIME_COUNTS
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TIM1.IPParameters=Period,Prescaler,BreakState,AutomaticOutput,Channel-PWM Generation2 CH2 CH2N,OCFastMode_PWM-PWM Generation2 CH2 CH2N,DeadTime,OffStateRunMode,OffStateIDLEMode,Channel-PWM Generation1 CH1 CH1N,Channel-PWM Generation3 CH3 CH3N,OCFastMode_PWM-PWM Generation1 CH1 CH1N,OCFastMode_PWM-PWM Generation3 CH3 CH3N
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TIM1.IPParameters=Period,Prescaler,BreakState,AutomaticOutput,Channel-PWM Generation2 CH2 CH2N,OCFastMode_PWM-PWM Generation2 CH2 CH2N,DeadTime,OffStateRunMode,OffStateIDLEMode,Channel-PWM Generation1 CH1 CH1N,Channel-PWM Generation3 CH3 CH3N,OCFastMode_PWM-PWM Generation1 CH1 CH1N,OCFastMode_PWM-PWM Generation3 CH3 CH3N
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TIM1.IPParametersWithoutCheck=Period
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TIM1.IPParametersWithoutCheck=DeadTime,Period
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TIM1.OCFastMode_PWM-PWM\ Generation1\ CH1\ CH1N=TIM_OCFAST_ENABLE
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TIM1.OCFastMode_PWM-PWM\ Generation1\ CH1\ CH1N=TIM_OCFAST_ENABLE
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TIM1.OCFastMode_PWM-PWM\ Generation2\ CH2\ CH2N=TIM_OCFAST_ENABLE
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TIM1.OCFastMode_PWM-PWM\ Generation2\ CH2\ CH2N=TIM_OCFAST_ENABLE
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TIM1.OCFastMode_PWM-PWM\ Generation3\ CH3\ CH3N=TIM_OCFAST_ENABLE
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TIM1.OCFastMode_PWM-PWM\ Generation3\ CH3\ CH3N=TIM_OCFAST_ENABLE
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@@ -229,7 +229,8 @@ TIM3.IPParameters=Channel-PWM Generation4 CH4,Prescaler,Period,ClockDivision
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TIM3.IPParametersWithoutCheck=Period
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TIM3.IPParametersWithoutCheck=Period
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TIM3.Period=PWM_COUNTS-1
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TIM3.Period=PWM_COUNTS-1
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TIM3.Prescaler=1
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TIM3.Prescaler=1
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USART1.IPParameters=VirtualMode-Asynchronous
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USART1.BaudRate=115200
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USART1.IPParameters=VirtualMode-Asynchronous,BaudRate
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USART1.VirtualMode-Asynchronous=VM_ASYNC
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USART1.VirtualMode-Asynchronous=VM_ASYNC
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VP_SYS_VS_Systick.Mode=SysTick
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VP_SYS_VS_Systick.Mode=SysTick
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VP_SYS_VS_Systick.Signal=SYS_VS_Systick
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VP_SYS_VS_Systick.Signal=SYS_VS_Systick
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22
Core/Inc/motor_controller.h
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22
Core/Inc/motor_controller.h
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@@ -0,0 +1,22 @@
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#ifndef MOTOR_CONTROLLER_H
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#define MOTOR_CONTROLLER_H
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#include "stm32f0xx_hal.h"
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#include "stm32f0xx_hal_def.h"
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#include "stm32f0xx_hal_tim.h"
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typedef struct {
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TIM_HandleTypeDef* Driver_PWM_TIM;
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uint32_t U_Phase_TIM_Channel;
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uint32_t V_Phase_TIM_Channel;
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uint32_t W_Phase_TIM_Channel;
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}Cont_Mot_Interface_TypeDef;
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typedef struct {
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Cont_Mot_Interface_TypeDef Motor_Interface;
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} Motor_TypeDef;
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void BLDC_Init(Cont_Mot_Interface_TypeDef Interface);
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void BLDC_Loop();
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#endif
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@@ -24,6 +24,7 @@
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#include <stdio.h>
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#include <stdio.h>
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#include <string.h>
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#include <string.h>
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#include "motor_controller.h"
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/* USER CODE END Includes */
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/* USER CODE END Includes */
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@@ -37,8 +38,9 @@
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#define PWM_COUNTS 2000
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#define PWM_COUNTS 2000
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#define CLOCK_SPEED_MHZ 32
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#define CLOCK_SPEED_MHZ 32UL
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#define PWM_DEADTIME_NS 1000
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#define PWM_DEADTIME_NS 1000UL
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#define PWM_DEADTIME_COUNTS (CLOCK_SPEED_MHZ * 1000UL / PWM_DEADTIME_NS)
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/* USER CODE END PD */
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/* USER CODE END PD */
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@@ -124,22 +126,30 @@ int main(void)
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static uint32_t loops;
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static uint32_t loops;
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HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_4);
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HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_4);
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HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_1);
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HAL_TIMEx_PWMN_Start(&htim1, TIM_CHANNEL_1);
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HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_2);
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HAL_TIMEx_PWMN_Start(&htim1, TIM_CHANNEL_2);
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HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_3);
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HAL_TIMEx_PWMN_Start(&htim1, TIM_CHANNEL_2);
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HAL_TIM_Base_Start_IT(&htim2);
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// HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_1);
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// HAL_TIMEx_PWMN_Start(&htim1, TIM_CHANNEL_1);
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//TIM1->BDTR |= TIM_BDTR_MOE;
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// HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_2);
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// HAL_TIMEx_PWMN_Start(&htim1, TIM_CHANNEL_2);
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// HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_3);
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// HAL_TIMEx_PWMN_Start(&htim1, TIM_CHANNEL_3);
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Cont_Mot_Interface_TypeDef MotorInterface = {
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.Driver_PWM_TIM = &htim1,
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.U_Phase_TIM_Channel = TIM_CHANNEL_1,
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.V_Phase_TIM_Channel = TIM_CHANNEL_2,
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.W_Phase_TIM_Channel = TIM_CHANNEL_3,
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};
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BLDC_Init(MotorInterface);
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HAL_ADC_Start(&hadc);
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HAL_ADC_Start(&hadc);
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HAL_GPIO_WritePin(OC_TH_STBY1_GPIO_Port, OC_TH_STBY1_Pin, GPIO_PIN_SET);
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HAL_GPIO_WritePin(OC_TH_STBY1_GPIO_Port, OC_TH_STBY1_Pin, GPIO_PIN_SET);
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HAL_GPIO_WritePin(OC_TH_STBY2_GPIO_Port, OC_TH_STBY2_Pin, GPIO_PIN_SET);
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HAL_GPIO_WritePin(OC_TH_STBY2_GPIO_Port, OC_TH_STBY2_Pin, GPIO_PIN_SET);
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HAL_GPIO_WritePin(PWM_LSW_GPIO_Port, PWM_LSW_Pin, GPIO_PIN_SET);
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HAL_GPIO_WritePin(PWM_LSW_GPIO_Port, PWM_LSW_Pin, GPIO_PIN_SET);
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//HAL_Delay(2000);
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HAL_TIM_Base_Start_IT(&htim2);
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while (1)
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while (1)
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{
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{
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@@ -324,7 +334,7 @@ static void MX_TIM1_Init(void)
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sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_ENABLE;
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sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_ENABLE;
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sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_ENABLE;
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sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_ENABLE;
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sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
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sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
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sBreakDeadTimeConfig.DeadTime = 32;
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sBreakDeadTimeConfig.DeadTime = PWM_DEADTIME_COUNTS;
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sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
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sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
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sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
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sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
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sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
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sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
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@@ -449,7 +459,7 @@ static void MX_USART1_UART_Init(void)
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/* USER CODE END USART1_Init 1 */
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/* USER CODE END USART1_Init 1 */
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huart1.Instance = USART1;
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huart1.Instance = USART1;
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huart1.Init.BaudRate = 38400;
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huart1.Init.BaudRate = 115200;
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huart1.Init.WordLength = UART_WORDLENGTH_8B;
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huart1.Init.WordLength = UART_WORDLENGTH_8B;
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huart1.Init.StopBits = UART_STOPBITS_1;
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huart1.Init.StopBits = UART_STOPBITS_1;
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huart1.Init.Parity = UART_PARITY_NONE;
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huart1.Init.Parity = UART_PARITY_NONE;
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@@ -550,33 +560,15 @@ static void MX_GPIO_Init(void)
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void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) {
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void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) {
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static uint32_t int_count;
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if (htim->Instance == TIM2) {
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if (htim->Instance == TIM2) {
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int_count++;
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BLDC_Loop();
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static uint32_t seconds;
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if (int_count/1000u > seconds) {
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seconds = int_count/1000u;
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uint8_t txMsg1[20] = "";
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snprintf(txMsg1, sizeof(txMsg1), "IRQ: %8lu\n\0", int_count);
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HAL_UART_Transmit(&huart1, txMsg1, strlen(txMsg1), 100);
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}
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}
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}
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// static uint32_t loops;
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// if (HAL_GetTick()/1000 > loops) {
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// loops = HAL_GetTick()/1000;
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// uint8_t txMsg[20] = "";
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// snprintf(txMsg, sizeof(txMsg), "IRQ: %8lu\n\0", HAL_GetTick());
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// HAL_UART_Transmit(&huart1, txMsg, strlen(txMsg), 100);
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// }
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}
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}
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/* USER CODE END 4 */
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/* USER CODE END 4 */
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36
Core/Src/motor_controller.c
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36
Core/Src/motor_controller.c
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@@ -0,0 +1,36 @@
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#include <stdio.h>
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#include <stdint.h>
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#include "motor_controller.h"
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void BLDC_Init(Cont_Mot_Interface_TypeDef Interface) {
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HAL_TIM_PWM_Start(Interface.Driver_PWM_TIM, Interface.U_Phase_TIM_Channel);
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HAL_TIMEx_PWMN_Start(Interface.Driver_PWM_TIM, Interface.U_Phase_TIM_Channel);
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HAL_TIM_PWM_Start(Interface.Driver_PWM_TIM, Interface.V_Phase_TIM_Channel);
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||||||
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HAL_TIMEx_PWMN_Start(Interface.Driver_PWM_TIM, Interface.V_Phase_TIM_Channel);
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HAL_TIM_PWM_Start(Interface.Driver_PWM_TIM, Interface.W_Phase_TIM_Channel);
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HAL_TIMEx_PWMN_Start(Interface.Driver_PWM_TIM, Interface.W_Phase_TIM_Channel);
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}
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void BLDC_Loop() {
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static uint32_t int_count;
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int_count++;
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static uint32_t seconds;
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||||||
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if (int_count/1000u > seconds) {
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seconds = int_count/1000u;
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||||||
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||||||
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uint8_t txMsg1[20] = "";
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snprintf(txMsg1, sizeof(txMsg1), "IRQ: %8lu\n\0", int_count);
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||||||
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//HAL_UART_Transmit(&huart1, txMsg1, strlen(txMsg1), 100);
|
||||||
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//HAL_UART_Transmit_DMA(&huart1, txMsg1, strlen(txMsg1));
|
||||||
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||||||
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uint8_t txMsg2[20] = "";
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||||||
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//snprintf(txMsg2, sizeof(txMsg2), "CNT: %8lu\n\0", htim->Instance->CNT);
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||||||
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//HAL_UART_Transmit(&huart1, txMsg2, strlen(txMsg2), 100);
|
||||||
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//HAL_UART_Transmit_DMA(&huart1, txMsg2, strlen(txMsg2));
|
||||||
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|
||||||
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}
|
||||||
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|
||||||
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}
|
||||||
5
Makefile
5
Makefile
@@ -1,5 +1,5 @@
|
|||||||
##########################################################################################################################
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##########################################################################################################################
|
||||||
# File automatically-generated by tool: [projectgenerator] version: [4.7.0-B52] date: [Sat Oct 04 16:04:41 CDT 2025]
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# File automatically-generated by tool: [projectgenerator] version: [4.7.0-B52] date: [Sun Oct 05 13:27:16 CDT 2025]
|
||||||
##########################################################################################################################
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##########################################################################################################################
|
||||||
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|
||||||
# ------------------------------------------------
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# ------------------------------------------------
|
||||||
@@ -13,7 +13,7 @@
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|||||||
######################################
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######################################
|
||||||
# target
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# target
|
||||||
######################################
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######################################
|
||||||
TARGET = CustomCode
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TARGET = BLDC-Motor-Controller
|
||||||
|
|
||||||
|
|
||||||
######################################
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######################################
|
||||||
@@ -37,6 +37,7 @@ BUILD_DIR = build
|
|||||||
# C sources
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# C sources
|
||||||
C_SOURCES = \
|
C_SOURCES = \
|
||||||
Core/Src/main.c \
|
Core/Src/main.c \
|
||||||
|
Core/Src/motor_controller.c \
|
||||||
Core/Src/stm32f0xx_it.c \
|
Core/Src/stm32f0xx_it.c \
|
||||||
Core/Src/stm32f0xx_hal_msp.c \
|
Core/Src/stm32f0xx_hal_msp.c \
|
||||||
Core/Src/sysmem.c \
|
Core/Src/sysmem.c \
|
||||||
|
|||||||
207
STM32F031XX_FLASH.ld
Normal file
207
STM32F031XX_FLASH.ld
Normal file
@@ -0,0 +1,207 @@
|
|||||||
|
/*
|
||||||
|
******************************************************************************
|
||||||
|
**
|
||||||
|
|
||||||
|
** File : LinkerScript.ld
|
||||||
|
**
|
||||||
|
** Author : STM32CubeMX
|
||||||
|
**
|
||||||
|
** Abstract : Linker script for STM32F031C6Tx series
|
||||||
|
** 32Kbytes FLASH and 4Kbytes RAM
|
||||||
|
**
|
||||||
|
** Set heap size, stack size and stack location according
|
||||||
|
** to application requirements.
|
||||||
|
**
|
||||||
|
** Set memory bank area and size if external memory is used.
|
||||||
|
**
|
||||||
|
** Target : STMicroelectronics STM32
|
||||||
|
**
|
||||||
|
** Distribution: The file is distributed “as is,” without any warranty
|
||||||
|
** of any kind.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
** @attention
|
||||||
|
**
|
||||||
|
** <h2><center>© COPYRIGHT(c) 2025 STMicroelectronics</center></h2>
|
||||||
|
**
|
||||||
|
** Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
** are permitted provided that the following conditions are met:
|
||||||
|
** 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer.
|
||||||
|
** 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer in the documentation
|
||||||
|
** and/or other materials provided with the distribution.
|
||||||
|
** 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
** may be used to endorse or promote products derived from this software
|
||||||
|
** without specific prior written permission.
|
||||||
|
**
|
||||||
|
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Entry Point */
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
/* Highest address of the user mode stack */
|
||||||
|
_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of RAM */
|
||||||
|
/* Generate a link error if heap and stack don't fit into RAM */
|
||||||
|
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||||
|
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||||
|
|
||||||
|
/* Specify the memory areas */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 4K
|
||||||
|
FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 32K
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Define output sections */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* The startup code goes first into FLASH */
|
||||||
|
.isr_vector :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* The program code and other data goes into FLASH */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text) /* .text sections (code) */
|
||||||
|
*(.text*) /* .text* sections (code) */
|
||||||
|
*(.glue_7) /* glue arm to thumb code */
|
||||||
|
*(.glue_7t) /* glue thumb to arm code */
|
||||||
|
*(.eh_frame)
|
||||||
|
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .; /* define a global symbols at end of code */
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* Constant data goes into FLASH */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||||
|
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* used by the startup to initialize data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
|
||||||
|
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sdata = .; /* create a global symbol at data start */
|
||||||
|
*(.data) /* .data sections */
|
||||||
|
*(.data*) /* .data* sections */
|
||||||
|
*(.RamFunc) /* .RamFunc sections */
|
||||||
|
*(.RamFunc*) /* .RamFunc* sections */
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_edata = .; /* define a global symbol at data end */
|
||||||
|
} >RAM AT> FLASH
|
||||||
|
|
||||||
|
|
||||||
|
/* Uninitialized data section */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_sbss = .; /* define a global symbol at bss start */
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_ebss = .; /* define a global symbol at bss end */
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||||
|
._user_heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE ( end = . );
|
||||||
|
PROVIDE ( _end = . );
|
||||||
|
. = . + _Min_Heap_Size;
|
||||||
|
. = . + _Min_Stack_Size;
|
||||||
|
. = ALIGN(8);
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* Remove information from the standard libraries */
|
||||||
|
/DISCARD/ :
|
||||||
|
{
|
||||||
|
libc.a ( * )
|
||||||
|
libm.a ( * )
|
||||||
|
libgcc.a ( * )
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
264
startup_stm32f031x6.s
Executable file
264
startup_stm32f031x6.s
Executable file
@@ -0,0 +1,264 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file startup_stm32f031x6.s
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @brief STM32F031x4/STM32F031x6 devices vector table for GCC toolchain.
|
||||||
|
* This module performs:
|
||||||
|
* - Set the initial SP
|
||||||
|
* - Set the initial PC == Reset_Handler,
|
||||||
|
* - Set the vector table entries with the exceptions ISR address
|
||||||
|
* - Branches to main in the C library (which eventually
|
||||||
|
* calls main()).
|
||||||
|
* After Reset the Cortex-M0 processor is in Thread mode,
|
||||||
|
* priority is Privileged, and the Stack is set to Main.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* Copyright (c) 2016 STMicroelectronics.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* This software is licensed under terms that can be found in the LICENSE file
|
||||||
|
* in the root directory of this software component.
|
||||||
|
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
.syntax unified
|
||||||
|
.cpu cortex-m0
|
||||||
|
.fpu softvfp
|
||||||
|
.thumb
|
||||||
|
|
||||||
|
.global g_pfnVectors
|
||||||
|
.global Default_Handler
|
||||||
|
|
||||||
|
/* start address for the initialization values of the .data section.
|
||||||
|
defined in linker script */
|
||||||
|
.word _sidata
|
||||||
|
/* start address for the .data section. defined in linker script */
|
||||||
|
.word _sdata
|
||||||
|
/* end address for the .data section. defined in linker script */
|
||||||
|
.word _edata
|
||||||
|
/* start address for the .bss section. defined in linker script */
|
||||||
|
.word _sbss
|
||||||
|
/* end address for the .bss section. defined in linker script */
|
||||||
|
.word _ebss
|
||||||
|
|
||||||
|
.section .text.Reset_Handler
|
||||||
|
.weak Reset_Handler
|
||||||
|
.type Reset_Handler, %function
|
||||||
|
Reset_Handler:
|
||||||
|
ldr r0, =_estack
|
||||||
|
mov sp, r0 /* set stack pointer */
|
||||||
|
|
||||||
|
/* Call the clock system initialization function.*/
|
||||||
|
bl SystemInit
|
||||||
|
|
||||||
|
/* Copy the data segment initializers from flash to SRAM */
|
||||||
|
ldr r0, =_sdata
|
||||||
|
ldr r1, =_edata
|
||||||
|
ldr r2, =_sidata
|
||||||
|
movs r3, #0
|
||||||
|
b LoopCopyDataInit
|
||||||
|
|
||||||
|
CopyDataInit:
|
||||||
|
ldr r4, [r2, r3]
|
||||||
|
str r4, [r0, r3]
|
||||||
|
adds r3, r3, #4
|
||||||
|
|
||||||
|
LoopCopyDataInit:
|
||||||
|
adds r4, r0, r3
|
||||||
|
cmp r4, r1
|
||||||
|
bcc CopyDataInit
|
||||||
|
|
||||||
|
/* Zero fill the bss segment. */
|
||||||
|
ldr r2, =_sbss
|
||||||
|
ldr r4, =_ebss
|
||||||
|
movs r3, #0
|
||||||
|
b LoopFillZerobss
|
||||||
|
|
||||||
|
FillZerobss:
|
||||||
|
str r3, [r2]
|
||||||
|
adds r2, r2, #4
|
||||||
|
|
||||||
|
LoopFillZerobss:
|
||||||
|
cmp r2, r4
|
||||||
|
bcc FillZerobss
|
||||||
|
|
||||||
|
/* Call static constructors */
|
||||||
|
bl __libc_init_array
|
||||||
|
/* Call the application's entry point.*/
|
||||||
|
bl main
|
||||||
|
|
||||||
|
LoopForever:
|
||||||
|
b LoopForever
|
||||||
|
|
||||||
|
|
||||||
|
.size Reset_Handler, .-Reset_Handler
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor receives an
|
||||||
|
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||||
|
* the system state for examination by a debugger.
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
.section .text.Default_Handler,"ax",%progbits
|
||||||
|
Default_Handler:
|
||||||
|
Infinite_Loop:
|
||||||
|
b Infinite_Loop
|
||||||
|
.size Default_Handler, .-Default_Handler
|
||||||
|
/******************************************************************************
|
||||||
|
*
|
||||||
|
* The minimal vector table for a Cortex M0. Note that the proper constructs
|
||||||
|
* must be placed on this to ensure that it ends up at physical address
|
||||||
|
* 0x0000.0000.
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
.section .isr_vector,"a",%progbits
|
||||||
|
.type g_pfnVectors, %object
|
||||||
|
.size g_pfnVectors, .-g_pfnVectors
|
||||||
|
|
||||||
|
|
||||||
|
g_pfnVectors:
|
||||||
|
.word _estack
|
||||||
|
.word Reset_Handler
|
||||||
|
.word NMI_Handler
|
||||||
|
.word HardFault_Handler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word SVC_Handler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word PendSV_Handler
|
||||||
|
.word SysTick_Handler
|
||||||
|
.word WWDG_IRQHandler /* Window WatchDog */
|
||||||
|
.word PVD_IRQHandler /* PVD through EXTI Line detect */
|
||||||
|
.word RTC_IRQHandler /* RTC through the EXTI line */
|
||||||
|
.word FLASH_IRQHandler /* FLASH */
|
||||||
|
.word RCC_IRQHandler /* RCC */
|
||||||
|
.word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */
|
||||||
|
.word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */
|
||||||
|
.word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
|
||||||
|
.word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */
|
||||||
|
.word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */
|
||||||
|
.word ADC1_IRQHandler /* ADC1 */
|
||||||
|
.word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */
|
||||||
|
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||||
|
.word TIM2_IRQHandler /* TIM2 */
|
||||||
|
.word TIM3_IRQHandler /* TIM3 */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word TIM14_IRQHandler /* TIM14 */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word TIM16_IRQHandler /* TIM16 */
|
||||||
|
.word TIM17_IRQHandler /* TIM17 */
|
||||||
|
.word I2C1_IRQHandler /* I2C1 */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word SPI1_IRQHandler /* SPI1 */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word USART1_IRQHandler /* USART1 */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
*
|
||||||
|
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||||
|
* As they are weak aliases, any function with the same name will override
|
||||||
|
* this definition.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
.weak NMI_Handler
|
||||||
|
.thumb_set NMI_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak HardFault_Handler
|
||||||
|
.thumb_set HardFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SVC_Handler
|
||||||
|
.thumb_set SVC_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak PendSV_Handler
|
||||||
|
.thumb_set PendSV_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SysTick_Handler
|
||||||
|
.thumb_set SysTick_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDG_IRQHandler
|
||||||
|
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak PVD_IRQHandler
|
||||||
|
.thumb_set PVD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_IRQHandler
|
||||||
|
.thumb_set RTC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FLASH_IRQHandler
|
||||||
|
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RCC_IRQHandler
|
||||||
|
.thumb_set RCC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI0_1_IRQHandler
|
||||||
|
.thumb_set EXTI0_1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI2_3_IRQHandler
|
||||||
|
.thumb_set EXTI2_3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI4_15_IRQHandler
|
||||||
|
.thumb_set EXTI4_15_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel2_3_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel4_5_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC1_IRQHandler
|
||||||
|
.thumb_set ADC1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_BRK_UP_TRG_COM_IRQHandler
|
||||||
|
.thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_CC_IRQHandler
|
||||||
|
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM2_IRQHandler
|
||||||
|
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM3_IRQHandler
|
||||||
|
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM14_IRQHandler
|
||||||
|
.thumb_set TIM14_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM16_IRQHandler
|
||||||
|
.thumb_set TIM16_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM17_IRQHandler
|
||||||
|
.thumb_set TIM17_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_IRQHandler
|
||||||
|
.thumb_set I2C1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI1_IRQHandler
|
||||||
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART1_IRQHandler
|
||||||
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
Reference in New Issue
Block a user