279 lines
7.2 KiB
C
279 lines
7.2 KiB
C
/**
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* \file
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*
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* \brief Chip-specific generic clock management.
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*
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* Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="https://www.atmel.com/design-support/">Atmel Support</a>
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*/
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#ifndef CHIP_GENCLK_H_INCLUDED
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#define CHIP_GENCLK_H_INCLUDED
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#include <osc.h>
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#include <pll.h>
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/// @cond 0
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/**INDENT-OFF**/
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**INDENT-ON**/
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/// @endcond
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/**
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* \weakgroup genclk_group
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* @{
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*/
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//! \name Programmable Clock Identifiers (PCK)
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//@{
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#define GENCLK_PCK_0 0 //!< PCK0 ID
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#define GENCLK_PCK_1 1 //!< PCK1 ID
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#define GENCLK_PCK_2 2 //!< PCK2 ID
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//@}
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//! \name Programmable Clock Sources (PCK)
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//@{
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enum genclk_source {
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GENCLK_PCK_SRC_SLCK_RC = 0, //!< Internal 32kHz RC oscillator as PCK source clock
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GENCLK_PCK_SRC_SLCK_XTAL = 1, //!< External 32kHz crystal oscillator as PCK source clock
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GENCLK_PCK_SRC_SLCK_BYPASS = 2, //!< External 32kHz bypass oscillator as PCK source clock
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GENCLK_PCK_SRC_MAINCK_4M_RC = 3, //!< Internal 4MHz RC oscillator as PCK source clock
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GENCLK_PCK_SRC_MAINCK_8M_RC = 4, //!< Internal 8MHz RC oscillator as PCK source clock
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GENCLK_PCK_SRC_MAINCK_12M_RC = 5, //!< Internal 12MHz RC oscillator as PCK source clock
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GENCLK_PCK_SRC_MAINCK_XTAL = 6, //!< External crystal oscillator as PCK source clock
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GENCLK_PCK_SRC_MAINCK_BYPASS = 7, //!< External bypass oscillator as PCK source clock
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GENCLK_PCK_SRC_PLLACK = 8, //!< Use PLLACK as PCK source clock
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GENCLK_PCK_SRC_PLLBCK = 9, //!< Use PLLBCK as PCK source clock
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GENCLK_PCK_SRC_MCK = 10, //!< Use Master Clk as PCK source clock
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};
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//@}
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//! \name Programmable Clock Prescalers (PCK)
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//@{
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enum genclk_divider {
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GENCLK_PCK_PRES_1 = PMC_PCK_PRES_CLK_1, //!< Set PCK clock prescaler to 1
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GENCLK_PCK_PRES_2 = PMC_PCK_PRES_CLK_2, //!< Set PCK clock prescaler to 2
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GENCLK_PCK_PRES_4 = PMC_PCK_PRES_CLK_4, //!< Set PCK clock prescaler to 4
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GENCLK_PCK_PRES_8 = PMC_PCK_PRES_CLK_8, //!< Set PCK clock prescaler to 8
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GENCLK_PCK_PRES_16 = PMC_PCK_PRES_CLK_16, //!< Set PCK clock prescaler to 16
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GENCLK_PCK_PRES_32 = PMC_PCK_PRES_CLK_32, //!< Set PCK clock prescaler to 32
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GENCLK_PCK_PRES_64 = PMC_PCK_PRES_CLK_64, //!< Set PCK clock prescaler to 64
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};
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//@}
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struct genclk_config {
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uint32_t ctrl;
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};
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static inline void genclk_config_defaults(struct genclk_config *p_cfg,
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uint32_t ul_id)
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{
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ul_id = ul_id;
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p_cfg->ctrl = 0;
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}
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static inline void genclk_config_read(struct genclk_config *p_cfg,
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uint32_t ul_id)
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{
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p_cfg->ctrl = PMC->PMC_PCK[ul_id];
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}
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static inline void genclk_config_write(const struct genclk_config *p_cfg,
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uint32_t ul_id)
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{
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PMC->PMC_PCK[ul_id] = p_cfg->ctrl;
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}
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//! \name Programmable Clock Source and Prescaler configuration
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//@{
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static inline void genclk_config_set_source(struct genclk_config *p_cfg,
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enum genclk_source e_src)
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{
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p_cfg->ctrl &= (~PMC_PCK_CSS_Msk);
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switch (e_src) {
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case GENCLK_PCK_SRC_SLCK_RC:
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case GENCLK_PCK_SRC_SLCK_XTAL:
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case GENCLK_PCK_SRC_SLCK_BYPASS:
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p_cfg->ctrl |= (PMC_PCK_CSS_SLOW_CLK);
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break;
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case GENCLK_PCK_SRC_MAINCK_4M_RC:
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case GENCLK_PCK_SRC_MAINCK_8M_RC:
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case GENCLK_PCK_SRC_MAINCK_12M_RC:
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case GENCLK_PCK_SRC_MAINCK_XTAL:
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case GENCLK_PCK_SRC_MAINCK_BYPASS:
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p_cfg->ctrl |= (PMC_PCK_CSS_MAIN_CLK);
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break;
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case GENCLK_PCK_SRC_PLLACK:
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p_cfg->ctrl |= (PMC_PCK_CSS_PLLA_CLK);
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break;
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case GENCLK_PCK_SRC_PLLBCK:
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p_cfg->ctrl |= (PMC_PCK_CSS_UPLL_CLK);
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break;
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case GENCLK_PCK_SRC_MCK:
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p_cfg->ctrl |= (PMC_PCK_CSS_MCK);
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break;
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}
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}
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static inline void genclk_config_set_divider(struct genclk_config *p_cfg,
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uint32_t e_divider)
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{
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p_cfg->ctrl &= ~PMC_PCK_PRES_Msk;
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p_cfg->ctrl |= e_divider;
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}
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//@}
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static inline void genclk_enable(const struct genclk_config *p_cfg,
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uint32_t ul_id)
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{
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PMC->PMC_PCK[ul_id] = p_cfg->ctrl;
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pmc_enable_pck(ul_id);
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}
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static inline void genclk_disable(uint32_t ul_id)
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{
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pmc_disable_pck(ul_id);
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}
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static inline void genclk_enable_source(enum genclk_source e_src)
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{
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switch (e_src) {
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case GENCLK_PCK_SRC_SLCK_RC:
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if (!osc_is_ready(OSC_SLCK_32K_RC)) {
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osc_enable(OSC_SLCK_32K_RC);
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osc_wait_ready(OSC_SLCK_32K_RC);
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}
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break;
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case GENCLK_PCK_SRC_SLCK_XTAL:
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if (!osc_is_ready(OSC_SLCK_32K_XTAL)) {
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osc_enable(OSC_SLCK_32K_XTAL);
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osc_wait_ready(OSC_SLCK_32K_XTAL);
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}
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break;
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case GENCLK_PCK_SRC_SLCK_BYPASS:
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if (!osc_is_ready(OSC_SLCK_32K_BYPASS)) {
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osc_enable(OSC_SLCK_32K_BYPASS);
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osc_wait_ready(OSC_SLCK_32K_BYPASS);
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}
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break;
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case GENCLK_PCK_SRC_MAINCK_4M_RC:
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if (!osc_is_ready(OSC_MAINCK_4M_RC)) {
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osc_enable(OSC_MAINCK_4M_RC);
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osc_wait_ready(OSC_MAINCK_4M_RC);
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}
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break;
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case GENCLK_PCK_SRC_MAINCK_8M_RC:
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if (!osc_is_ready(OSC_MAINCK_8M_RC)) {
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osc_enable(OSC_MAINCK_8M_RC);
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osc_wait_ready(OSC_MAINCK_8M_RC);
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}
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break;
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case GENCLK_PCK_SRC_MAINCK_12M_RC:
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if (!osc_is_ready(OSC_MAINCK_12M_RC)) {
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osc_enable(OSC_MAINCK_12M_RC);
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osc_wait_ready(OSC_MAINCK_12M_RC);
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}
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break;
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case GENCLK_PCK_SRC_MAINCK_XTAL:
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if (!osc_is_ready(OSC_MAINCK_XTAL)) {
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osc_enable(OSC_MAINCK_XTAL);
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osc_wait_ready(OSC_MAINCK_XTAL);
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}
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break;
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case GENCLK_PCK_SRC_MAINCK_BYPASS:
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if (!osc_is_ready(OSC_MAINCK_BYPASS)) {
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osc_enable(OSC_MAINCK_BYPASS);
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osc_wait_ready(OSC_MAINCK_BYPASS);
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}
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break;
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#ifdef CONFIG_PLL0_SOURCE
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case GENCLK_PCK_SRC_PLLACK:
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pll_enable_config_defaults(0);
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break;
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#endif
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#ifdef CONFIG_PLL1_SOURCE
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case GENCLK_PCK_SRC_PLLBCK:
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pll_enable_config_defaults(1);
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break;
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#endif
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case GENCLK_PCK_SRC_MCK:
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break;
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default:
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Assert(false);
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break;
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}
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}
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//! @}
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/// @cond 0
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/**INDENT-OFF**/
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#ifdef __cplusplus
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}
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#endif
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/**INDENT-ON**/
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/// @endcond
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#endif /* CHIP_GENCLK_H_INCLUDED */
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