a5cf3a190c
* Fix mistake in gitignore file and add in missing core files. The missing leading slash on "lib" meant all folders names lib in the directory tree are ignored, rather than just the top level PlatformIO lib folder * Add LiquidCrystal Library and associated headers modified to compile.
131 lines
4.4 KiB
C
131 lines
4.4 KiB
C
/*----------------------------------------------------------------------------
|
|
* U S B - K e r n e l
|
|
*----------------------------------------------------------------------------
|
|
* Name: usbreg.h
|
|
* Purpose: USB Hardware Layer Definitions for NXP LPC Family MCUs
|
|
* Version: V1.20
|
|
*----------------------------------------------------------------------------
|
|
* This software is supplied "AS IS" without any warranties, express,
|
|
* implied or statutory, including but not limited to the implied
|
|
* warranties of fitness for purpose, satisfactory quality and
|
|
* noninfringement. Keil extends you a royalty-free right to reproduce
|
|
* and distribute executable files created using this software for use
|
|
* on NXP Semiconductors LPC family microcontroller devices only. Nothing
|
|
* else gives you the right to use this software.
|
|
*
|
|
* Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
|
|
*---------------------------------------------------------------------------*/
|
|
|
|
#ifndef __USBREG_H
|
|
#define __USBREG_H
|
|
|
|
/* Device Interrupt Bit Definitions */
|
|
#define FRAME_INT 0x00000001
|
|
#define EP_FAST_INT 0x00000002
|
|
#define EP_SLOW_INT 0x00000004
|
|
#define DEV_STAT_INT 0x00000008
|
|
#define CCEMTY_INT 0x00000010
|
|
#define CDFULL_INT 0x00000020
|
|
#define RxENDPKT_INT 0x00000040
|
|
#define TxENDPKT_INT 0x00000080
|
|
#define EP_RLZED_INT 0x00000100
|
|
#define ERR_INT 0x00000200
|
|
|
|
/* Rx & Tx Packet Length Definitions */
|
|
#define PKT_LNGTH_MASK 0x000003FF
|
|
#define PKT_DV 0x00000400
|
|
#define PKT_RDY 0x00000800
|
|
|
|
/* USB Control Definitions */
|
|
#define CTRL_RD_EN 0x00000001
|
|
#define CTRL_WR_EN 0x00000002
|
|
|
|
/* Command Codes */
|
|
#define CMD_SET_ADDR 0x00D00500
|
|
#define CMD_CFG_DEV 0x00D80500
|
|
#define CMD_SET_MODE 0x00F30500
|
|
#define CMD_RD_FRAME 0x00F50500
|
|
#define DAT_RD_FRAME 0x00F50200
|
|
#define CMD_RD_TEST 0x00FD0500
|
|
#define DAT_RD_TEST 0x00FD0200
|
|
#define CMD_SET_DEV_STAT 0x00FE0500
|
|
#define CMD_GET_DEV_STAT 0x00FE0500
|
|
#define DAT_GET_DEV_STAT 0x00FE0200
|
|
#define CMD_GET_ERR_CODE 0x00FF0500
|
|
#define DAT_GET_ERR_CODE 0x00FF0200
|
|
#define CMD_RD_ERR_STAT 0x00FB0500
|
|
#define DAT_RD_ERR_STAT 0x00FB0200
|
|
#define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16))
|
|
#define CMD_SEL_EP(x) (0x00000500 | ((x) << 16))
|
|
#define DAT_SEL_EP(x) (0x00000200 | ((x) << 16))
|
|
#define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16))
|
|
#define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16))
|
|
#define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16))
|
|
#define CMD_CLR_BUF 0x00F20500
|
|
#define DAT_CLR_BUF 0x00F20200
|
|
#define CMD_VALID_BUF 0x00FA0500
|
|
|
|
/* Device Address Register Definitions */
|
|
#define DEV_ADDR_MASK 0x7F
|
|
#define DEV_EN 0x80
|
|
|
|
/* Device Configure Register Definitions */
|
|
#define CONF_DVICE 0x01
|
|
|
|
/* Device Mode Register Definitions */
|
|
#define AP_CLK 0x01
|
|
#define INAK_CI 0x02
|
|
#define INAK_CO 0x04
|
|
#define INAK_II 0x08
|
|
#define INAK_IO 0x10
|
|
#define INAK_BI 0x20
|
|
#define INAK_BO 0x40
|
|
|
|
/* Device Status Register Definitions */
|
|
#define DEV_CON 0x01
|
|
#define DEV_CON_CH 0x02
|
|
#define DEV_SUS 0x04
|
|
#define DEV_SUS_CH 0x08
|
|
#define DEV_RST 0x10
|
|
|
|
/* Error Code Register Definitions */
|
|
#define ERR_EC_MASK 0x0F
|
|
#define ERR_EA 0x10
|
|
|
|
/* Error Status Register Definitions */
|
|
#define ERR_PID 0x01
|
|
#define ERR_UEPKT 0x02
|
|
#define ERR_DCRC 0x04
|
|
#define ERR_TIMOUT 0x08
|
|
#define ERR_EOP 0x10
|
|
#define ERR_B_OVRN 0x20
|
|
#define ERR_BTSTF 0x40
|
|
#define ERR_TGL 0x80
|
|
|
|
/* Endpoint Select Register Definitions */
|
|
#define EP_SEL_F 0x01
|
|
#define EP_SEL_ST 0x02
|
|
#define EP_SEL_STP 0x04
|
|
#define EP_SEL_PO 0x08
|
|
#define EP_SEL_EPN 0x10
|
|
#define EP_SEL_B_1_FULL 0x20
|
|
#define EP_SEL_B_2_FULL 0x40
|
|
|
|
/* Endpoint Status Register Definitions */
|
|
#define EP_STAT_ST 0x01
|
|
#define EP_STAT_DA 0x20
|
|
#define EP_STAT_RF_MO 0x40
|
|
#define EP_STAT_CND_ST 0x80
|
|
|
|
/* Clear Buffer Register Definitions */
|
|
#define CLR_BUF_PO 0x01
|
|
|
|
|
|
/* DMA Interrupt Bit Definitions */
|
|
#define EOT_INT 0x01
|
|
#define NDD_REQ_INT 0x02
|
|
#define SYS_ERR_INT 0x04
|
|
|
|
|
|
#endif /* __USBREG_H */
|