230 lines
8.4 KiB
C
230 lines
8.4 KiB
C
/**
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* \file
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*
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* \brief Chip-specific system clock management functions.
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*
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* Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="https://www.atmel.com/design-support/">Atmel Support</a>
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*/
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#ifndef CHIP_SYSCLK_H_INCLUDED
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#define CHIP_SYSCLK_H_INCLUDED
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#include "osc.h"
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#include "pll.h"
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/**
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* \page sysclk_quickstart Quick Start Guide for the System Clock Management service (SAM3A)
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*
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* This is the quick start guide for the \ref sysclk_group "System Clock Management"
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* service, with step-by-step instructions on how to configure and use the service for
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* specific use cases.
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*
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* \section sysclk_quickstart_usecases System Clock Management use cases
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* - \ref sysclk_quickstart_basic
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*
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* \section sysclk_quickstart_basic Basic usage of the System Clock Management service
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* This section will present a basic use case for the System Clock Management service.
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* This use case will configure the main system clock to 84MHz, using an internal PLL
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* module to multiply the frequency of a crystal attached to the microcontroller.
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*
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* \subsection sysclk_quickstart_use_case_1_prereq Prerequisites
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* - None
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*
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* \subsection sysclk_quickstart_use_case_1_setup_steps Initialization code
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* Add to the application initialization code:
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* \code
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sysclk_init();
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\endcode
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*
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* \subsection sysclk_quickstart_use_case_1_setup_steps_workflow Workflow
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* -# Configure the system clocks according to the settings in conf_clock.h:
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* \code sysclk_init(); \endcode
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*
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* \subsection sysclk_quickstart_use_case_1_example_code Example code
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* Add or uncomment the following in your conf_clock.h header file, commenting out all other
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* definitions of the same symbol(s):
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* \code
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#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK
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// Fpll0 = (Fclk * PLL_mul) / PLL_div
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#define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL
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#define CONFIG_PLL0_MUL (84000000UL / BOARD_FREQ_MAINCK_XTAL)
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#define CONFIG_PLL0_DIV 1
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// Fbus = Fsys / BUS_div
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#define CONFIG_SYSCLK_PRES SYSCLK_PRES_1
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\endcode
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*
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* \subsection sysclk_quickstart_use_case_1_example_workflow Workflow
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* -# Configure the main system clock to use the output of the PLL module as its source:
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* \code #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK \endcode
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* -# Configure the PLL module to use the fast external fast crystal oscillator as its source:
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* \code #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL \endcode
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* -# Configure the PLL module to multiply the external fast crystal oscillator frequency up to 84MHz:
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* \code
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#define CONFIG_PLL0_MUL (84000000UL / BOARD_FREQ_MAINCK_XTAL)
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#define CONFIG_PLL0_DIV 1
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\endcode
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* \note For user boards, \c BOARD_FREQ_MAINCK_XTAL should be defined in the board \c conf_board.h configuration
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* file as the frequency of the fast crystal attached to the microcontroller.
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* -# Configure the main clock to run at the full 84MHz, disable scaling of the main system clock speed:
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* \code
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#define CONFIG_SYSCLK_PRES SYSCLK_PRES_1
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\endcode
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* \note Some dividers are powers of two, while others are integer division factors. Refer to the
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* formulas in the conf_clock.h template commented above each division define.
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*/
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/// @cond 0
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/**INDENT-OFF**/
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**INDENT-ON**/
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/// @endcond
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/**
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* \weakgroup sysclk_group
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* @{
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*/
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//! \name Configuration Symbols
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//@{
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/**
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* \def CONFIG_SYSCLK_SOURCE
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* \brief Initial/static main system clock source
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*
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* The main system clock will be configured to use this clock during
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* initialization.
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*/
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#ifndef CONFIG_SYSCLK_SOURCE
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# define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC
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#endif
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/**
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* \def CONFIG_SYSCLK_PRES
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* \brief Initial CPU clock divider (mck)
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*
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* The MCK will run at
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* \f[
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* f_{MCK} = \frac{f_{sys}}{\mathrm{CONFIG\_SYSCLK\_PRES}}\,\mbox{Hz}
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* \f]
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* after initialization.
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*/
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#ifndef CONFIG_SYSCLK_PRES
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# define CONFIG_SYSCLK_PRES 0
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#endif
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//@}
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//! \name Master Clock Sources (MCK)
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//@{
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#define SYSCLK_SRC_SLCK_RC 0 //!< Internal 32kHz RC oscillator as master source clock
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#define SYSCLK_SRC_SLCK_XTAL 1 //!< External 32kHz crystal oscillator as master source clock
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#define SYSCLK_SRC_SLCK_BYPASS 2 //!< External 32kHz bypass oscillator as master source clock
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#define SYSCLK_SRC_MAINCK_4M_RC 3 //!< Internal 4MHz RC oscillator as master source clock
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#define SYSCLK_SRC_MAINCK_8M_RC 4 //!< Internal 8MHz RC oscillator as master source clock
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#define SYSCLK_SRC_MAINCK_12M_RC 5 //!< Internal 12MHz RC oscillator as master source clock
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#define SYSCLK_SRC_MAINCK_XTAL 6 //!< External crystal oscillator as master source clock
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#define SYSCLK_SRC_MAINCK_BYPASS 7 //!< External bypass oscillator as master source clock
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#define SYSCLK_SRC_PLLACK 8 //!< Use PLLACK as master source clock
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#define SYSCLK_SRC_UPLLCK 9 //!< Use UPLLCK as master source clock
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//@}
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//! \name Master Clock Prescalers (MCK)
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//@{
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#define SYSCLK_PRES_1 PMC_MCKR_PRES_CLK_1 //!< Set master clock prescaler to 1
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#define SYSCLK_PRES_2 PMC_MCKR_PRES_CLK_2 //!< Set master clock prescaler to 2
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#define SYSCLK_PRES_4 PMC_MCKR_PRES_CLK_4 //!< Set master clock prescaler to 4
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#define SYSCLK_PRES_8 PMC_MCKR_PRES_CLK_8 //!< Set master clock prescaler to 8
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#define SYSCLK_PRES_16 PMC_MCKR_PRES_CLK_16 //!< Set master clock prescaler to 16
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#define SYSCLK_PRES_32 PMC_MCKR_PRES_CLK_32 //!< Set master clock prescaler to 32
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#define SYSCLK_PRES_64 PMC_MCKR_PRES_CLK_64 //!< Set master clock prescaler to 64
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#define SYSCLK_PRES_3 PMC_MCKR_PRES_CLK_3 //!< Set master clock prescaler to 3
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//@}
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//! \name USB Clock Sources
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//@{
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#define USBCLK_SRC_PLL0 0 //!< Use PLLA
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#define USBCLK_SRC_UPLL 1 //!< Use UPLL
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//@}
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/**
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* \def CONFIG_USBCLK_SOURCE
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* \brief Configuration symbol for the USB generic clock source
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*
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* Sets the clock source to use for the USB. The source must also be properly
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* configured.
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*
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* Define this to one of the \c USBCLK_SRC_xxx settings. Leave it undefined if
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* USB is not required.
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*/
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#ifdef __DOXYGEN__
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# define CONFIG_USBCLK_SOURCE
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#endif
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/**
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* \def CONFIG_USBCLK_DIV
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* \brief Configuration symbol for the USB generic clock divider setting
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*
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* Sets the clock division for the USB generic clock. If a USB clock source is
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* selected with CONFIG_USBCLK_SOURCE, this configuration symbol must also be
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* defined.
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*/
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#ifdef __DOXYGEN__
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# define CONFIG_USBCLK_DIV
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#endif
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extern void sysclk_enable_usb(void);
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extern void sysclk_disable_usb(void);
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//! @}
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/// @cond 0
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/**INDENT-OFF**/
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#ifdef __cplusplus
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}
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#endif
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/**INDENT-ON**/
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/// @endcond
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#endif /* CHIP_SYSCLK_H_INCLUDED */
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