Commit Graph

19 Commits

Author SHA1 Message Date
Scott Lahteine
64f007580b Fix some header comments 2018-07-17 19:50:24 -05:00
Scott Lahteine
d05e832f29 Add STM32F1 support for SD-based EEPROM 2018-07-06 23:45:47 -05:00
Scott Lahteine
99591dc20c
Filter endstops state at all times (#11066) 2018-06-21 20:14:16 -05:00
etagle
a215725df6 Fix stepper pulse timing
Always honor minimum period on stepper pulse generation, and fix timing calculations

Signed-off-by: etagle <ejtagle@hotmail.com>
2018-06-12 21:34:24 -05:00
Scott Lahteine
cf53e502a2 No need to set input after attachInterrupt 2018-06-12 18:43:11 -05:00
Karl Andersson
e0276d2f32 Official STMicroelectronics Arduino Core STM32F4 HAL compatibility (#11006) 2018-06-12 18:38:00 -05:00
Scott Lahteine
4dbec774b5 HAL_*_TIMER_RATE => *_TIMER_RATE 2018-06-12 16:39:12 -05:00
Scott Lahteine
a426986df8
Ensure pins set to INPUT after attachInterrupt (#10928) 2018-06-06 20:59:08 -05:00
Scott Lahteine
c685c7b7dd STM32F4: All pins can do PWM 2018-06-03 04:30:15 -05:00
Eduardo José Tagle
d3c02410a8 [2.0.x] Small assorted collection of fixes and improvements (#10911)
* Misc fixes and improvements

- Get rid of most critical sections on the Serial port drivers for AVR and DUE. Proper usage of FIFOs should allow interrupts to stay enabled without harm to queuing and dequeuing.
  Also, with 8-bit indices (for AVR) and up to 32-bit indices (for ARM), there is no need to protect reads and writes to those indices.
- Simplify the XON/XOFF logic quite a bit. Much cleaner now (both for AVR and ARM)
- Prevent a race condition (edge case) that could happen when estimating the proper value for the stepper timer (by reading it) and writing the calculated value for the time to the next ISR by disabling interrupts in those critical and small sections of the code - The problem could lead to lost steps.
- Fix dual endstops not properly homing bug (maybe).

* Set position immediately when possible
2018-06-01 19:02:22 -05:00
etagle
569df3fc0c Fix interrupt-based endstop detection
- Also implemented real endstop reading on interrupt.
2018-05-20 07:10:24 -05:00
etagle
0566badcef Add memory barrier, optimal interrupt on-off
Disabling an ISR on ARM has 3 instructions of latency. A Memory barrier is REQUIRED to ensure proper and predictable disabling. Memory barriers are expensive, so avoid disabling if already disabled (See https://mcuoneclipse.com/2015/10/16/nvic-disabling-interrupts-on-arm-cortex-m-and-the-need-for-a-memory-barrier-instruction/)
2018-05-20 02:39:34 -05:00
Scott Lahteine
37b15fe4cf Reorder HAL timer header items 2018-05-13 16:50:39 -05:00
Scott Lahteine
456cf971af HAL FastIO cleanup and fixes 2018-04-26 00:40:16 -05:00
Scott Lahteine
a3ce8a3fcd Add sanity checks for EMERGENCY_PARSER 2018-04-24 09:24:26 -05:00
Eduardo José Tagle
0c428a66d9 Proper AVR preemptive interrupt handling (#10496)
Also simplify logic on all ARM-based interrupts. Now, it is REQUIRED to properly configure interrupt priority. USART should have highest priority, followed by Stepper, and then all others.
2018-04-23 22:05:07 -05:00
Scott Lahteine
f423e54f77 Strip trailing spaces 2018-04-23 18:00:43 -05:00
Scott Lahteine
dea686cf55
Define short pin names in fastio for STM32 (#10461) 2018-04-20 14:54:35 -05:00
Karl Andersson
428c54f2ad [2.0.x] HAL for STM32F4 (#10434) 2018-04-17 17:33:29 -05:00