5 Commits

Author	SHA1	Message	Date
etagle	0566badcef	Add memory barrier, optimal interrupt on-off ... Disabling an ISR on ARM has 3 instructions of latency. A Memory barrier is REQUIRED to ensure proper and predictable disabling. Memory barriers are expensive, so avoid disabling if already disabled (See https://mcuoneclipse.com/2015/10/16/nvic-disabling-interrupts-on-arm-cortex-m-and-the-need-for-a-memory-barrier-instruction/)	2018-05-20 02:39:34 -05:00
Eduardo José Tagle	97e8a6ebd9	Various fixes for DUE... (#10152) ... - Watchdog reset during SD Card initialization. - Move `DebugMonitor` to `DebugMonitor_Due.cpp`. - Since the watchdog is enabled on boot do extra resets during init. - Have `thermalManager` do watchdog reset before its ISR starts to prevent reset. - Ensure that timers are stopped before reprogramming them to address tone issues. - Improve SAM3XE reset when reflashed through the native port.	2018-03-21 19:04:45 -05:00
Scott Lahteine	c2b1d51f16	HAL whitespace and style cleanup	2017-09-27 10:55:36 -05:00
Scott Lahteine	54326fb06a	HAL updates	2017-09-21 15:52:17 -05:00
Christopher Pepper	cfef925559	HAL for DUE architecture	2017-08-31 18:15:07 -05:00