etagle
569df3fc0c
Fix interrupt-based endstop detection
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- Also implemented real endstop reading on interrupt.
2018-05-20 07:10:24 -05:00
etagle
0566badcef
Add memory barrier, optimal interrupt on-off
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Disabling an ISR on ARM has 3 instructions of latency. A Memory barrier is REQUIRED to ensure proper and predictable disabling. Memory barriers are expensive, so avoid disabling if already disabled (See https://mcuoneclipse.com/2015/10/16/nvic-disabling-interrupts-on-arm-cortex-m-and-the-need-for-a-memory-barrier-instruction/ )
2018-05-20 02:39:34 -05:00
Scott Lahteine
37b15fe4cf
Reorder HAL timer header items
2018-05-13 16:50:39 -05:00
Scott Lahteine
456cf971af
HAL FastIO cleanup and fixes
2018-04-26 00:40:16 -05:00
Scott Lahteine
a3ce8a3fcd
Add sanity checks for EMERGENCY_PARSER
2018-04-24 09:24:26 -05:00
Eduardo José Tagle
0c428a66d9
Proper AVR preemptive interrupt handling ( #10496 )
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Also simplify logic on all ARM-based interrupts. Now, it is REQUIRED to properly configure interrupt priority. USART should have highest priority, followed by Stepper, and then all others.
2018-04-23 22:05:07 -05:00
Scott Lahteine
f423e54f77
Strip trailing spaces
2018-04-23 18:00:43 -05:00
Scott Lahteine
dea686cf55
Define short pin names in fastio for STM32 ( #10461 )
2018-04-20 14:54:35 -05:00
Karl Andersson
428c54f2ad
[2.0.x] HAL for STM32F4 ( #10434 )
2018-04-17 17:33:29 -05:00
