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Merge pull request #9197 from p3p/pr_bf2_operation_freemem

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[2.0.x] LPC1768: Free up some RAM
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Scott Lahteine 2018-01-19 22:35:45 -06:00 committed by GitHub
commit f2ea8a0529
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GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 108 additions and 155 deletions
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8
Marlin/src/HAL/HAL_LPC1768/HAL.h
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@ -78,13 +78,17 @@ extern HalSerial usb_serial;
#if SERIAL_PORT == -1 #if SERIAL_PORT == -1
#define MYSERIAL0 usb_serial #define MYSERIAL0 usb_serial
#elif SERIAL_PORT == 0 #elif SERIAL_PORT == 0
extern HardwareSerial Serial;
#define MYSERIAL0 Serial #define MYSERIAL0 Serial
#elif SERIAL_PORT == 1 #elif SERIAL_PORT == 1
extern HardwareSerial Serial1;
#define MYSERIAL0 Serial1 #define MYSERIAL0 Serial1
#elif SERIAL_PORT == 2 #elif SERIAL_PORT == 2
extern HardwareSerial Serial2;
#define MYSERIAL0 Serial2 #define MYSERIAL0 Serial2
#elif SERIAL_PORT == 3 #elif SERIAL_PORT == 3
#define MYSERIAL0 Serial3 #define MYSERIAL0 Serial3
extern HardwareSerial Serial3;
#endif #endif
#ifdef SERIAL_PORT_2 #ifdef SERIAL_PORT_2
@ -97,12 +101,16 @@ extern HalSerial usb_serial;
#if SERIAL_PORT_2 == -1 #if SERIAL_PORT_2 == -1
#define MYSERIAL1 usb_serial #define MYSERIAL1 usb_serial
#elif SERIAL_PORT_2 == 0 #elif SERIAL_PORT_2 == 0
extern HardwareSerial Serial;
#define MYSERIAL1 Serial #define MYSERIAL1 Serial
#elif SERIAL_PORT_2 == 1 #elif SERIAL_PORT_2 == 1
extern HardwareSerial Serial1;
#define MYSERIAL1 Serial1 #define MYSERIAL1 Serial1
#elif SERIAL_PORT_2 == 2 #elif SERIAL_PORT_2 == 2
extern HardwareSerial Serial2;
#define MYSERIAL1 Serial2 #define MYSERIAL1 Serial2
#elif SERIAL_PORT_2 == 3 #elif SERIAL_PORT_2 == 3
extern HardwareSerial Serial3;
#define MYSERIAL1 Serial3 #define MYSERIAL1 Serial3
#endif #endif
#else #else

208
Marlin/src/HAL/HAL_LPC1768/HardwareSerial.cpp
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@ -25,10 +25,15 @@
#include "../../inc/MarlinConfig.h" #include "../../inc/MarlinConfig.h"
#include "HardwareSerial.h" #include "HardwareSerial.h"
HardwareSerial Serial = HardwareSerial(LPC_UART0); #if SERIAL_PORT == 0 || SERIAL_PORT_2 == 0
HardwareSerial Serial1 = HardwareSerial((LPC_UART_TypeDef *) LPC_UART1); HardwareSerial Serial = HardwareSerial(LPC_UART0);
HardwareSerial Serial2 = HardwareSerial(LPC_UART2); #elif SERIAL_PORT == 1 || SERIAL_PORT_2 == 1
HardwareSerial Serial3 = HardwareSerial(LPC_UART3); HardwareSerial Serial1 = HardwareSerial((LPC_UART_TypeDef *) LPC_UART1);
#elif SERIAL_PORT == 2 || SERIAL_PORT_2 == 2
HardwareSerial Serial2 = HardwareSerial(LPC_UART2);
#elif SERIAL_PORT == 3 || SERIAL_PORT_2 == 3
HardwareSerial Serial3 = HardwareSerial(LPC_UART3);
#endif
void HardwareSerial::begin(uint32_t baudrate) { void HardwareSerial::begin(uint32_t baudrate) {
@ -37,9 +42,7 @@ void HardwareSerial::begin(uint32_t baudrate) {
UART_FIFO_CFG_Type FIFOConfig; UART_FIFO_CFG_Type FIFOConfig;
if (UARTx == LPC_UART0) { if (UARTx == LPC_UART0) {
/* // Initialize UART0 pin connect
* Initialize UART0 pin connect
*/
PinCfg.Funcnum = 1; PinCfg.Funcnum = 1;
PinCfg.OpenDrain = 0; PinCfg.OpenDrain = 0;
PinCfg.Pinmode = 0; PinCfg.Pinmode = 0;
@ -48,11 +51,8 @@ void HardwareSerial::begin(uint32_t baudrate) {
PINSEL_ConfigPin(&PinCfg); PINSEL_ConfigPin(&PinCfg);
PinCfg.Pinnum = 3; PinCfg.Pinnum = 3;
PINSEL_ConfigPin(&PinCfg); PINSEL_ConfigPin(&PinCfg);
} } else if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1) {
else if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1) { // Initialize UART1 pin connect
/*
* Initialize UART1 pin connect
*/
PinCfg.Funcnum = 1; PinCfg.Funcnum = 1;
PinCfg.OpenDrain = 0; PinCfg.OpenDrain = 0;
PinCfg.Pinmode = 0; PinCfg.Pinmode = 0;
@ -61,11 +61,8 @@ void HardwareSerial::begin(uint32_t baudrate) {
PINSEL_ConfigPin(&PinCfg); PINSEL_ConfigPin(&PinCfg);
PinCfg.Pinnum = 16; PinCfg.Pinnum = 16;
PINSEL_ConfigPin(&PinCfg); PINSEL_ConfigPin(&PinCfg);
} } else if (UARTx == LPC_UART2) {
else if (UARTx == LPC_UART2) { // Initialize UART2 pin connect
/*
* Initialize UART2 pin connect
*/
PinCfg.Funcnum = 1; PinCfg.Funcnum = 1;
PinCfg.OpenDrain = 0; PinCfg.OpenDrain = 0;
PinCfg.Pinmode = 0; PinCfg.Pinmode = 0;
@ -74,11 +71,8 @@ void HardwareSerial::begin(uint32_t baudrate) {
PINSEL_ConfigPin(&PinCfg); PINSEL_ConfigPin(&PinCfg);
PinCfg.Pinnum = 11; PinCfg.Pinnum = 11;
PINSEL_ConfigPin(&PinCfg); PINSEL_ConfigPin(&PinCfg);
} } else if (UARTx == LPC_UART3) {
else if (UARTx == LPC_UART3) { // Initialize UART2 pin connect
/*
* Initialize UART2 pin connect
*/
PinCfg.Funcnum = 1; PinCfg.Funcnum = 1;
PinCfg.OpenDrain = 0; PinCfg.OpenDrain = 0;
PinCfg.Pinmode = 0; PinCfg.Pinmode = 0;
@ -114,14 +108,10 @@ void HardwareSerial::begin(uint32_t baudrate) {
UART_IntConfig(UARTx, UART_INTCFG_RBR, ENABLE); UART_IntConfig(UARTx, UART_INTCFG_RBR, ENABLE);
UART_IntConfig(UARTx, UART_INTCFG_RLS, ENABLE); UART_IntConfig(UARTx, UART_INTCFG_RLS, ENABLE);
if (UARTx == LPC_UART0) if (UARTx == LPC_UART0) NVIC_EnableIRQ(UART0_IRQn);
NVIC_EnableIRQ(UART0_IRQn); else if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1) NVIC_EnableIRQ(UART1_IRQn);
else if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1) else if (UARTx == LPC_UART2) NVIC_EnableIRQ(UART2_IRQn);
NVIC_EnableIRQ(UART1_IRQn); else if (UARTx == LPC_UART3) NVIC_EnableIRQ(UART3_IRQn);
else if (UARTx == LPC_UART2)
NVIC_EnableIRQ(UART2_IRQn);
else if (UARTx == LPC_UART3)
NVIC_EnableIRQ(UART3_IRQn);
RxQueueWritePos = RxQueueReadPos = 0; RxQueueWritePos = RxQueueReadPos = 0;
#if TX_BUFFER_SIZE > 0 #if TX_BUFFER_SIZE > 0
@ -132,14 +122,14 @@ void HardwareSerial::begin(uint32_t baudrate) {
int HardwareSerial::peek() { int HardwareSerial::peek() {
int byte = -1; int byte = -1;
/* Temporarily lock out UART receive interrupts during this read so the UART receive // Temporarily lock out UART receive interrupts during this read so the UART receive
interrupt won't cause problems with the index values */ // interrupt won't cause problems with the index values
UART_IntConfig(UARTx, UART_INTCFG_RBR, DISABLE); UART_IntConfig(UARTx, UART_INTCFG_RBR, DISABLE);
if (RxQueueReadPos != RxQueueWritePos) if (RxQueueReadPos != RxQueueWritePos)
byte = RxBuffer[RxQueueReadPos]; byte = RxBuffer[RxQueueReadPos];
/* Re-enable UART interrupts */ // Re-enable UART interrupts
UART_IntConfig(UARTx, UART_INTCFG_RBR, ENABLE); UART_IntConfig(UARTx, UART_INTCFG_RBR, ENABLE);
return byte; return byte;
@ -148,8 +138,8 @@ int HardwareSerial::peek() {
int HardwareSerial::read() { int HardwareSerial::read() {
int byte = -1; int byte = -1;
/* Temporarily lock out UART receive interrupts during this read so the UART receive // Temporarily lock out UART receive interrupts during this read so the UART receive
interrupt won't cause problems with the index values */ // interrupt won't cause problems with the index values
UART_IntConfig(UARTx, UART_INTCFG_RBR, DISABLE); UART_IntConfig(UARTx, UART_INTCFG_RBR, DISABLE);
if (RxQueueReadPos != RxQueueWritePos) { if (RxQueueReadPos != RxQueueWritePos) {
@ -157,53 +147,52 @@ int HardwareSerial::read() {
RxQueueReadPos = (RxQueueReadPos + 1) % RX_BUFFER_SIZE; RxQueueReadPos = (RxQueueReadPos + 1) % RX_BUFFER_SIZE;
} }
/* Re-enable UART interrupts */ // Re-enable UART interrupts
UART_IntConfig(UARTx, UART_INTCFG_RBR, ENABLE); UART_IntConfig(UARTx, UART_INTCFG_RBR, ENABLE);
return byte; return byte;
} }
size_t HardwareSerial::write(uint8_t send) { size_t HardwareSerial::write(uint8_t send) {
#if TX_BUFFER_SIZE > 0 #if TX_BUFFER_SIZE > 0
size_t bytes = 0; size_t bytes = 0;
uint32_t fifolvl = 0; uint32_t fifolvl = 0;
/* If the Tx Buffer is full, wait for space to clear */ // If the Tx Buffer is full, wait for space to clear
if ((TxQueueWritePos+1) % TX_BUFFER_SIZE == TxQueueReadPos) flushTX(); if ((TxQueueWritePos+1) % TX_BUFFER_SIZE == TxQueueReadPos) flushTX();
/* Temporarily lock out UART transmit interrupts during this read so the UART transmit interrupt won't // Temporarily lock out UART transmit interrupts during this read so the UART transmit interrupt won't
cause problems with the index values */ // cause problems with the index values
UART_IntConfig(UARTx, UART_INTCFG_THRE, DISABLE); UART_IntConfig(UARTx, UART_INTCFG_THRE, DISABLE);
/* LPC17xx.h incorrectly defines FIFOLVL as a uint8_t, when it's actually a 32-bit register */ // LPC17xx.h incorrectly defines FIFOLVL as a uint8_t, when it's actually a 32-bit register
if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1) if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1) {
fifolvl = *(reinterpret_cast<volatile uint32_t *>(&((LPC_UART1_TypeDef *) UARTx)->FIFOLVL)); fifolvl = *(reinterpret_cast<volatile uint32_t *>(&((LPC_UART1_TypeDef *) UARTx)->FIFOLVL));
else } else fifolvl = *(reinterpret_cast<volatile uint32_t *>(&UARTx->FIFOLVL));
fifolvl = *(reinterpret_cast<volatile uint32_t *>(&UARTx->FIFOLVL));
/* If the queue is empty and there's space in the FIFO, immediately send the byte */ // If the queue is empty and there's space in the FIFO, immediately send the byte
if (TxQueueWritePos == TxQueueReadPos && fifolvl < UART_TX_FIFO_SIZE) { if (TxQueueWritePos == TxQueueReadPos && fifolvl < UART_TX_FIFO_SIZE) {
bytes = UART_Send(UARTx, &send, 1, BLOCKING); bytes = UART_Send(UARTx, &send, 1, BLOCKING);
} }
/* Otherwiise, write the byte to the transmit buffer */ // Otherwiise, write the byte to the transmit buffer
else if ((TxQueueWritePos+1) % TX_BUFFER_SIZE != TxQueueReadPos) { else if ((TxQueueWritePos+1) % TX_BUFFER_SIZE != TxQueueReadPos) {
TxBuffer[TxQueueWritePos] = send; TxBuffer[TxQueueWritePos] = send;
TxQueueWritePos = (TxQueueWritePos+1) % TX_BUFFER_SIZE; TxQueueWritePos = (TxQueueWritePos+1) % TX_BUFFER_SIZE;
bytes++; bytes++;
} }
/* Re-enable the TX Interrupt */ // Re-enable the TX Interrupt
UART_IntConfig(UARTx, UART_INTCFG_THRE, ENABLE); UART_IntConfig(UARTx, UART_INTCFG_THRE, ENABLE);
return bytes; return bytes;
#else #else
return UART_Send(UARTx, &send, 1, BLOCKING); return UART_Send(UARTx, &send, 1, BLOCKING);
#endif #endif
} }
#if TX_BUFFER_SIZE > 0 #if TX_BUFFER_SIZE > 0
void HardwareSerial::flushTX() { void HardwareSerial::flushTX() {
/* Wait for the tx buffer and FIFO to drain */ // Wait for the tx buffer and FIFO to drain
while (TxQueueWritePos != TxQueueReadPos && UART_CheckBusy(UARTx) == SET); while (TxQueueWritePos != TxQueueReadPos && UART_CheckBusy(UARTx) == SET);
} }
#endif #endif
@ -234,65 +223,58 @@ void HardwareSerial::IRQHandler() {
uint8_t LSRValue, byte; uint8_t LSRValue, byte;
IIRValue = UART_GetIntId(UARTx); IIRValue = UART_GetIntId(UARTx);
IIRValue &= UART_IIR_INTID_MASK; /* check bit 1~3, interrupt identification */ IIRValue &= UART_IIR_INTID_MASK; // check bit 1~3, interrupt identification
if ( IIRValue == UART_IIR_INTID_RLS ) /* Receive Line Status */ // Receive Line Status
{ if (IIRValue == UART_IIR_INTID_RLS) {
LSRValue = UART_GetLineStatus(UARTx); LSRValue = UART_GetLineStatus(UARTx);
/* Receive Line Status */ // Receive Line Status
if ( LSRValue & (UART_LSR_OE|UART_LSR_PE|UART_LSR_FE|UART_LSR_RXFE|UART_LSR_BI) ) if (LSRValue & (UART_LSR_OE | UART_LSR_PE | UART_LSR_FE | UART_LSR_RXFE | UART_LSR_BI)) {
{ // There are errors or break interrupt
/* There are errors or break interrupt */ // Read LSR will clear the interrupt
/* Read LSR will clear the interrupt */
Status = LSRValue; Status = LSRValue;
byte = UART_ReceiveByte(UARTx); /* Dummy read on RX to clear byte = UART_ReceiveByte(UARTx); // Dummy read on RX to clear interrupt, then bail out
interrupt, then bail out */
return; return;
} }
} }
if ( IIRValue == UART_IIR_INTID_RDA ) /* Receive Data Available */ // Receive Data Available
{ if (IIRValue == UART_IIR_INTID_RDA) {
/* Clear the FIFO */ // Clear the FIFO
while ( UART_Receive(UARTx, &byte, 1, NONE_BLOCKING) ) { while (UART_Receive(UARTx, &byte, 1, NONE_BLOCKING)) {
if ((RxQueueWritePos+1) % RX_BUFFER_SIZE != RxQueueReadPos) if ((RxQueueWritePos + 1) % RX_BUFFER_SIZE != RxQueueReadPos) {
{
RxBuffer[RxQueueWritePos] = byte; RxBuffer[RxQueueWritePos] = byte;
RxQueueWritePos = (RxQueueWritePos+1) % RX_BUFFER_SIZE; RxQueueWritePos = (RxQueueWritePos + 1) % RX_BUFFER_SIZE;
} } else
else
break; break;
} }
} // Character timeout indicator
else if ( IIRValue == UART_IIR_INTID_CTI ) /* Character timeout indicator */ } else if (IIRValue == UART_IIR_INTID_CTI) {
{ // Character Time-out indicator
/* Character Time-out indicator */ Status |= 0x100; // Bit 9 as the CTI error
Status |= 0x100; /* Bit 9 as the CTI error */
} }
#if TX_BUFFER_SIZE > 0 #if TX_BUFFER_SIZE > 0
if (IIRValue == UART_IIR_INTID_THRE) { if (IIRValue == UART_IIR_INTID_THRE) {
/* Disable THRE interrupt */ // Disable THRE interrupt
UART_IntConfig(UARTx, UART_INTCFG_THRE, DISABLE); UART_IntConfig(UARTx, UART_INTCFG_THRE, DISABLE);
/* Wait for FIFO buffer empty */ // Wait for FIFO buffer empty
while (UART_CheckBusy(UARTx) == SET); while (UART_CheckBusy(UARTx) == SET);
/* Transfer up to UART_TX_FIFO_SIZE bytes of data */ // Transfer up to UART_TX_FIFO_SIZE bytes of data
for (int i = 0; i < UART_TX_FIFO_SIZE && TxQueueWritePos != TxQueueReadPos; i++) { for (int i = 0; i < UART_TX_FIFO_SIZE && TxQueueWritePos != TxQueueReadPos; i++) {
/* Move a piece of data into the transmit FIFO */ // Move a piece of data into the transmit FIFO
if (UART_Send(UARTx, &TxBuffer[TxQueueReadPos], 1, NONE_BLOCKING)) if (UART_Send(UARTx, &TxBuffer[TxQueueReadPos], 1, NONE_BLOCKING)) {
TxQueueReadPos = (TxQueueReadPos+1) % TX_BUFFER_SIZE; TxQueueReadPos = (TxQueueReadPos+1) % TX_BUFFER_SIZE;
else } else break;
break;
} }
/* If there is no more data to send, disable the transmit interrupt - else enable it or keep it enabled */ // If there is no more data to send, disable the transmit interrupt - else enable it or keep it enabled
if (TxQueueWritePos == TxQueueReadPos) if (TxQueueWritePos == TxQueueReadPos) {
UART_IntConfig(UARTx, UART_INTCFG_THRE, DISABLE); UART_IntConfig(UARTx, UART_INTCFG_THRE, DISABLE);
else } else UART_IntConfig(UARTx, UART_INTCFG_THRE, ENABLE);
UART_IntConfig(UARTx, UART_INTCFG_THRE, ENABLE);
} }
#endif #endif
} }
@ -301,60 +283,28 @@ void HardwareSerial::IRQHandler() {
extern "C" { extern "C" {
#endif #endif
/***************************************************************************** void UART0_IRQHandler(void) {
** Function name: UART0_IRQHandler #if SERIAL_PORT == 0 || SERIAL_PORT_2 == 0
**
** Descriptions: UART0 interrupt handler
**
** parameters: None
** Returned value: None
**
*****************************************************************************/
void UART0_IRQHandler (void)
{
Serial.IRQHandler(); Serial.IRQHandler();
#endif
} }
/***************************************************************************** void UART1_IRQHandler(void) {
** Function name: UART1_IRQHandler #if SERIAL_PORT == 1 || SERIAL_PORT_2 == 1
**
** Descriptions: UART1 interrupt handler
**
** parameters: None
** Returned value: None
**
*****************************************************************************/
void UART1_IRQHandler (void)
{
Serial1.IRQHandler(); Serial1.IRQHandler();
#endif
} }
/***************************************************************************** void UART2_IRQHandler(void) {
** Function name: UART2_IRQHandler #if SERIAL_PORT == 2 || SERIAL_PORT_2 == 2
**
** Descriptions: UART2 interrupt handler
**
** parameters: None
** Returned value: None
**
*****************************************************************************/
void UART2_IRQHandler (void)
{
Serial2.IRQHandler(); Serial2.IRQHandler();
#endif
} }
/***************************************************************************** void UART3_IRQHandler(void) {
** Function name: UART3_IRQHandler #if SERIAL_PORT == 3 || SERIAL_PORT_2 == 3
**
** Descriptions: UART3 interrupt handler
**
** parameters: None
** Returned value: None
**
*****************************************************************************/
void UART3_IRQHandler (void)
{
Serial3.IRQHandler(); Serial3.IRQHandler();
#endif
} }
#ifdef __cplusplus #ifdef __cplusplus

5
Marlin/src/HAL/HAL_LPC1768/HardwareSerial.h
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@ -177,9 +177,4 @@ public:
}; };
extern HardwareSerial Serial;
extern HardwareSerial Serial1;
extern HardwareSerial Serial2;
extern HardwareSerial Serial3;
#endif // MARLIN_SRC_HAL_HAL_SERIAL_H_ #endif // MARLIN_SRC_HAL_HAL_SERIAL_H_

2
Marlin/src/inc/Conditionals_post.h
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@ -1260,7 +1260,7 @@
#undef SDSORT_USES_RAM #undef SDSORT_USES_RAM
#undef SDSORT_USES_STACK #undef SDSORT_USES_STACK
#undef SDSORT_CACHE_NAMES #undef SDSORT_CACHE_NAMES
#define SDSORT_LIMIT 256 #define SDSORT_LIMIT 64
#define SDSORT_USES_RAM true #define SDSORT_USES_RAM true
#define SDSORT_USES_STACK false #define SDSORT_USES_STACK false
#define SDSORT_CACHE_NAMES true #define SDSORT_CACHE_NAMES true