Rename, clean up boards/variants (#21655)

* Consolidate variant scripts
* Rename Marlin-local boards
* Simplify variants where possible
* Rename variants
* CHITU_F103 and MEEB_3DP: Maple platform `platformio-build-stm32f1.py` uses the 'board' name, not 'board_build.variant' so folder names match 'board' and not `board_build.variant`.
This commit is contained in:
Scott Lahteine
2021-04-27 04:49:21 -05:00
committed by GitHub
parent 69d85cce2d
commit ee016e605c
167 changed files with 340 additions and 840 deletions

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@ -1,65 +0,0 @@
{
"build": {
"core": "stm32",
"cpu": "cortex-m4",
"extra_flags": "-DSTM32F407xx",
"f_cpu": "168000000L",
"hwids": [
[
"0x1EAF",
"0x0003"
],
[
"0x0483",
"0x3748"
]
],
"mcu": "stm32f407zgt6",
"variant": "LERDGE",
"ldscript": "LERDGE.ld"
},
"debug": {
"jlink_device": "STM32F407ZG",
"openocd_target": "stm32f4x",
"svd_path": "STM32F40x.svd",
"tools": {
"stlink": {
"server": {
"arguments": [
"-f",
"scripts/interface/stlink.cfg",
"-c",
"transport select hla_swd",
"-f",
"scripts/target/stm32f4x.cfg",
"-c",
"reset_config none"
],
"executable": "bin/openocd",
"package": "tool-openocd"
}
}
}
},
"frameworks": [
"arduino",
"stm32cube"
],
"name": "STM32F407ZGT6(192k RAM. 1024k Flash)",
"upload": {
"disable_flushing": false,
"maximum_ram_size": 196608,
"maximum_size": 1048576,
"protocol": "stlink",
"protocols": [
"stlink",
"dfu",
"jlink"
],
"require_upload_port": true,
"use_1200bps_touch": false,
"wait_for_upload_port": false
},
"url": "https://www.st.com/en/microcontrollers-microprocessors/stm32f407ZG.html",
"vendor": "Generic"
}

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@ -1,34 +0,0 @@
{
"build": {
"core": "arduino",
"extra_flags": "-DARDUINO_AVR_MEGA2560",
"f_cpu": "16000000L",
"hwids": [
[
"0x27b2",
"0x0002"
]
],
"mcu": "atmega2560",
"variant": "fysetcf6"
},
"debug": {
"simavr_target": "atmega2560",
"avr-stub": {
"speed": 115200
}
},
"frameworks": [
"arduino"
],
"name": "FYSETC F6",
"upload": {
"maximum_ram_size": 8192,
"maximum_size": 258048,
"protocol": "wiring",
"require_upload_port": true,
"speed": 115200
},
"url": "https://www.fysetc.com/",
"vendor": "FYSETC"
}

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@ -5,7 +5,7 @@
"extra_flags": "-DSTM32H743xx",
"f_cpu": "400000000L",
"mcu": "stm32h743iit6",
"variant": "BTT_SKR_SE_BX"
"variant": "MARLIN_BTT_SKR_SE_BX"
},
"debug": {
"jlink_device": "STM32H743II",

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@ -15,7 +15,7 @@
]
],
"mcu": "stm32f407vgt6",
"variant": "BIGTREE_BTT002"
"variant": "MARLIN_BIGTREE_BTT002"
},
"debug": {
"jlink_device": "STM32F407VG",

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@ -15,7 +15,7 @@
]
],
"mcu": "stm32f407zgt6",
"variant": "BIGTREE_GTR_V1"
"variant": "MARLIN_BIGTREE_GTR_V1"
},
"debug": {
"jlink_device": "STM32F407ZG",

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@ -15,7 +15,7 @@
]
],
"mcu": "stm32f407zgt6",
"variant": "BIGTREE_SKR_PRO_1v1"
"variant": "MARLIN_BIGTREE_SKR_PRO_11"
},
"debug": {
"jlink_device": "STM32F407ZG",

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@ -15,8 +15,7 @@
]
],
"mcu": "stm32f103zet6",
"variant": "CHITU_F103",
"ldscript": "chitu_f103.ld"
"variant": "marlin_CHITU_F103"
},
"debug": {
"jlink_device": "STM32F103ZE",

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@ -16,7 +16,7 @@
],
"ldscript": "stm32f401rc.ld",
"mcu": "stm32f401rct6",
"variant": "FYSETC_CHEETAH_V20"
"variant": "MARLIN_FYSETC_CHEETAH_V20"
},
"debug": {
"jlink_device": "STM32F401RC",

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@ -18,7 +18,7 @@
"ldscript": "stm32f103xc.ld"
},
"mcu": "stm32f103rct6",
"variant": "MEEB_3DP"
"variant": "marlin_MEEB_3DP"
},
"debug": {
"jlink_device": "STM32F103RC",

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@ -14,9 +14,8 @@
"0x3748"
]
],
"ldscript": "stm32f401xe.ld",
"mcu": "stm32f401vet6",
"variant": "STEVAL_F401VE"
"variant": "MARLIN_STEVAL_F401VE"
},
"debug": {
"jlink_device": "STM32F401VE",

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@ -14,8 +14,7 @@
"0x3748"
]
],
"mcu": "stm32f407zgt6",
"variant": "FLY_F407ZG"
"mcu": "stm32f407zgt6"
},
"debug": {
"jlink_device": "STM32F407ZG",
@ -49,7 +48,7 @@
"disable_flushing": false,
"maximum_ram_size": 196608,
"maximum_size": 1048576,
"protocol": "dfu",
"protocol": "stlink",
"protocols": [
"stlink",
"dfu",

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@ -21,7 +21,7 @@
"ldscript": "linker_scripts/gcc/flash.ld",
"mcu": "at91sam3x8e",
"usb_product": "Archim",
"variant": "archim"
"variant": "MARLIN_ARCHIM"
},
"connectivity": [
"can"