bissen21/Marlin_Firmware
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Clean up envs / variants

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This commit is contained in:
Scott Lahteine
2020-06-11 20:17:22 -05:00
parent 85e48bbb0d
commit ea20c77df9
4 changed files with 163 additions and 118 deletions
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2
buildroot/share/PlatformIO/scripts/STEVAL__F401XX.py
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@ -7,5 +7,3 @@ for i, flag in enumerate(env["LINKFLAGS"]):
env["LINKFLAGS"][i] = "-Wl,-T" + custom_ld_script
elif flag == "-T":
env["LINKFLAGS"][i + 1] = custom_ld_script

0
buildroot/share/PlatformIO/scripts/STM32F103RC_MEEB_3DP_create_variant.py → buildroot/share/PlatformIO/scripts/STM32F1_create_variant.py
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11
buildroot/share/PlatformIO/variants/MEEB_3DP/variant.h
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@ -1,20 +1,17 @@
#ifndef _VARIANT_ARDUINO_STM32_
#define _VARIANT_ARDUINO_STM32_
#pragma once
#define digitalPinToPort(P) ( PIN_MAP[P].gpio_device )
#define digitalPinToBitMask(P) ( BIT(PIN_MAP[P].gpio_bit) )
#define portOutputRegister(port) ( &(port->regs->ODR) )
#define portInputRegister(port) ( &(port->regs->IDR) )
#define portSetRegister(pin) ( &(PIN_MAP[pin].gpio_device->regs->BSRR) )
#define portClearRegister(pin) ( &(PIN_MAP[pin].gpio_device->regs->BRR) )
#define portSetRegister(pin) ( &(PIN_MAP[pin].gpio_device->regs->BSRR) )
#define portClearRegister(pin) ( &(PIN_MAP[pin].gpio_device->regs->BRR) )
#define portConfigRegister(pin) ( &(PIN_MAP[pin].gpio_device->regs->CRL) )
#define portConfigRegister(pin) ( &(PIN_MAP[pin].gpio_device->regs->CRL) )
static const uint8_t SS = BOARD_SPI1_NSS_PIN;
static const uint8_t SS1 = BOARD_SPI2_NSS_PIN;
static const uint8_t MOSI = BOARD_SPI1_MOSI_PIN;
static const uint8_t MISO = BOARD_SPI1_MISO_PIN;
static const uint8_t SCK = BOARD_SPI1_SCK_PIN;
#endif /* _VARIANT_ARDUINO_STM32_ */