Fix up various spacing, comments, and typos

This commit is contained in:
Scott Lahteine
2018-03-07 20:30:19 -06:00
parent d45f19d385
commit ca577c1638
16 changed files with 747 additions and 864 deletions

View File

@ -20,42 +20,38 @@
*
*/
/*
u8g_dev_ssd1306_128x64.c
Universal 8bit Graphics Library
Copyright (c) 2011, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* Based on u8g_dev_ssd1306_128x64.c
*
* Universal 8bit Graphics Library
*
* Copyright (c) 2015, olikraus@gmail.com
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* These routines are meant for two wire I2C interfaces.
@ -85,43 +81,38 @@ uint8_t u8g_WriteEscSeqP_2_wire(u8g_t *u8g, u8g_dev_t *dev, const uint8_t *esc_s
// The sh1106 is compatible to the ssd1306, but is 132x64. 128x64 display area is centered within
// the 132x64.
static const uint8_t u8g_dev_sh1106_128x64_data_start_2_wire[] PROGMEM = {
0x010, // set upper 4 bit of the col adr to 0
0x002, // set lower 4 bit of the col adr to 2 (centered display with ssd1306)
U8G_ESC_END // end of sequence
0x010, // set upper 4 bit of the col adr to 0
0x002, // set lower 4 bit of the col adr to 2 (centered display with ssd1306)
U8G_ESC_END // end of sequence
};
static const uint8_t u8g_dev_sh1106_128x64_init_seq_2_wire[] PROGMEM = {
U8G_ESC_ADR(0), // initiate command mode
0x0ae, /* display off, sleep mode */
0x0a8, 0x03f, /* mux ratio */
0x0d3, 0x00, /* display offset */
0x040, /* start line */
0x0a1, /* segment remap a0/a1*/
0x0c8, /* c0: scan dir normal, c8: reverse */
0x0da, 0x012, /* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */
0x081, 0x0cf, /* [2] set contrast control */
0x020, 0x002, /* 2012-05-27: page addressing mode */
0x21, 2, 0x81, // set column range from 0 through 131
0x22, 0, 7, // set page range from 0 through 7
0x0d9, 0x0f1, /* [2] pre-charge period 0x022/f1*/
0x0db, 0x040, /* vcomh deselect level */
0x0a4, /* output ram to display */
0x0a6, /* none inverted normal display mode */
0x0d5, 0x080, /* clock divide ratio (0x00=1) and oscillator frequency (0x8) */
0x08d, 0x014, /* [2] charge pump setting (p62): 0x014 enable, 0x010 disable */
0x02e, /* 2012-05-27: Deactivate scroll */
0x0af, /* display on */
U8G_ESC_END /* end of sequence */
U8G_ESC_ADR(0), // initiate command mode
0x0AE, // display off, sleep mode
0x0A8, 0x03F, // mux ratio
0x0D3, 0x00, // display offset
0x040, // start line
0x0A1, // segment remap a0/a1
0x0C8, // c0: scan dir normal, c8: reverse
0x0DA, 0x012, // com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5)
0x081, 0x0CF, // [2] set contrast control
0x020, 0x002, // 2012-05-27: page addressing mode
0x21, 2, 0x81, // set column range from 0 through 131
0x22, 0, 7, // set page range from 0 through 7
0x0D9, 0x0F1, // [2] pre-charge period 0x022/f1
0x0DB, 0x040, // vcomh deselect level
0x0A4, // output ram to display
0x0A6, // none inverted normal display mode
0x0D5, 0x080, // clock divide ratio (0x00=1) and oscillator frequency (0x8)
0x08D, 0x014, // [2] charge pump setting (p62): 0x014 enable, 0x010 disable
0x02E, // 2012-05-27: Deactivate scroll
0x0AF, // display on
U8G_ESC_END // end of sequence
};
uint8_t u8g_dev_sh1106_128x64_2x_2_wire_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
uint8_t u8g_dev_sh1106_128x64_2x_2_wire_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg) {
switch(msg) {
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
u8g_WriteEscSeqP_2_wire(u8g, dev, u8g_dev_sh1106_128x64_init_seq_2_wire);
@ -152,7 +143,6 @@ uint8_t u8g_dev_sh1106_128x64_2x_2_wire_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t m
return u8g_dev_pb16v1_base_fn(u8g, dev, msg, arg);
}
uint8_t u8g_dev_sh1106_128x64_2x_i2c_2_wire_buf[WIDTH*2] U8G_NOCOMMON ;
u8g_pb_t u8g_dev_sh1106_128x64_2x_i2c_2_wire_pb = { {16, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_sh1106_128x64_2x_i2c_2_wire_buf};
u8g_dev_t u8g_dev_sh1106_128x64_2x_i2c_2_wire = { u8g_dev_sh1106_128x64_2x_2_wire_fn, &u8g_dev_sh1106_128x64_2x_i2c_2_wire_pb, U8G_COM_SSD_I2C_HAL };
@ -160,41 +150,37 @@ u8g_dev_t u8g_dev_sh1106_128x64_2x_i2c_2_wire = { u8g_dev_sh1106_128x64_2x_2_wir
/////////////////////////////////////////////////////////////////////////////////////////////
static const uint8_t u8g_dev_ssd1306_128x64_data_start_2_wire[] PROGMEM = {
0x010, // set upper 4 bit of the col adr to 0
0x000, // set lower 4 bit of the col adr to 0
U8G_ESC_END // end of sequence
0x010, // set upper 4 bit of the col adr to 0
0x000, // set lower 4 bit of the col adr to 0
U8G_ESC_END // end of sequence
};
static const uint8_t u8g_dev_ssd1306_128x64_init_seq_2_wire[] PROGMEM = {
U8G_ESC_ADR(0), // initiate command mode
0x0ae, /* display off, sleep mode */
0x0a8, 0x03f, /* mux ratio */
0x0d3, 0x00, /* display offset */
0x040, /* start line */
0x0a1, /* segment remap a0/a1*/
0x0c8, /* c0: scan dir normal, c8: reverse */
0x0da, 0x012, /* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */
0x081, 0x0cf, /* [2] set contrast control */
0x020, 0x002, /* 2012-05-27: page addressing mode */
0x21, 0, 0x7f, // set column range from 0 through 127
0x22, 0, 7, // set page range from 0 through 7
0x0d9, 0x0f1, /* [2] pre-charge period 0x022/f1*/
0x0db, 0x040, /* vcomh deselect level */
0x0a4, /* output ram to display */
0x0a6, /* none inverted normal display mode */
0x0d5, 0x080, /* clock divide ratio (0x00=1) and oscillator frequency (0x8) */
0x08d, 0x014, /* [2] charge pump setting (p62): 0x014 enable, 0x010 disable */
0x02e, /* 2012-05-27: Deactivate scroll */
0x0af, /* display on */
U8G_ESC_END /* end of sequence */
U8G_ESC_ADR(0), // initiate command mode
0x0AE, // display off, sleep mode
0x0A8, 0x03F, // mux ratio
0x0D3, 0x00, // display offset
0x040, // start line
0x0A1, // segment remap a0/a1
0x0C8, // c0: scan dir normal, c8: reverse
0x0DA, 0x012, // com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5)
0x081, 0x0CF, // [2] set contrast control
0x020, 0x002, // 2012-05-27: page addressing mode
0x21, 0, 0x7F, // set column range from 0 through 127
0x22, 0, 7, // set page range from 0 through 7
0x0D9, 0x0F1, // [2] pre-charge period 0x022/f1
0x0DB, 0x040, // vcomh deselect level
0x0A4, // output ram to display
0x0A6, // none inverted normal display mode
0x0D5, 0x080, // clock divide ratio (0x00=1) and oscillator frequency (0x8)
0x08D, 0x014, // [2] charge pump setting (p62): 0x014 enable, 0x010 disable
0x02E, // 2012-05-27: Deactivate scroll
0x0AF, // display on
U8G_ESC_END // end of sequence
};
uint8_t u8g_dev_ssd1306_128x64_2x_2_wire_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
uint8_t u8g_dev_ssd1306_128x64_2x_2_wire_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg) {
switch(msg) {
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
u8g_WriteEscSeqP_2_wire(u8g, dev, u8g_dev_ssd1306_128x64_init_seq_2_wire);
@ -238,54 +224,42 @@ u8g_dev_t u8g_dev_ssd1306_128x64_2x_i2c_2_wire = { u8g_dev_ssd1306_128x64_2x_2_w
#define I2C_CMD_MODE 0x080
uint8_t u8g_WriteEscSeqP_2_wire(u8g_t *u8g, u8g_dev_t *dev, const uint8_t *esc_seq)
{
uint8_t u8g_WriteEscSeqP_2_wire(u8g_t *u8g, u8g_dev_t *dev, const uint8_t *esc_seq) {
uint8_t is_escape = 0;
uint8_t value;
for(;;)
{
for(;;) {
value = u8g_pgm_read(esc_seq);
if ( is_escape == 0 )
{
if ( value != 255 )
{
if ( u8g_WriteByte(u8g, dev, value) == 0 )
if (is_escape == 0) {
if (value != 255) {
if (u8g_WriteByte(u8g, dev, value) == 0 )
return 0;
if ( u8g_WriteByte(u8g, dev, I2C_CMD_MODE) == 0 )
if (u8g_WriteByte(u8g, dev, I2C_CMD_MODE) == 0 )
return 0;
}
else
{
else {
is_escape = 1;
}
}
else
{
if ( value == 255 )
{
if ( u8g_WriteByte(u8g, dev, value) == 0 )
else {
if (value == 255) {
if (u8g_WriteByte(u8g, dev, value) == 0 )
return 0;
if ( u8g_WriteByte(u8g, dev, I2C_CMD_MODE) == 0 )
if (u8g_WriteByte(u8g, dev, I2C_CMD_MODE) == 0 )
return 0;
}
else if ( value == 254 )
{
else if (value == 254) {
break;
}
else if ( value >= 0x0f0 )
{
else if (value >= 0x0f0) {
/* not yet used, do nothing */
}
else if ( value >= 0xe0 )
{
else if (value >= 0xe0 ) {
u8g_SetAddress(u8g, dev, value & 0x0f);
}
else if ( value >= 0xd0 )
{
else if (value >= 0xd0) {
u8g_SetChipSelect(u8g, dev, value & 0x0f);
}
else if ( value >= 0xc0 )
{
else if (value >= 0xc0) {
u8g_SetResetLow(u8g, dev);
value &= 0x0f;
value <<= 4;
@ -294,13 +268,10 @@ uint8_t u8g_WriteEscSeqP_2_wire(u8g_t *u8g, u8g_dev_t *dev, const uint8_t *esc_s
u8g_SetResetHigh(u8g, dev);
u8g_Delay(value);
}
else if ( value >= 0xbe )
{
/* not yet implemented */
else if (value >= 0xbe) { /* not yet implemented */
/* u8g_SetVCC(u8g, dev, value & 0x01); */
}
else if ( value <= 127 )
{
else if (value <= 127) {
u8g_Delay(value);
}
is_escape = 0;

View File

@ -20,42 +20,38 @@
*
*/
/*
u8g_dev_st7565_64128n_HAL.c (Displaytech)
Universal 8bit Graphics Library
Copyright (c) 2011, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* u8g_dev_st7565_64128n_HAL.c (Displaytech)
*
* Universal 8bit Graphics Library
*
* Copyright (c) 2011, olikraus@gmail.com
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "../../inc/MarlinConfig.h"
@ -71,78 +67,76 @@
/* init sequence from https://github.com/adafruit/ST7565-LCD/blob/master/ST7565/ST7565.cpp */
static const uint8_t u8g_dev_st7565_64128n_HAL_init_seq[] PROGMEM = {
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
U8G_ESC_RST(15), /* do reset low pulse with (15*16)+2 milliseconds (=maximum delay)*/
U8G_ESC_CS(0), // disable chip
U8G_ESC_ADR(0), // instruction mode
U8G_ESC_CS(1), // enable chip
U8G_ESC_RST(15), // do reset low pulse with (15*16)+2 milliseconds (=maximum delay)*/
0x0A2, /* 0x0a2: LCD bias 1/9 (according to Displaytech 64128N datasheet) */
0x0A0, /* Normal ADC Select (according to Displaytech 64128N datasheet) */
0x0A2, // 0x0a2: LCD bias 1/9 (according to Displaytech 64128N datasheet)
0x0A0, // Normal ADC Select (according to Displaytech 64128N datasheet)
0x0c8, /* common output mode: set scan direction normal operation/SHL Select, 0x0c0 --> SHL = 0, normal, 0x0c8 --> SHL = 1 */
0x040, /* Display start line for Displaytech 64128N */
0x0c8, // common output mode: set scan direction normal operation/SHL Select, 0x0c0 --> SHL = 0, normal, 0x0c8 --> SHL = 1
0x040, // Display start line for Displaytech 64128N
0x028 | 0x04, /* power control: turn on voltage converter */
U8G_ESC_DLY(50), /* delay 50 ms */
0x028 | 0x04, // power control: turn on voltage converter
U8G_ESC_DLY(50), // delay 50 ms
0x028 | 0x06, /* power control: turn on voltage regulator */
U8G_ESC_DLY(50), /* delay 50 ms */
0x028 | 0x06, // power control: turn on voltage regulator
U8G_ESC_DLY(50), // delay 50 ms
0x028 | 0x07, /* power control: turn on voltage follower */
U8G_ESC_DLY(50), /* delay 50 ms */
0x028 | 0x07, // power control: turn on voltage follower
U8G_ESC_DLY(50), // delay 50 ms
0x010, /* Set V0 voltage resistor ratio. Setting for controlling brightness of Displaytech 64128N */
0x010, // Set V0 voltage resistor ratio. Setting for controlling brightness of Displaytech 64128N
0x0a6, /* display normal, bit val 0: LCD pixel off. */
0x0a6, // display normal, bit val 0: LCD pixel off.
0x081, /* set contrast */
0x01e, /* Contrast value. Setting for controlling brightness of Displaytech 64128N */
0x081, // set contrast
0x01e, // Contrast value. Setting for controlling brightness of Displaytech 64128N
0x0af, /* display on */
0x0af, // display on
U8G_ESC_DLY(100), /* delay 100 ms */
0x0a5, /* display all points, ST7565 */
U8G_ESC_DLY(100), /* delay 100 ms */
U8G_ESC_DLY(100), /* delay 100 ms */
0x0a4, /* normal display */
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_END /* end of sequence */
U8G_ESC_DLY(100), // delay 100 ms
0x0a5, // display all points, ST7565
U8G_ESC_DLY(100), // delay 100 ms
U8G_ESC_DLY(100), // delay 100 ms
0x0a4, // normal display
U8G_ESC_CS(0), // disable chip
U8G_ESC_END // end of sequence
};
static const uint8_t u8g_dev_st7565_64128n_HAL_data_start[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x010, /* set upper 4 bit of the col adr to 0x10 */
0x000, /* set lower 4 bit of the col adr to 0x00. Changed for DisplayTech 64128N */
U8G_ESC_END /* end of sequence */
U8G_ESC_ADR(0), // instruction mode
U8G_ESC_CS(1), // enable chip
0x010, // set upper 4 bit of the col adr to 0x10
0x000, // set lower 4 bit of the col adr to 0x00. Changed for DisplayTech 64128N
U8G_ESC_END // end of sequence
};
static const uint8_t u8g_dev_st7565_64128n_HAL_sleep_on[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x0ac, /* static indicator off */
0x000, /* indicator register set (not sure if this is required) */
0x0ae, /* display off */
0x0a5, /* all points on */
U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
U8G_ESC_END /* end of sequence */
U8G_ESC_ADR(0), // instruction mode
U8G_ESC_CS(1), // enable chip
0x0ac, // static indicator off
0x000, // indicator register set (not sure if this is required)
0x0ae, // display off
0x0a5, // all points on
U8G_ESC_CS(0), // disable chip, bugfix 12 nov 2014
U8G_ESC_END // end of sequence
};
static const uint8_t u8g_dev_st7565_64128n_HAL_sleep_off[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x0a4, /* all points off */
0x0af, /* display on */
U8G_ESC_DLY(50), /* delay 50 ms */
U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
U8G_ESC_END /* end of sequence */
U8G_ESC_ADR(0), // instruction mode
U8G_ESC_CS(1), // enable chip
0x0a4, // all points off
0x0af, // display on
U8G_ESC_DLY(50), // delay 50 ms
U8G_ESC_CS(0), // disable chip, bugfix 12 nov 2014
U8G_ESC_END // end of sequence
};
uint8_t u8g_dev_st7565_64128n_HAL_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
uint8_t u8g_dev_st7565_64128n_HAL_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg) {
switch(msg) {
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_HAL_init_seq);
@ -176,10 +170,8 @@ uint8_t u8g_dev_st7565_64128n_HAL_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, vo
return u8g_dev_pb8v1_base_fn(u8g, dev, msg, arg);
}
uint8_t u8g_dev_st7565_64128n_HAL_2x_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
uint8_t u8g_dev_st7565_64128n_HAL_2x_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg) {
switch(msg) {
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_HAL_init_seq);

View File

@ -20,41 +20,38 @@
*
*/
/*
u8g_dev_st7920_128x64_HAL.c
Universal 8bit Graphics Library
Copyright (c) 2011, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* u8g_dev_st7920_128x64_HAL.c
*
* Universal 8bit Graphics Library
*
* Copyright (c) 2011, olikraus@gmail.com
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "../../inc/MarlinConfig.h"
@ -68,25 +65,24 @@
#define HEIGHT 64
#define PAGE_HEIGHT 8
/* init sequence from https://github.com/adafruit/ST7565-LCD/blob/master/ST7565/ST7565.cpp */
static const uint8_t u8g_dev_st7920_128x64_HAL_init_seq[] PROGMEM = {
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_RST(15), /* do reset low pulse with (15*16)+2 milliseconds (=maximum delay)*/
U8G_ESC_DLY(100), /* 8 Dez 2012: additional delay 100 ms because of reset*/
U8G_ESC_CS(1), /* enable chip */
U8G_ESC_DLY(50), /* delay 50 ms */
U8G_ESC_CS(0), // disable chip
U8G_ESC_ADR(0), // instruction mode
U8G_ESC_RST(15), // do reset low pulse with (15*16)+2 milliseconds (=maximum delay)
U8G_ESC_DLY(100), // 8 Dez 2012: additional delay 100 ms because of reset
U8G_ESC_CS(1), // enable chip
U8G_ESC_DLY(50), // delay 50 ms
0x038, /* 8 Bit interface (DL=1), basic instruction set (RE=0) */
0x00c, /* display on, cursor & blink off; 0x08: all off */
0x006, /* Entry mode: Cursor move to right ,DDRAM address counter (AC) plus 1, no shift */
0x002, /* disable scroll, enable CGRAM adress */
0x001, /* clear RAM, needs 1.6 ms */
U8G_ESC_DLY(100), /* delay 100 ms */
0x038, // 8 Bit interface (DL=1), basic instruction set (RE=0)
0x00c, // display on, cursor & blink off; 0x08: all off
0x006, // Entry mode: Cursor move to right ,DDRAM address counter (AC) plus 1, no shift
0x002, // disable scroll, enable CGRAM adress
0x001, // clear RAM, needs 1.6 ms
U8G_ESC_DLY(100), // delay 100 ms
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_END /* end of sequence */
U8G_ESC_CS(0), // disable chip
U8G_ESC_END // end of sequence
};
void clear_graphics_DRAM(u8g_t *u8g, u8g_dev_t *dev){
@ -107,13 +103,10 @@ void clear_graphics_DRAM(u8g_t *u8g, u8g_dev_t *dev){
u8g_WriteByte(u8g, dev, 0x0C); //display on, cursor+blink off
u8g_SetChipSelect(u8g, dev, 0);
}
uint8_t u8g_dev_st7920_128x64_HAL_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
uint8_t u8g_dev_st7920_128x64_HAL_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg) {
switch(msg) {
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7920_128x64_HAL_init_seq);
@ -122,46 +115,41 @@ uint8_t u8g_dev_st7920_128x64_HAL_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, vo
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_NEXT: {
uint8_t y, i;
uint8_t *ptr;
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
uint8_t y, i;
uint8_t *ptr;
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
u8g_SetAddress(u8g, dev, 0); /* cmd mode */
u8g_SetChipSelect(u8g, dev, 1);
y = pb->p.page_y0;
ptr = (uint8_t *)pb->buf;
for (i = 0; i < 8; i ++) {
u8g_SetAddress(u8g, dev, 0); /* cmd mode */
u8g_SetChipSelect(u8g, dev, 1);
y = pb->p.page_y0;
ptr = (uint8_t *)pb->buf;
for( i = 0; i < 8; i ++ )
{
u8g_SetAddress(u8g, dev, 0); /* cmd mode */
u8g_WriteByte(u8g, dev, 0x03e ); /* enable extended mode */
u8g_WriteByte(u8g, dev, 0x03e ); /* enable extended mode */
if ( y < 32 )
{
u8g_WriteByte(u8g, dev, 0x080 | y ); /* y pos */
u8g_WriteByte(u8g, dev, 0x080 ); /* set x pos to 0*/
}
else
{
u8g_WriteByte(u8g, dev, 0x080 | (y-32) ); /* y pos */
u8g_WriteByte(u8g, dev, 0x080 | 8); /* set x pos to 64*/
}
u8g_SetAddress(u8g, dev, 1); /* data mode */
u8g_WriteSequence(u8g, dev, WIDTH/8, ptr);
ptr += WIDTH/8;
y++;
if (y < 32) {
u8g_WriteByte(u8g, dev, 0x080 | y ); /* y pos */
u8g_WriteByte(u8g, dev, 0x080 ); /* set x pos to 0*/
}
u8g_SetChipSelect(u8g, dev, 0);
else {
u8g_WriteByte(u8g, dev, 0x080 | (y-32) ); /* y pos */
u8g_WriteByte(u8g, dev, 0x080 | 8); /* set x pos to 64*/
}
u8g_SetAddress(u8g, dev, 1); /* data mode */
u8g_WriteSequence(u8g, dev, WIDTH/8, ptr);
ptr += WIDTH/8;
y++;
}
break;
u8g_SetChipSelect(u8g, dev, 0);
}
break;
}
return u8g_dev_pb8h1_base_fn(u8g, dev, msg, arg);
}
uint8_t u8g_dev_st7920_128x64_HAL_4x_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
uint8_t u8g_dev_st7920_128x64_HAL_4x_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg) {
switch(msg) {
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7920_128x64_HAL_init_seq);
@ -172,38 +160,35 @@ uint8_t u8g_dev_st7920_128x64_HAL_4x_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg,
break;
case U8G_DEV_MSG_PAGE_NEXT: {
uint8_t y, i;
uint8_t *ptr;
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
uint8_t y, i;
uint8_t *ptr;
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
u8g_SetAddress(u8g, dev, 0); /* cmd mode */
u8g_SetChipSelect(u8g, dev, 1);
y = pb->p.page_y0;
ptr = (uint8_t *)pb->buf;
for (i = 0; i < 32; i ++) {
u8g_SetAddress(u8g, dev, 0); /* cmd mode */
u8g_SetChipSelect(u8g, dev, 1);
y = pb->p.page_y0;
ptr = (uint8_t *)pb->buf;
for( i = 0; i < 32; i ++ )
{
u8g_SetAddress(u8g, dev, 0); /* cmd mode */
u8g_WriteByte(u8g, dev, 0x03e ); /* enable extended mode */
u8g_WriteByte(u8g, dev, 0x03e ); /* enable extended mode */
if ( y < 32 )
{
u8g_WriteByte(u8g, dev, 0x080 | y ); /* y pos */
u8g_WriteByte(u8g, dev, 0x080 ); /* set x pos to 0*/
}
else
{
u8g_WriteByte(u8g, dev, 0x080 | (y-32) ); /* y pos */
u8g_WriteByte(u8g, dev, 0x080 | 8); /* set x pos to 64*/
}
u8g_SetAddress(u8g, dev, 1); /* data mode */
u8g_WriteSequence(u8g, dev, WIDTH/8, ptr);
ptr += WIDTH/8;
y++;
if (y < 32) {
u8g_WriteByte(u8g, dev, 0x080 | y ); /* y pos */
u8g_WriteByte(u8g, dev, 0x080 ); /* set x pos to 0*/
}
u8g_SetChipSelect(u8g, dev, 0);
else {
u8g_WriteByte(u8g, dev, 0x080 | (y-32) ); /* y pos */
u8g_WriteByte(u8g, dev, 0x080 | 8); /* set x pos to 64*/
}
u8g_SetAddress(u8g, dev, 1); /* data mode */
u8g_WriteSequence(u8g, dev, WIDTH/8, ptr);
ptr += WIDTH/8;
y++;
}
break;
u8g_SetChipSelect(u8g, dev, 0);
}
break;
}
return u8g_dev_pb32h1_base_fn(u8g, dev, msg, arg);
}
@ -215,11 +200,9 @@ uint8_t u8g_dev_st7920_128x64_HAL_4x_buf[QWIDTH] U8G_NOCOMMON ;
u8g_pb_t u8g_dev_st7920_128x64_HAL_4x_pb = { {32, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_st7920_128x64_HAL_4x_buf};
u8g_dev_t u8g_dev_st7920_128x64_HAL_4x_sw_spi = { u8g_dev_st7920_128x64_HAL_4x_fn, &u8g_dev_st7920_128x64_HAL_4x_pb, U8G_COM_ST7920_HAL_SW_SPI };
U8G_PB_DEV(u8g_dev_st7920_128x64_HAL_hw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7920_128x64_HAL_fn, U8G_COM_ST7920_HAL_HW_SPI);
u8g_dev_t u8g_dev_st7920_128x64_HAL_4x_hw_spi = { u8g_dev_st7920_128x64_HAL_4x_fn, &u8g_dev_st7920_128x64_HAL_4x_pb, U8G_COM_ST7920_HAL_HW_SPI };
#if defined(U8G_HAL_LINKS) || defined(__SAM3X8E__)
// Also use this device for HAL version of rrd class. This results in the same device being used
// for the ST7920 for HAL systems no matter what is selected in ultralcd_impl_DOGM.h.