bissen21/Marlin_Firmware
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🐛 Spellcheck comments (#22496)

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codespell -q 3 --builtin=clear,rare,informal,code -S ./Marlin/src/lcd/language -L alo,amin,endcode,stdio,uint
This commit is contained in:
luzpaz
2021-08-03 20:02:34 -04:00
committed by Scott Lahteine
parent 8385be25cd
commit c612b56bc1
135 changed files with 186 additions and 186 deletions
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2
Marlin/src/HAL/SAMD51/HAL.cpp
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@@ -98,7 +98,7 @@
// Struct must be 32 bits aligned because of DMA accesses but fields needs to be 8 bits packed
typedef struct __attribute__((aligned(4), packed)) {
ADC_INPUTCTRL_Type INPUTCTRL;
} HAL_DMA_DAC_Registers; // DMA transfered registers
} HAL_DMA_DAC_Registers; // DMA transferred registers
#endif

2
Marlin/src/HAL/SAMD51/fastio.h
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@@ -131,7 +131,7 @@
*/
#define PWM_PIN(P) (WITHIN(P, 2, 13) || WITHIN(P, 22, 23) || WITHIN(P, 44, 45) || P == 48)
// Return fullfilled ADCx->INPUTCTRL.reg
// Return fulfilled ADCx->INPUTCTRL.reg
#define PIN_TO_INPUTCTRL(P) ( (PIN_TO_AIN(P) == 0) ? ADC_INPUTCTRL_MUXPOS_AIN0 \
: (PIN_TO_AIN(P) == 1) ? ADC_INPUTCTRL_MUXPOS_AIN1 \
: (PIN_TO_AIN(P) == 2) ? ADC_INPUTCTRL_MUXPOS_AIN2 \

2
Marlin/src/HAL/SAMD51/timers.cpp
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@@ -107,7 +107,7 @@ void HAL_timer_start(const uint8_t timer_num, const uint32_t frequency) {
tc->COUNT32.INTENCLR.reg = TC_INTENCLR_OVF; // disable overflow interrupt
// TCn clock setup
const uint8_t clockID = GCLK_CLKCTRL_IDs[TCC_INST_NUM + timer_num]; // TC clock are preceeded by TCC ones
const uint8_t clockID = GCLK_CLKCTRL_IDs[TCC_INST_NUM + timer_num]; // TC clock are preceded by TCC ones
GCLK->PCHCTRL[clockID].bit.CHEN = false;
SYNC(GCLK->PCHCTRL[clockID].bit.CHEN);
GCLK->PCHCTRL[clockID].reg = GCLK_PCHCTRL_GEN_GCLK0 | GCLK_PCHCTRL_CHEN; // 120MHz startup code programmed