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HAL whitespace and style cleanup

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This commit is contained in:
Scott Lahteine
2017-09-27 04:57:33 -05:00
parent c272f2c84e
commit c2b1d51f16
24 changed files with 449 additions and 829 deletions
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92
Marlin/src/HAL/HAL_LPC1768/LPC1768_PWM.h
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@ -27,19 +27,19 @@
*/
/**
* This is a hybrid system.
* This is a hybrid system.
*
* The PWM1 module is used to directly control the Servo 0, 1 & 3 pins. This keeps
* the pulse width jitter to under a microsecond.
*
* For all other pins the PWM1 module is used to generate interrupts. The ISR
* For all other pins the PWM1 module is used to generate interrupts. The ISR
* routine does the actual setting/clearing of pins. The upside is that any pin can
* have a PWM channel assigned to it. The downside is that there is more pulse width
* jitter. The jitter depends on what else is happening in the system and what ISRs
* prempt the PWM ISR. Writing to the SD card can add 20 microseconds to the pulse
* width.
*/
/**
* The data structures are setup to minimize the computation done by the ISR which
* minimizes ISR execution time. Execution times are 2.2 - 3.7 microseconds.
@ -72,7 +72,7 @@ typedef struct { // holds all data needed to control/init one of the
uint16_t PWM_mask; // MASK TO CHECK/WRITE THE IR REGISTER
volatile uint32_t* set_register;
volatile uint32_t* clr_register;
uint32_t write_mask; // USED BY SET/CLEAR COMMANDS
uint32_t write_mask; // USED BY SET/CLEAR COMMANDS
uint32_t microseconds; // value written to MR register
uint32_t min; // lower value limit checked by WRITE routine before writing to the MR register
uint32_t max; // upper value limit checked by WRITE routine before writing to the MR register
@ -180,7 +180,7 @@ void LPC1768_PWM_init(void) {
bool PWM_table_swap = false; // flag to tell the ISR that the tables have been swapped
bool PWM_MR0_wait = false; // flag to ensure don't delay MR0 interrupt
bool PWM_MR0_wait = false; // flag to ensure don't delay MR0 interrupt
bool LPC1768_PWM_attach_pin(uint8_t pin, uint32_t min = 1, uint32_t max = (LPC_PWM1_MR0 - MR0_MARGIN), uint8_t servo_index = 0xff) {
@ -209,7 +209,7 @@ bool LPC1768_PWM_attach_pin(uint8_t pin, uint32_t min = 1, uint32_t max = (LPC_P
//swap tables
PWM_MR0_wait = true;
while (PWM_MR0_wait) delay(5); //wait until MR0 interrupt has happend so don't delay it.
NVIC_DisableIRQ(PWM1_IRQn);
PWM_map *pointer_swap = active_table;
active_table = work_table;
@ -235,8 +235,8 @@ typedef struct { // status of PWM1 channel
uint32_t PINSEL3_bits; // PINSEL3 register bits to set pin mode to PWM1 control
} MR_map;
MR_map map_MR[NUM_PWMS];
MR_map map_MR[NUM_PWMS];
void LPC1768_PWM_update_map_MR(void) {
map_MR[0] = {0, (uint8_t) (LPC_PWM1->PCR & _BV(8 + pin_4_PWM_channel) ? 1 : 0), 4, &LPC_PWM1->MR1, 0, 0};
map_MR[1] = {0, (uint8_t) (LPC_PWM1->PCR & _BV(8 + pin_11_PWM_channel) ? 1 : 0), 11, &LPC_PWM1->MR2, 0, 0};
@ -244,7 +244,7 @@ void LPC1768_PWM_update_map_MR(void) {
map_MR[3] = {0, 0, 0, &LPC_PWM1->MR4, 0, 0};
map_MR[4] = {0, 0, 0, &LPC_PWM1->MR5, 0, 0};
map_MR[5] = {0, 0, 0, &LPC_PWM1->MR6, 0, 0};
}
}
uint32_t LPC1768_PWM_interrupt_mask = 1;
@ -265,46 +265,46 @@ void LPC1768_PWM_update(void) {
}
LPC1768_PWM_interrupt_mask = 0; // set match registers to new values, build IRQ mask
for (uint8_t i = 0; i < NUM_PWMS; i++) {
for (uint8_t i = 0; i < NUM_PWMS; i++) {
if (work_table[i].active_flag == true) {
work_table[i].sequence = i + 1;
// first see if there is a PWM1 controlled pin for this entry
bool found = false;
for (uint8_t j = 0; (j < NUM_PWMS) && !found; j++) {
for (uint8_t j = 0; (j < NUM_PWMS) && !found; j++) {
if ( (map_MR[j].map_PWM_PIN == work_table[i].logical_pin) && map_MR[j].map_PWM_INT ) {
*map_MR[j].MR_register = work_table[i].microseconds; // found one of the PWM pins
work_table[i].PWM_mask = 0;
work_table[i].PCR_bit = map_MR[j].PCR_bit; // PCR register bit to enable PWM1 control of this pin
work_table[i].PINSEL3_bits = map_MR[j].PINSEL3_bits; // PINSEL3 register bits to set pin mode to PWM1 control} MR_map;
map_MR[j].map_used = 2;
work_table[i].assigned_MR = j +1; // only used to help in debugging
work_table[i].assigned_MR = j +1; // only used to help in debugging
found = true;
}
}
}
// didn't find a PWM1 pin so get an interrupt
for (uint8_t k = 0; (k < NUM_PWMS) && !found; k++) {
for (uint8_t k = 0; (k < NUM_PWMS) && !found; k++) {
if ( !(map_MR[k].map_PWM_INT || map_MR[k].map_used)) {
*map_MR[k].MR_register = work_table[i].microseconds; // found one for an interrupt pin
map_MR[k].map_used = 1;
LPC1768_PWM_interrupt_mask |= _BV(3 * (k + 1)); // set bit in the MCR to enable this MR to generate an interrupt
work_table[i].PWM_mask = _BV(IR_BIT(k + 1)); // bit in the IR that will go active when this MR generates an interrupt
work_table[i].assigned_MR = k +1; // only used to help in debugging
work_table[i].assigned_MR = k +1; // only used to help in debugging
found = true;
}
}
}
}
else
work_table[i].sequence = 0;
}
}
LPC1768_PWM_interrupt_mask |= (uint32_t) _BV(0); // add in MR0 interrupt
// swap tables
PWM_MR0_wait = true;
while (PWM_MR0_wait) delay(5); //wait until MR0 interrupt has happend so don't delay it.
NVIC_DisableIRQ(PWM1_IRQn);
LPC_PWM1->LER = 0x07E; // Set the latch Enable Bits to load the new Match Values for MR1 - MR6
PWM_map *pointer_swap = active_table;
@ -324,7 +324,7 @@ bool LPC1768_PWM_write(uint8_t pin, uint32_t value) {
if (slot == 0xFF) return false; // return error if pin not found
LPC1768_PWM_update_map_MR();
switch(pin) {
case 11: // Servo 0, PWM1 channel 2 (Pin 11 P1.20 PWM1.2)
map_MR[pin_11_PWM_channel - 1].PCR_bit = _BV(8 + pin_11_PWM_channel); // enable PWM1 module control of this pin
@ -337,22 +337,22 @@ bool LPC1768_PWM_write(uint8_t pin, uint32_t value) {
map_MR[pin_6_PWM_channel - 1].PINSEL3_bits = 0x2 << 10; // ISR must do this AFTER setting PCR
break;
case 4: // Servo 3, PWM1 channel 1 (Pin 4 P1.18 PWM1.1)
map_MR[pin_4_PWM_channel - 1].PCR_bit = _BV(8 + pin_4_PWM_channel); // enable PWM1 module control of this pin
map_MR[pin_4_PWM_channel - 1].PCR_bit = _BV(8 + pin_4_PWM_channel); // enable PWM1 module control of this pin
map_MR[pin_4_PWM_channel - 1].map_PWM_INT = 1; // 0 - available for interrupts, 1 - in use by PWM
map_MR[pin_4_PWM_channel - 1].PINSEL3_bits = 0x2 << 4; // ISR must do this AFTER setting PCR
break;
default: // ISR pins
default: // ISR pins
pinMode(pin, OUTPUT); // set pin to output but don't write anything in case it's already in use
break;
}
}
work_table[slot].microseconds = MAX(MIN(value, work_table[slot].max), work_table[slot].min);
work_table[slot].active_flag = true;
LPC1768_PWM_update();
return 1;
}
}
bool LPC1768_PWM_detach_pin(uint8_t pin) {
@ -382,16 +382,16 @@ bool LPC1768_PWM_detach_pin(uint8_t pin) {
map_MR[pin_6_PWM_channel - 1].map_PWM_INT = 0; // 0 - available for interrupts, 1 - in use by PWM
break;
case 4: // Servo 3, PWM1 channel 1 (Pin 4 P1.18 PWM1.1)
LPC_PWM1->PCR &= ~(_BV(8 + pin_4_PWM_channel)); // disable PWM1 module control of this pin
LPC_PWM1->PCR &= ~(_BV(8 + pin_4_PWM_channel)); // disable PWM1 module control of this pin
map_MR[pin_4_PWM_channel - 1].PCR_bit = 0;
LPC_PINCON->PINSEL3 &= ~(0x3 << 4); // return pin to general purpose I/O
map_MR[pin_4_PWM_channel - 1].PINSEL3_bits = 0;
map_MR[pin_4_PWM_channel - 1].map_PWM_INT = 0; // 0 - available for interrupts, 1 - in use by PWM
break;
}
}
pinMode(pin, INPUT);
work_table[slot] = PWM_MAP_INIT_ROW;
LPC1768_PWM_update();
@ -411,8 +411,8 @@ bool LPC1768_PWM_detach_pin(uint8_t pin) {
* Changes to PINSEL3, PCR and MCR are only done during the MR0 interrupt otherwise
* the wrong pin may be toggled or even have the system hang.
*/
HAL_PWM_LPC1768_ISR {
if (PWM_table_swap) ISR_table = work_table; // use old table if a swap was just done
else ISR_table = active_table;
@ -422,13 +422,13 @@ HAL_PWM_LPC1768_ISR {
if (PWM_table_swap) LPC_PWM1->MCR = LPC1768_PWM_interrupt_mask; // enable new PWM individual channel interrupts
for (uint8_t i = 0; (i < NUM_PWMS) ; i++) {
if(ISR_table[i].active_flag && !((ISR_table[i].logical_pin == 11) ||
(ISR_table[i].logical_pin == 4) ||
(ISR_table[i].logical_pin == 6)))
if(ISR_table[i].active_flag && !((ISR_table[i].logical_pin == 11) ||
(ISR_table[i].logical_pin == 4) ||
(ISR_table[i].logical_pin == 6)))
*ISR_table[i].set_register = ISR_table[i].write_mask; // set pins for all enabled interrupt channels active
if (PWM_table_swap && ISR_table[i].PCR_bit) {
LPC_PWM1->PCR |= ISR_table[i].PCR_bit; // enable PWM1 module control of this pin
LPC_PINCON->PINSEL3 |= ISR_table[i].PINSEL3_bits; // set pin mode to PWM1 control - must be done after PCR
LPC_PINCON->PINSEL3 |= ISR_table[i].PINSEL3_bits; // set pin mode to PWM1 control - must be done after PCR
}
}
PWM_table_swap = false;
@ -442,7 +442,7 @@ HAL_PWM_LPC1768_ISR {
*ISR_table[i].clr_register = ISR_table[i].write_mask; // set channel to inactive
}
}
LPC_PWM1->IR = 0x70F; // guarantees all interrupt flags are cleared which, if there is an unexpected
// PWM interrupt, will keep the ISR from hanging which will crash the controller
@ -457,20 +457,20 @@ return;
/**
* Almost all changes to the hardware registers must be coordinated with the Match Register 0 (MR0)
* interrupt. The only exception is detaching pins. It doesn't matter when they go
* tristate.
* tristate.
*
* The LPC1768_PWM_init routine kicks off the MR0 interrupt. This interrupt is never disabled or
* delayed.
* The LPC1768_PWM_init routine kicks off the MR0 interrupt. This interrupt is never disabled or
* delayed.
*
* The PWM_table_swap flag is set when the firmware has swapped in an updated table. It is
* cleared by the ISR during the MR0 interrupt as it completes the swap and accompanying updates.
* It serves two purposes:
* 1) Tells the ISR that the tables have been swapped
* 2) Keeps the firmware from starting a new update until the previous one has been completed.
* 2) Keeps the firmware from starting a new update until the previous one has been completed.
*
* The PWM_MR0_wait flag is set when the firmware is ready to swap in an updated table and cleared by
* The PWM_MR0_wait flag is set when the firmware is ready to swap in an updated table and cleared by
* the ISR during the MR0 interrupt. It is used to avoid delaying the MR0 interrupt when swapping in
* an updated table. This avoids glitches in pulse width and/or repetition rate.
* an updated table. This avoids glitches in pulse width and/or repetition rate.
*
* The sequence of events during a write to a PWM channel is:
* 1) Waits until PWM_table_swap flag is false before starting
@ -489,7 +489,7 @@ return;
* writes to the LER register
* sets the PWM_table_swap flag active
* re-enables the ISR
* 7) On the next interrupt the ISR changes its pointer to the work table which is now the old,
* 7) On the next interrupt the ISR changes its pointer to the work table which is now the old,
* unmodified, active table.
* 8) On the next MR0 interrupt the ISR:
* switches over to the active table
@ -500,4 +500,4 @@ return;
* NOTE - PCR must be set before PINSEL
* sets the pins controlled by the ISR to their active states
*/