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Revert "[2.0.x] DUE compatibility with shared SPI LCDs, USB mass storage, add pin defs & update examples\MakerParts\Configuration.h"

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This commit is contained in:
Bob-the-Kuhn
2018-03-10 17:22:20 -06:00
committed by GitHub
parent fd1d590726
commit bf59a4a6df
11 changed files with 225 additions and 744 deletions
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10
Marlin/src/HAL/HAL_DUE/HAL_Due.h
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@ -41,7 +41,15 @@
// Defines
//
#define NUM_SERIAL 1
#define MYSERIAL0 customizedSerial
//#undef SERIAL_PORT
//#define SERIAL_PORT -1
#if SERIAL_PORT == -1
#define MYSERIAL0 SerialUSB
#else
#define MYSERIAL0 customizedSerial
#endif
// We need the previous define before the include, or compilation bombs...
#include "MarlinSerial_Due.h"

517
Marlin/src/HAL/HAL_DUE/HAL_spi_Due.cpp
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@ -53,7 +53,6 @@
// --------------------------------------------------------------------------
#if ENABLED(SOFTWARE_SPI)
// --------------------------------------------------------------------------
// software SPI
// --------------------------------------------------------------------------
@ -494,77 +493,44 @@
static pfnSpiTxBlock spiTxBlock = spiTxBlockX;
static pfnSpiRxBlock spiRxBlock = spiRxBlockX;
#if MB(ALLIGATOR) // control SDSS pin
void spiBegin() {
SET_OUTPUT(SS_PIN);
WRITE(SS_PIN, HIGH);
SET_OUTPUT(SCK_PIN);
SET_INPUT(MISO_PIN);
SET_OUTPUT(MOSI_PIN);
}
void spiBegin() {
SET_OUTPUT(SS_PIN);
WRITE(SS_PIN, HIGH);
SET_OUTPUT(SCK_PIN);
SET_INPUT(MISO_PIN);
SET_OUTPUT(MOSI_PIN);
}
uint8_t spiRec() {
WRITE(SS_PIN, LOW);
WRITE(MOSI_PIN, 1); /* Output 1s 1*/
uint8_t b = spiTransferRx(0xFF);
WRITE(SS_PIN, HIGH);
return b;
}
uint8_t spiRec() {
WRITE(SS_PIN, LOW);
WRITE(MOSI_PIN, 1); /* Output 1s 1*/
uint8_t b = spiTransferRx(0xFF);
WRITE(SS_PIN, HIGH);
return b;
}
void spiRead(uint8_t* buf, uint16_t nbyte) {
uint32_t todo = nbyte;
if (todo == 0) return;
void spiRead(uint8_t* buf, uint16_t nbyte) {
uint32_t todo = nbyte;
if (todo == 0) return;
WRITE(SS_PIN, LOW);
WRITE(MOSI_PIN, 1); /* Output 1s 1*/
spiRxBlock(buf,nbyte);
WRITE(SS_PIN, HIGH);
}
WRITE(SS_PIN, LOW);
WRITE(MOSI_PIN, 1); /* Output 1s 1*/
spiRxBlock(buf,nbyte);
WRITE(SS_PIN, HIGH);
}
void spiSend(uint8_t b) {
WRITE(SS_PIN, LOW);
(void) spiTransferTx(b);
WRITE(SS_PIN, HIGH);
}
void spiSend(uint8_t b) {
WRITE(SS_PIN, LOW);
(void) spiTransferTx(b);
WRITE(SS_PIN, HIGH);
}
void spiSendBlock(uint8_t token, const uint8_t* buf) {
WRITE(SS_PIN, LOW);
(void) spiTransferTx(token);
spiTxBlock(buf,512);
WRITE(SS_PIN, HIGH);
#else // let calling routine control SDSS
void spiBegin() {
SET_OUTPUT(SS_PIN);
SET_OUTPUT(SCK_PIN);
SET_INPUT(MISO_PIN);
SET_OUTPUT(MOSI_PIN);
}
void spiSendBlock(uint8_t token, const uint8_t* buf) {
uint8_t spiRec() {
WRITE(MOSI_PIN, 1); /* Output 1s 1*/
uint8_t b = spiTransferRx(0xFF);
return b;
}
void spiRead(uint8_t* buf, uint16_t nbyte) {
uint32_t todo = nbyte;
if (todo == 0) return;
WRITE(MOSI_PIN, 1); /* Output 1s 1*/
spiRxBlock(buf,nbyte);
}
void spiSend(uint8_t b) {
(void) spiTransferTx(b);
}
void spiSendBlock(uint8_t token, const uint8_t* buf) {
(void) spiTransferTx(token);
spiTxBlock(buf,512);
#endif
WRITE(SS_PIN, LOW);
(void) spiTransferTx(token);
spiTxBlock(buf,512);
WRITE(SS_PIN, HIGH);
}
/**
@ -600,9 +566,7 @@
break;
}
#if MB(ALLIGATOR)
WRITE(SS_PIN, HIGH);
#endif
WRITE(SS_PIN, HIGH);
WRITE(MOSI_PIN, HIGH);
WRITE(SCK_PIN, LOW);
}
@ -610,296 +574,211 @@
/** Begin SPI transaction, set clock, bit order, data mode */
void spiBeginTransaction(uint32_t spiClock, uint8_t bitOrder, uint8_t dataMode) {
// TODO: to be implemented
}
#pragma GCC reset_options
#else
// --------------------------------------------------------------------------
// hardware SPI
// --------------------------------------------------------------------------
// 8.4 MHz, 4 MHz, 2 MHz, 1 MHz, 0.5 MHz, 0.329 MHz, 0.329 MHz
int spiDueDividors[] = { 10, 21, 42, 84, 168, 255, 255 };
bool spiInitMaded = false;
#if MB(ALLIGATOR)
// slave selects controlled by SPI controller
// doesn't support changing SPI speeds for SD card
// --------------------------------------------------------------------------
// hardware SPI
// --------------------------------------------------------------------------
// 8.4 MHz, 4 MHz, 2 MHz, 1 MHz, 0.5 MHz, 0.329 MHz, 0.329 MHz
int spiDueDividors[] = { 10, 21, 42, 84, 168, 255, 255 };
bool spiInitMaded = false;
void spiBegin() {
if(spiInitMaded == false) {
// Configure SPI pins
PIO_Configure(
g_APinDescription[SCK_PIN].pPort,
g_APinDescription[SCK_PIN].ulPinType,
g_APinDescription[SCK_PIN].ulPin,
g_APinDescription[SCK_PIN].ulPinConfiguration);
PIO_Configure(
g_APinDescription[MOSI_PIN].pPort,
g_APinDescription[MOSI_PIN].ulPinType,
g_APinDescription[MOSI_PIN].ulPin,
g_APinDescription[MOSI_PIN].ulPinConfiguration);
PIO_Configure(
g_APinDescription[MISO_PIN].pPort,
g_APinDescription[MISO_PIN].ulPinType,
g_APinDescription[MISO_PIN].ulPin,
g_APinDescription[MISO_PIN].ulPinConfiguration);
void spiBegin() {
if(spiInitMaded == false) {
// Configure SPI pins
PIO_Configure(
g_APinDescription[SCK_PIN].pPort,
g_APinDescription[SCK_PIN].ulPinType,
g_APinDescription[SCK_PIN].ulPin,
g_APinDescription[SCK_PIN].ulPinConfiguration);
PIO_Configure(
g_APinDescription[MOSI_PIN].pPort,
g_APinDescription[MOSI_PIN].ulPinType,
g_APinDescription[MOSI_PIN].ulPin,
g_APinDescription[MOSI_PIN].ulPinConfiguration);
PIO_Configure(
g_APinDescription[MISO_PIN].pPort,
g_APinDescription[MISO_PIN].ulPinType,
g_APinDescription[MISO_PIN].ulPin,
g_APinDescription[MISO_PIN].ulPinConfiguration);
// set master mode, peripheral select, fault detection
SPI_Configure(SPI0, ID_SPI0, SPI_MR_MSTR | SPI_MR_MODFDIS | SPI_MR_PS);
SPI_Enable(SPI0);
// set master mode, peripheral select, fault detection
SPI_Configure(SPI0, ID_SPI0, SPI_MR_MSTR | SPI_MR_MODFDIS | SPI_MR_PS);
SPI_Enable(SPI0);
#if MB(ALLIGATOR)
SET_OUTPUT(DAC0_SYNC);
#if EXTRUDERS > 1
SET_OUTPUT(DAC1_SYNC);
WRITE(DAC1_SYNC, HIGH);
#endif
SET_OUTPUT(SPI_EEPROM1_CS);
SET_OUTPUT(SPI_EEPROM2_CS);
SET_OUTPUT(SPI_FLASH_CS);
WRITE(DAC0_SYNC, HIGH);
WRITE(SPI_EEPROM1_CS, HIGH );
WRITE(SPI_EEPROM2_CS, HIGH );
WRITE(SPI_FLASH_CS, HIGH );
WRITE(SS_PIN, HIGH );
#endif // MB(ALLIGATOR)
#if MB(ALLIGATOR)
SET_OUTPUT(DAC0_SYNC);
#if EXTRUDERS > 1
SET_OUTPUT(DAC1_SYNC);
WRITE(DAC1_SYNC, HIGH);
#endif
SET_OUTPUT(SPI_EEPROM1_CS);
SET_OUTPUT(SPI_EEPROM2_CS);
SET_OUTPUT(SPI_FLASH_CS);
WRITE(DAC0_SYNC, HIGH);
WRITE(SPI_EEPROM1_CS, HIGH );
WRITE(SPI_EEPROM2_CS, HIGH );
WRITE(SPI_FLASH_CS, HIGH );
WRITE(SS_PIN, HIGH );
#endif // MB(ALLIGATOR)
OUT_WRITE(SDSS,0);
PIO_Configure(
g_APinDescription[SPI_PIN].pPort,
g_APinDescription[SPI_PIN].ulPinType,
g_APinDescription[SPI_PIN].ulPin,
g_APinDescription[SPI_PIN].ulPinConfiguration);
spiInit(1);
spiInitMaded = true;
}
PIO_Configure(
g_APinDescription[SPI_PIN].pPort,
g_APinDescription[SPI_PIN].ulPinType,
g_APinDescription[SPI_PIN].ulPin,
g_APinDescription[SPI_PIN].ulPinConfiguration);
spiInit(1);
spiInitMaded = true;
}
}
void spiInit(uint8_t spiRate) {
if(spiInitMaded == false) {
if(spiRate > 6) spiRate = 1;
void spiInit(uint8_t spiRate) {
if(spiInitMaded == false) {
if(spiRate > 6) spiRate = 1;
#if MB(ALLIGATOR)
// Set SPI mode 1, clock, select not active after transfer, with delay between transfers
SPI_ConfigureNPCS(SPI0, SPI_CHAN_DAC,
SPI_CSR_CSAAT | SPI_CSR_SCBR(spiDueDividors[spiRate]) |
SPI_CSR_DLYBCT(1));
// Set SPI mode 0, clock, select not active after transfer, with delay between transfers
SPI_ConfigureNPCS(SPI0, SPI_CHAN_EEPROM1, SPI_CSR_NCPHA |
SPI_CSR_CSAAT | SPI_CSR_SCBR(spiDueDividors[spiRate]) |
SPI_CSR_DLYBCT(1));
#endif//MB(ALLIGATOR)
// Set SPI mode 0, clock, select not active after transfer, with delay between transfers
SPI_ConfigureNPCS(SPI0, SPI_CHAN, SPI_CSR_NCPHA |
#if MB(ALLIGATOR)
// Set SPI mode 1, clock, select not active after transfer, with delay between transfers
SPI_ConfigureNPCS(SPI0, SPI_CHAN_DAC,
SPI_CSR_CSAAT | SPI_CSR_SCBR(spiDueDividors[spiRate]) |
SPI_CSR_DLYBCT(1));
SPI_Enable(SPI0);
spiInitMaded = true;
}
}
// Set SPI mode 0, clock, select not active after transfer, with delay between transfers
SPI_ConfigureNPCS(SPI0, SPI_CHAN_EEPROM1, SPI_CSR_NCPHA |
SPI_CSR_CSAAT | SPI_CSR_SCBR(spiDueDividors[spiRate]) |
SPI_CSR_DLYBCT(1));
#endif//MB(ALLIGATOR)
// Write single byte to SPI
void spiSend(byte b) {
// write byte with address and end transmission flag
SPI0->SPI_TDR = (uint32_t)b | SPI_PCS(SPI_CHAN) | SPI_TDR_LASTXFER;
// wait for transmit register empty
// Set SPI mode 0, clock, select not active after transfer, with delay between transfers
SPI_ConfigureNPCS(SPI0, SPI_CHAN, SPI_CSR_NCPHA |
SPI_CSR_CSAAT | SPI_CSR_SCBR(spiDueDividors[spiRate]) |
SPI_CSR_DLYBCT(1));
SPI_Enable(SPI0);
spiInitMaded = true;
}
}
// Write single byte to SPI
void spiSend(byte b) {
// write byte with address and end transmission flag
SPI0->SPI_TDR = (uint32_t)b | SPI_PCS(SPI_CHAN) | SPI_TDR_LASTXFER;
// wait for transmit register empty
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
// wait for receive register
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
// clear status
SPI0->SPI_RDR;
//delayMicroseconds(1U);
}
void spiSend(const uint8_t* buf, size_t n) {
if (n == 0) return;
for (size_t i = 0; i < n - 1; i++) {
SPI0->SPI_TDR = (uint32_t)buf[i] | SPI_PCS(SPI_CHAN);
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
// wait for receive register
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
// clear status
SPI0->SPI_RDR;
//delayMicroseconds(1U);
}
spiSend(buf[n - 1]);
}
void spiSend(const uint8_t* buf, size_t n) {
if (n == 0) return;
for (size_t i = 0; i < n - 1; i++) {
SPI0->SPI_TDR = (uint32_t)buf[i] | SPI_PCS(SPI_CHAN);
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
SPI0->SPI_RDR;
//delayMicroseconds(1U);
}
spiSend(buf[n - 1]);
}
void spiSend(uint32_t chan, byte b) {
uint8_t dummy_read = 0;
// wait for transmit register empty
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
// write byte with address and end transmission flag
SPI0->SPI_TDR = (uint32_t)b | SPI_PCS(chan) | SPI_TDR_LASTXFER;
// wait for receive register
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
// clear status
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 1)
dummy_read = SPI0->SPI_RDR;
UNUSED(dummy_read);
}
void spiSend(uint32_t chan, byte b) {
uint8_t dummy_read = 0;
// wait for transmit register empty
void spiSend(uint32_t chan, const uint8_t* buf, size_t n) {
uint8_t dummy_read = 0;
if (n == 0) return;
for (int i = 0; i < (int)n - 1; i++) {
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
// write byte with address and end transmission flag
SPI0->SPI_TDR = (uint32_t)b | SPI_PCS(chan) | SPI_TDR_LASTXFER;
// wait for receive register
SPI0->SPI_TDR = (uint32_t)buf[i] | SPI_PCS(chan);
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
// clear status
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 1)
dummy_read = SPI0->SPI_RDR;
UNUSED(dummy_read);
}
spiSend(chan, buf[n - 1]);
}
void spiSend(uint32_t chan, const uint8_t* buf, size_t n) {
uint8_t dummy_read = 0;
if (n == 0) return;
for (int i = 0; i < (int)n - 1; i++) {
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
SPI0->SPI_TDR = (uint32_t)buf[i] | SPI_PCS(chan);
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 1)
dummy_read = SPI0->SPI_RDR;
UNUSED(dummy_read);
}
spiSend(chan, buf[n - 1]);
}
// Read single byte from SPI
uint8_t spiRec() {
// write dummy byte with address and end transmission flag
SPI0->SPI_TDR = 0x000000FF | SPI_PCS(SPI_CHAN) | SPI_TDR_LASTXFER;
// wait for transmit register empty
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
// Read single byte from SPI
uint8_t spiRec() {
// write dummy byte with address and end transmission flag
SPI0->SPI_TDR = 0x000000FF | SPI_PCS(SPI_CHAN) | SPI_TDR_LASTXFER;
// wait for transmit register empty
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
// wait for receive register
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
// get byte from receive register
//delayMicroseconds(1U);
return SPI0->SPI_RDR;
}
// wait for receive register
uint8_t spiRec(uint32_t chan) {
uint8_t spirec_tmp;
// wait for transmit register empty
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 1)
spirec_tmp = SPI0->SPI_RDR;
UNUSED(spirec_tmp);
// write dummy byte with address and end transmission flag
SPI0->SPI_TDR = 0x000000FF | SPI_PCS(chan) | SPI_TDR_LASTXFER;
// wait for receive register
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
// get byte from receive register
return SPI0->SPI_RDR;
}
// Read from SPI into buffer
void spiRead(uint8_t*buf, uint16_t nbyte) {
if (nbyte-- == 0) return;
for (int i = 0; i < nbyte; i++) {
//while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
SPI0->SPI_TDR = 0x000000FF | SPI_PCS(SPI_CHAN);
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
// get byte from receive register
buf[i] = SPI0->SPI_RDR;
//delayMicroseconds(1U);
return SPI0->SPI_RDR;
}
buf[nbyte] = spiRec();
}
uint8_t spiRec(uint32_t chan) {
uint8_t spirec_tmp;
// wait for transmit register empty
// Write from buffer to SPI
void spiSendBlock(uint8_t token, const uint8_t* buf) {
SPI0->SPI_TDR = (uint32_t)token | SPI_PCS(SPI_CHAN);
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
//while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
//SPI0->SPI_RDR;
for (int i = 0; i < 511; i++) {
SPI0->SPI_TDR = (uint32_t)buf[i] | SPI_PCS(SPI_CHAN);
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 1)
spirec_tmp = SPI0->SPI_RDR;
UNUSED(spirec_tmp);
// write dummy byte with address and end transmission flag
SPI0->SPI_TDR = 0x000000FF | SPI_PCS(chan) | SPI_TDR_LASTXFER;
// wait for receive register
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
// get byte from receive register
return SPI0->SPI_RDR;
SPI0->SPI_RDR;
//delayMicroseconds(1U);
}
spiSend(buf[511]);
}
// Read from SPI into buffer
void spiRead(uint8_t*buf, uint16_t nbyte) {
if (nbyte-- == 0) return;
/** Begin SPI transaction, set clock, bit order, data mode */
void spiBeginTransaction(uint32_t spiClock, uint8_t bitOrder, uint8_t dataMode) {
// TODO: to be implemented
}
for (int i = 0; i < nbyte; i++) {
//while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
SPI0->SPI_TDR = 0x000000FF | SPI_PCS(SPI_CHAN);
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
buf[i] = SPI0->SPI_RDR;
//delayMicroseconds(1U);
}
buf[nbyte] = spiRec();
}
// Write from buffer to SPI
void spiSendBlock(uint8_t token, const uint8_t* buf) {
SPI0->SPI_TDR = (uint32_t)token | SPI_PCS(SPI_CHAN);
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
//while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
//SPI0->SPI_RDR;
for (int i = 0; i < 511; i++) {
SPI0->SPI_TDR = (uint32_t)buf[i] | SPI_PCS(SPI_CHAN);
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
SPI0->SPI_RDR;
//delayMicroseconds(1U);
}
spiSend(buf[511]);
}
/** Begin SPI transaction, set clock, bit order, data mode */
void spiBeginTransaction(uint32_t spiClock, uint8_t bitOrder, uint8_t dataMode) {
// TODO: to be implemented
}
#else // U8G compatible hardware SPI
void spiInit(uint8_t spiRate = 6 ) { // default to slowest rate if not specified)
// 8.4 MHz, 4 MHz, 2 MHz, 1 MHz, 0.5 MHz, 0.329 MHz, 0.329 MHz
int spiDueDividors[] = { 10, 21, 42, 84, 168, 255, 255 };
if(spiRate > 6) spiRate = 1;
/* enable PIOA and SPI0 */
REG_PMC_PCER0 = (1UL << ID_PIOA) | (1UL << ID_SPI0);
/* disable PIO on A26 and A27 */
REG_PIOA_PDR = 0x0c000000;
OUT_WRITE(SDSS, 1);
/* reset SPI0 (from sam lib) */
SPI0->SPI_CR = SPI_CR_SPIDIS;
SPI0->SPI_CR = SPI_CR_SWRST;
SPI0->SPI_CR = SPI_CR_SWRST;
SPI0->SPI_CR = SPI_CR_SPIEN;
/* master mode, no fault detection, chip select 0 */
SPI0->SPI_MR = SPI_MR_MSTR | SPI_MR_PCSDEC | SPI_MR_MODFDIS;
/* SPI mode 0, 8 Bit data transfer, baud rate */
SPI0->SPI_CSR[0] = SPI_CSR_SCBR(spiDueDividors[spiRate]) | 1;
}
static uint8_t spiTransfer(uint8_t data) {
/* wait until tx register is empty */
while( (SPI0->SPI_SR & SPI_SR_TDRE) == 0 );
/* send data */
SPI0->SPI_TDR = (uint32_t)data; // | SPI_PCS(0xF);
// wait for transmit register empty
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
// wait for receive register
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
// get byte from receive register
return SPI0->SPI_RDR;
}
void spiBegin() {
spiInit();
}
uint8_t spiRec() {
uint8_t data = spiTransfer(0xff);
return data;
}
void spiRead(uint8_t*buf, uint16_t nbyte) {
if (nbyte == 0) return;
for (int i = 0; i < nbyte; i++) {
buf[i] = spiTransfer(0xff);
}
}
void spiSend(uint8_t data) {
spiTransfer(data);
}
void spiSend(const uint8_t* buf, size_t n) {
if (n == 0) return;
for (uint16_t i = 0; i < n; i++)
spiTransfer(buf[i]);
}
void spiSendBlock(uint8_t token, const uint8_t* buf) {
spiTransfer(token);
for (uint16_t i = 0; i < 512; i++)
spiTransfer(buf[i]);
}
#endif //MB(ALLIGATOR)
#endif // ENABLED(SOFTWARE_SPI)
#endif // ARDUINO_ARCH_SAM

163
Marlin/src/HAL/HAL_DUE/u8g_com_HAL_DUE_shared_hw_spi.cpp
View File

@ -1,163 +0,0 @@
/**
* Marlin 3D Printer Firmware
* Copyright (C) 2016, 2017, 2018 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
*
* Based on Sprinter and grbl.
* Copyright (C) 2011 Camiel Gubbels / Erik van der Zalm
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
/*
based on u8g_com_msp430_hw_spi.c
Universal 8bit Graphics Library
Copyright (c) 2012, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifdef __SAM3X8E__
// #include <inttypes.h>
// #include "src/core/macros.h"
// #include "Configuration.h"
#include "../../Marlin.h"
#include "../../inc/MarlinConfig.h"
#include <U8glib.h>
#define SPI_FULL_SPEED 0
#define SPI_HALF_SPEED 1
#define SPI_QUARTER_SPEED 2
#define SPI_EIGHTH_SPEED 3
#define SPI_SIXTEENTH_SPEED 4
#define SPI_SPEED_5 5
#define SPI_SPEED_6 6
void spiBegin();
void spiInit(uint8_t spiRate);
void spiSend(uint8_t b);
void spiSend(const uint8_t* buf, size_t n);
#include <Arduino.h>
#include "../../core/macros.h"
#include "fastio_Due.h"
void u8g_SetPIOutput_DUE_hw_spi(u8g_t *u8g, uint8_t pin_index) {
PIO_Configure(g_APinDescription[u8g->pin_list[pin_index]].pPort, PIO_OUTPUT_1,
g_APinDescription[u8g->pin_list[pin_index]].ulPin, g_APinDescription[u8g->pin_list[pin_index]].ulPinConfiguration); // OUTPUT
}
void u8g_SetPILevel_DUE_hw_spi(u8g_t *u8g, uint8_t pin_index, uint8_t level) {
volatile Pio* port = g_APinDescription[u8g->pin_list[pin_index]].pPort;
uint32_t mask = g_APinDescription[u8g->pin_list[pin_index]].ulPin;
if (level) port->PIO_SODR = mask;
else port->PIO_CODR = mask;
}
uint8_t u8g_com_HAL_DUE_shared_hw_spi_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr)
{
switch(msg)
{
case U8G_COM_MSG_STOP:
break;
case U8G_COM_MSG_INIT:
u8g_SetPILevel_DUE_hw_spi(u8g, U8G_PI_CS, 1);
u8g_SetPILevel_DUE_hw_spi(u8g, U8G_PI_A0, 1);
u8g_SetPIOutput_DUE_hw_spi(u8g, U8G_PI_CS);
u8g_SetPIOutput_DUE_hw_spi(u8g, U8G_PI_A0);
u8g_Delay(5);
spiBegin();
#ifndef SPI_SPEED
#define SPI_SPEED SPI_FULL_SPEED // use same SPI speed as SD card
#endif
spiInit(2);
break;
case U8G_COM_MSG_ADDRESS: /* define cmd (arg_val = 0) or data mode (arg_val = 1) */
u8g_SetPILevel_DUE_hw_spi(u8g, U8G_PI_A0, arg_val);
break;
case U8G_COM_MSG_CHIP_SELECT:
u8g_SetPILevel_DUE_hw_spi(u8g, U8G_PI_CS, (arg_val ? 0 : 1));
break;
case U8G_COM_MSG_RESET:
break;
case U8G_COM_MSG_WRITE_BYTE:
spiSend((uint8_t)arg_val);
break;
case U8G_COM_MSG_WRITE_SEQ: {
uint8_t *ptr = (uint8_t*) arg_ptr;
while (arg_val > 0) {
spiSend(*ptr++);
arg_val--;
}
}
break;
case U8G_COM_MSG_WRITE_SEQ_P: {
uint8_t *ptr = (uint8_t*) arg_ptr;
while (arg_val > 0) {
spiSend(*ptr++);
arg_val--;
}
}
break;
}
return 1;
}
#endif //__SAM3X8E__