📝 KHz => kHz (#23512)

This commit is contained in:
Scott Lahteine 2022-01-10 19:49:03 -06:00
parent c1d3e4634c
commit b6c37960e8
11 changed files with 16 additions and 16 deletions

View File

@ -567,8 +567,8 @@
* *
* USE_OCR2A_AS_TOP [undefined by default] * USE_OCR2A_AS_TOP [undefined by default]
* Boards that use TIMER2 for PWM have limitations resulting in only a few possible frequencies on TIMER2: * Boards that use TIMER2 for PWM have limitations resulting in only a few possible frequencies on TIMER2:
* 16MHz MCUs: [62.5KHz, 31.4KHz (default), 7.8KHz, 3.92KHz, 1.95KHz, 977Hz, 488Hz, 244Hz, 60Hz, 122Hz, 30Hz] * 16MHz MCUs: [62.5kHz, 31.4kHz (default), 7.8kHz, 3.92kHz, 1.95kHz, 977Hz, 488Hz, 244Hz, 60Hz, 122Hz, 30Hz]
* 20MHz MCUs: [78.1KHz, 39.2KHz (default), 9.77KHz, 4.9KHz, 2.44KHz, 1.22KHz, 610Hz, 305Hz, 153Hz, 76Hz, 38Hz] * 20MHz MCUs: [78.1kHz, 39.2kHz (default), 9.77kHz, 4.9kHz, 2.44kHz, 1.22kHz, 610Hz, 305Hz, 153Hz, 76Hz, 38Hz]
* A greater range can be achieved by enabling USE_OCR2A_AS_TOP. But note that this option blocks the use of * A greater range can be achieved by enabling USE_OCR2A_AS_TOP. But note that this option blocks the use of
* PWM on pin OC2A. Only use this option if you don't need PWM on 0C2A. (Check your schematic.) * PWM on pin OC2A. Only use this option if you don't need PWM on 0C2A. (Check your schematic.)
* USE_OCR2A_AS_TOP sacrifices duty cycle control resolution to achieve this broader range of frequencies. * USE_OCR2A_AS_TOP sacrifices duty cycle control resolution to achieve this broader range of frequencies.

View File

@ -245,7 +245,7 @@ uint16_t set_pwm_frequency_hz(const_float_t hz, const float dca, const float dcb
float count = 0; float count = 0;
if (hz > 0 && (dca || dcb || dcc)) { if (hz > 0 && (dca || dcb || dcc)) {
count = float(F_CPU) / hz; // 1x prescaler, TOP for 16MHz base freq. count = float(F_CPU) / hz; // 1x prescaler, TOP for 16MHz base freq.
uint16_t prescaler; // Range of 30.5Hz (65535) 64.5KHz (>31) uint16_t prescaler; // Range of 30.5Hz (65535) 64.5kHz (>31)
if (count >= 255. * 256.) { prescaler = 1024; SET_CS(5, PRESCALER_1024); } if (count >= 255. * 256.) { prescaler = 1024; SET_CS(5, PRESCALER_1024); }
else if (count >= 255. * 64.) { prescaler = 256; SET_CS(5, PRESCALER_256); } else if (count >= 255. * 64.) { prescaler = 256; SET_CS(5, PRESCALER_256); }
@ -277,7 +277,7 @@ uint16_t set_pwm_frequency_hz(const_float_t hz, const float dca, const float dcb
// Restore the default for Timer 5 // Restore the default for Timer 5
SET_WGM(5, PWM_PC_8); // PWM 8-bit (Phase Correct) SET_WGM(5, PWM_PC_8); // PWM 8-bit (Phase Correct)
SET_COMS(5, NORMAL, NORMAL, NORMAL); // Do nothing SET_COMS(5, NORMAL, NORMAL, NORMAL); // Do nothing
SET_CS(5, PRESCALER_64); // 16MHz / 64 = 250KHz SET_CS(5, PRESCALER_64); // 16MHz / 64 = 250kHz
OCR5A = OCR5B = OCR5C = 0; OCR5A = OCR5B = OCR5C = 0;
} }
return round(count); return round(count);

View File

@ -25,7 +25,7 @@
* is NOT used to directly toggle pins. The ISR writes to the pin assigned to * is NOT used to directly toggle pins. The ISR writes to the pin assigned to
* that interrupt. * that interrupt.
* *
* All PWMs use the same repetition rate. The G2 needs about 10KHz min in order to * All PWMs use the same repetition rate. The G2 needs about 10kHz min in order to
* not have obvious ripple on the Vref signals. * not have obvious ripple on the Vref signals.
* *
* The data structures are setup to minimize the computation done by the ISR which * The data structures are setup to minimize the computation done by the ISR which

View File

@ -53,7 +53,7 @@
* The net result is that both the g_pinStatus[pin] array and the PIO_OSR register * The net result is that both the g_pinStatus[pin] array and the PIO_OSR register
* needs to be looked at when determining if a pin is an input or an output. * needs to be looked at when determining if a pin is an input or an output.
* *
* b) Due has only pins 6, 7, 8 & 9 enabled for PWMs. FYI - they run at 1KHz * b) Due has only pins 6, 7, 8 & 9 enabled for PWMs. FYI - they run at 1kHz
* *
* c) NUM_DIGITAL_PINS does not include the analog pins * c) NUM_DIGITAL_PINS does not include the analog pins
* *

View File

@ -79,7 +79,7 @@ void HAL_timer_start(const uint8_t timer_num, const uint32_t frequency) {
rtc->MODE0.INTENCLR.reg = RTC_MODE0_INTENCLR_CMP0; rtc->MODE0.INTENCLR.reg = RTC_MODE0_INTENCLR_CMP0;
// RTC clock setup // RTC clock setup
OSC32KCTRL->RTCCTRL.reg = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K; // External 32.768KHz oscillator OSC32KCTRL->RTCCTRL.reg = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K; // External 32.768kHz oscillator
// Stop timer, just in case, to be able to reconfigure it // Stop timer, just in case, to be able to reconfigure it
rtc->MODE0.CTRLA.bit.ENABLE = false; rtc->MODE0.CTRLA.bit.ENABLE = false;

View File

@ -59,7 +59,7 @@ DMA_HandleTypeDef hdma_sdio;
/* /*
SDIO_INIT_CLK_DIV is 118 SDIO_INIT_CLK_DIV is 118
SDIO clock frequency is 48MHz / (TRANSFER_CLOCK_DIV + 2) SDIO clock frequency is 48MHz / (TRANSFER_CLOCK_DIV + 2)
SDIO init clock frequency should not exceed 400KHz = 48MHz / (118 + 2) SDIO init clock frequency should not exceed 400kHz = 48MHz / (118 + 2)
Default TRANSFER_CLOCK_DIV is 2 (118 / 40) Default TRANSFER_CLOCK_DIV is 2 (118 / 40)
Default SDIO clock frequency is 48MHz / (2 + 2) = 12 MHz Default SDIO clock frequency is 48MHz / (2 + 2) = 12 MHz

View File

@ -53,7 +53,7 @@
// b7 b6 b5 b4 ~b4 ... hi bits, NOT last bit // b7 b6 b5 b4 ~b4 ... hi bits, NOT last bit
// b3 b2 b1 b0 ~b0 ... lo bits, NOT last bit // b3 b2 b1 b0 ~b0 ... lo bits, NOT last bit
// //
void M672_send(uint8_t b) { // bit rate requirement: 1KHz +/- 30% void M672_send(uint8_t b) { // bit rate requirement: 1kHz +/- 30%
LOOP_L_N(bits, 14) { LOOP_L_N(bits, 14) {
switch (bits) { switch (bits) {
default: { OUT_WRITE(SMART_EFFECTOR_MOD_PIN, !!(b & 0x80)); b <<= 1; break; } // send bit, shift next into place default: { OUT_WRITE(SMART_EFFECTOR_MOD_PIN, !!(b & 0x80)); b <<= 1; break; } // send bit, shift next into place

View File

@ -43,7 +43,7 @@
* *
* If no PWM pin is defined then M3/M4 just turns it on. * If no PWM pin is defined then M3/M4 just turns it on.
* *
* At least 12.8KHz (50Hz * 256) is needed for Spindle PWM. * At least 12.8kHz (50Hz * 256) is needed for Spindle PWM.
* Hardware PWM is required on AVR. ISRs are too slow. * Hardware PWM is required on AVR. ISRs are too slow.
* *
* NOTE: WGM for timers 3, 4, and 5 must be either Mode 1 or Mode 5. * NOTE: WGM for timers 3, 4, and 5 must be either Mode 1 or Mode 5.

View File

@ -352,7 +352,7 @@ void Endstops::init() {
} // Endstops::init } // Endstops::init
// Called at ~1KHz from Temperature ISR: Poll endstop state if required // Called at ~1kHz from Temperature ISR: Poll endstop state if required
void Endstops::poll() { void Endstops::poll() {
TERN_(PINS_DEBUGGING, run_monitor()); // Report changes in endstop status TERN_(PINS_DEBUGGING, run_monitor()); // Report changes in endstop status
@ -403,7 +403,7 @@ void Endstops::not_homing() {
void Endstops::resync() { void Endstops::resync() {
if (!abort_enabled()) return; // If endstops/probes are disabled the loop below can hang if (!abort_enabled()) return; // If endstops/probes are disabled the loop below can hang
// Wait for Temperature ISR to run at least once (runs at 1KHz) // Wait for Temperature ISR to run at least once (runs at 1kHz)
TERN(ENDSTOP_INTERRUPTS_FEATURE, update(), safe_delay(2)); TERN(ENDSTOP_INTERRUPTS_FEATURE, update(), safe_delay(2));
while (TERN0(ENDSTOP_NOISE_THRESHOLD, endstop_poll_count)) safe_delay(1); while (TERN0(ENDSTOP_NOISE_THRESHOLD, endstop_poll_count)) safe_delay(1);
} }

View File

@ -3007,8 +3007,8 @@ public:
}; };
/** /**
* Handle various ~1KHz tasks associated with temperature * Handle various ~1kHz tasks associated with temperature
* - Heater PWM (~1KHz with scaler) * - Heater PWM (~1kHz with scaler)
* - LCD Button polling (~500Hz) * - LCD Button polling (~500Hz)
* - Start / Read one ADC sensor * - Start / Read one ADC sensor
* - Advance Babysteps * - Advance Babysteps
@ -3510,7 +3510,7 @@ void Temperature::isr() {
adc_sensor_state = next_sensor_state; adc_sensor_state = next_sensor_state;
// //
// Additional ~1KHz Tasks // Additional ~1kHz Tasks
// //
#if ENABLED(BABYSTEPPING) && DISABLED(INTEGRATED_BABYSTEPPING) #if ENABLED(BABYSTEPPING) && DISABLED(INTEGRATED_BABYSTEPPING)

View File

@ -118,7 +118,7 @@ extern "C" {
#endif #endif
#ifndef LSE_STARTUP_TIMEOUT #ifndef LSE_STARTUP_TIMEOUT
#define LSE_STARTUP_TIMEOUT 50U // No 32.7KHz LSE on this board, reduced to avoid delays #define LSE_STARTUP_TIMEOUT 50U // No 32.7kHz LSE on this board, reduced to avoid delays
#endif #endif
/* Tip: To avoid modifying this file each time you need to use different HSE, /* Tip: To avoid modifying this file each time you need to use different HSE,