Merge pull request #10983 from thinkyhead/bf2_xon_xoff_changes
[2.0.x] Serial handshaking fixes / debug
This commit is contained in:
commit
ae15c5af88
@ -56,16 +56,15 @@
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ring_buffer_r rx_buffer = { { 0 }, 0, 0 };
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ring_buffer_r rx_buffer = { { 0 }, 0, 0 };
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#if TX_BUFFER_SIZE > 0
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#if TX_BUFFER_SIZE > 0
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ring_buffer_t tx_buffer = { { 0 }, 0, 0 };
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ring_buffer_t tx_buffer = { { 0 }, 0, 0 };
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static bool _written;
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#endif
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#endif
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static bool _written;
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#endif
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#endif
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#if ENABLED(SERIAL_XON_XOFF)
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#if ENABLED(SERIAL_XON_XOFF)
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constexpr uint8_t XON_XOFF_CHAR_SENT = 0x80; // XON / XOFF Character was sent
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constexpr uint8_t XON_XOFF_CHAR_SENT = 0x80, // XON / XOFF Character was sent
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constexpr uint8_t XON_XOFF_CHAR_MASK = 0x1F; // XON / XOFF character to send
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XON_XOFF_CHAR_MASK = 0x1F; // XON / XOFF character to send
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// XON / XOFF character definitions
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// XON / XOFF character definitions
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constexpr uint8_t XON_CHAR = 17;
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constexpr uint8_t XON_CHAR = 17, XOFF_CHAR = 19;
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constexpr uint8_t XOFF_CHAR = 19;
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uint8_t xon_xoff_state = XON_XOFF_CHAR_SENT | XON_CHAR;
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uint8_t xon_xoff_state = XON_XOFF_CHAR_SENT | XON_CHAR;
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#endif
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#endif
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@ -73,6 +72,14 @@
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uint8_t rx_dropped_bytes = 0;
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uint8_t rx_dropped_bytes = 0;
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#endif
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#endif
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#if ENABLED(SERIAL_STATS_RX_BUFFER_OVERRUNS)
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uint8_t rx_buffer_overruns = 0;
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#endif
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#if ENABLED(SERIAL_STATS_RX_FRAMING_ERRORS)
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uint8_t rx_framing_errors = 0;
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#endif
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#if ENABLED(SERIAL_STATS_MAX_RX_QUEUED)
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#if ENABLED(SERIAL_STATS_MAX_RX_QUEUED)
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ring_buffer_pos_t rx_max_enqueued = 0;
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ring_buffer_pos_t rx_max_enqueued = 0;
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#endif
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#endif
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@ -91,125 +98,209 @@
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static EmergencyParser::State emergency_state; // = EP_RESET
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static EmergencyParser::State emergency_state; // = EP_RESET
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#endif
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#endif
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const ring_buffer_pos_t h = rx_buffer.head,
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// Get the tail - Nothing can alter its value while we are at this ISR
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i = (ring_buffer_pos_t)(h + 1) & (ring_buffer_pos_t)(RX_BUFFER_SIZE - 1);
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const ring_buffer_pos_t t = rx_buffer.tail;
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// Read the character
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// Get the head pointer
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const uint8_t c = M_UDRx;
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ring_buffer_pos_t h = rx_buffer.head;
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// Get the next element
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ring_buffer_pos_t i = (ring_buffer_pos_t)(h + 1) & (ring_buffer_pos_t)(RX_BUFFER_SIZE - 1);
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// This must read the M_UCSRxA register before reading the received byte to detect error causes
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#if ENABLED(SERIAL_STATS_DROPPED_RX)
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if (TEST(M_UCSRxA, M_DORx) && !++rx_dropped_bytes) --rx_dropped_bytes;
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#endif
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#if ENABLED(SERIAL_STATS_RX_BUFFER_OVERRUNS)
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if (TEST(M_UCSRxA, M_DORx) && !++rx_buffer_overruns) --rx_buffer_overruns;
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#endif
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#if ENABLED(SERIAL_STATS_RX_FRAMING_ERRORS)
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if (TEST(M_UCSRxA, M_FEx) && !++rx_framing_errors) --rx_framing_errors;
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#endif
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// Read the character from the USART
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uint8_t c = M_UDRx;
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#if ENABLED(EMERGENCY_PARSER)
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emergency_parser.update(emergency_state, c);
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#endif
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// If the character is to be stored at the index just before the tail
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// If the character is to be stored at the index just before the tail
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// (such that the head would advance to the current tail), the buffer is
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// (such that the head would advance to the current tail), the RX FIFO is
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// critical, so don't write the character or advance the head.
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// full, so don't write the character or advance the head.
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if (i != rx_buffer.tail) {
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if (i != t) {
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rx_buffer.buffer[h] = c;
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rx_buffer.buffer[h] = c;
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rx_buffer.head = i;
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h = i;
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}
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}
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else {
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#if ENABLED(SERIAL_STATS_DROPPED_RX)
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#if ENABLED(SERIAL_STATS_DROPPED_RX)
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if (!++rx_dropped_bytes) ++rx_dropped_bytes;
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else if (!++rx_dropped_bytes) --rx_dropped_bytes;
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#endif
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#endif
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}
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#if ENABLED(SERIAL_STATS_MAX_RX_QUEUED)
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#if ENABLED(SERIAL_STATS_MAX_RX_QUEUED)
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// calculate count of bytes stored into the RX buffer
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// Calculate count of bytes stored into the RX buffer
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ring_buffer_pos_t rx_count = (ring_buffer_pos_t)(rx_buffer.head - rx_buffer.tail) & (ring_buffer_pos_t)(RX_BUFFER_SIZE - 1);
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const ring_buffer_pos_t rx_count = (ring_buffer_pos_t)(h - t) & (ring_buffer_pos_t)(RX_BUFFER_SIZE - 1);
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// Keep track of the maximum count of enqueued bytes
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// Keep track of the maximum count of enqueued bytes
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NOLESS(rx_max_enqueued, rx_count);
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NOLESS(rx_max_enqueued, rx_count);
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#endif
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#endif
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#if ENABLED(SERIAL_XON_XOFF)
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#if ENABLED(SERIAL_XON_XOFF)
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// If the last char that was sent was an XON
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// for high speed transfers, we can use XON/XOFF protocol to do
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// software handshake and avoid overruns.
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if ((xon_xoff_state & XON_XOFF_CHAR_MASK) == XON_CHAR) {
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if ((xon_xoff_state & XON_XOFF_CHAR_MASK) == XON_CHAR) {
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// calculate count of bytes stored into the RX buffer
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// Bytes stored into the RX buffer
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ring_buffer_pos_t rx_count = (ring_buffer_pos_t)(rx_buffer.head - rx_buffer.tail) & (ring_buffer_pos_t)(RX_BUFFER_SIZE - 1);
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const ring_buffer_pos_t rx_count = (ring_buffer_pos_t)(h - t) & (ring_buffer_pos_t)(RX_BUFFER_SIZE - 1);
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// if we are above 12.5% of RX buffer capacity, send XOFF before
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// If over 12.5% of RX buffer capacity, send XOFF before running out of
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// we run out of RX buffer space .. We need 325 bytes @ 250kbits/s to
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// RX buffer space .. 325 bytes @ 250kbits/s needed to let the host react
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// let the host react and stop sending bytes. This translates to 13mS
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// and stop sending bytes. This translates to 13mS propagation time.
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// propagation time.
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if (rx_count >= (RX_BUFFER_SIZE) / 8) {
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if (rx_count >= (RX_BUFFER_SIZE) / 8) {
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// If TX interrupts are disabled and data register is empty,
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// At this point, definitely no TX interrupt was executing, since the TX isr can't be preempted.
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// just write the byte to the data register and be done. This
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// Don't enable the TX interrupt here as a means to trigger the XOFF char, because if it happens
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// shortcut helps significantly improve the effective datarate
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// to be in the middle of trying to disable the RX interrupt in the main program, eventually the
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// at high (>500kbit/s) bitrates, where interrupt overhead
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// enabling of the TX interrupt could be undone. The ONLY reliable thing this can do to ensure
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// becomes a slowdown.
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// the sending of the XOFF char is to send it HERE AND NOW.
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if (!TEST(M_UCSRxB, M_UDRIEx) && TEST(M_UCSRxA, M_UDREx)) {
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// Send an XOFF character
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// About to send the XOFF char
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M_UDRx = XOFF_CHAR;
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// clear the TXC bit -- "can be cleared by writing a one to its bit
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// location". This makes sure flush() won't return until the bytes
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// actually got written
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SBI(M_UCSRxA, M_TXCx);
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// And remember it was sent
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xon_xoff_state = XOFF_CHAR | XON_XOFF_CHAR_SENT;
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xon_xoff_state = XOFF_CHAR | XON_XOFF_CHAR_SENT;
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}
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else {
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// TX interrupts disabled, but buffer still not empty ... or
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// TX interrupts enabled. Reenable TX ints and schedule XOFF
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// character to be sent
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#if TX_BUFFER_SIZE > 0
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SBI(M_UCSRxB, M_UDRIEx);
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xon_xoff_state = XOFF_CHAR;
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#else
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// We are not using TX interrupts, we will have to send this manually
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while (!TEST(M_UCSRxA, M_UDREx)) sw_barrier();
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M_UDRx = XOFF_CHAR;
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// clear the TXC bit -- "can be cleared by writing a one to its bit
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// Wait until the TX register becomes empty and send it - Here there could be a problem
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// location". This makes sure flush() won't return until the bytes
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// - While waiting for the TX register to empty, the RX register could receive a new
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// actually got written
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// character. This must also handle that situation!
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SBI(M_UCSRxA, M_TXCx);
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while (!TEST(M_UCSRxA, M_UDREx)) {
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// And remember we already sent it
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if (TEST(M_UCSRxA,M_RXCx)) {
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xon_xoff_state = XOFF_CHAR | XON_XOFF_CHAR_SENT;
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// A char arrived while waiting for the TX buffer to be empty - Receive and process it!
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#endif
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}
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i = (ring_buffer_pos_t)(h + 1) & (ring_buffer_pos_t)(RX_BUFFER_SIZE - 1);
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}
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}
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// Read the character from the USART
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#endif // SERIAL_XON_XOFF
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c = M_UDRx;
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#if ENABLED(EMERGENCY_PARSER)
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#if ENABLED(EMERGENCY_PARSER)
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emergency_parser.update(emergency_state, c);
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emergency_parser.update(emergency_state, c);
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#endif
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#endif
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// If the character is to be stored at the index just before the tail
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// (such that the head would advance to the current tail), the FIFO is
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// full, so don't write the character or advance the head.
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if (i != t) {
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rx_buffer.buffer[h] = c;
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h = i;
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}
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#if ENABLED(SERIAL_STATS_DROPPED_RX)
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else if (!++rx_dropped_bytes) --rx_dropped_bytes;
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#endif
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}
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sw_barrier();
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}
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M_UDRx = XOFF_CHAR;
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// Clear the TXC bit -- "can be cleared by writing a one to its bit
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// location". This makes sure flush() won't return until the bytes
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// actually got written
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SBI(M_UCSRxA, M_TXCx);
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// At this point there could be a race condition between the write() function
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// and this sending of the XOFF char. This interrupt could happen between the
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// wait to be empty TX buffer loop and the actual write of the character. Since
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// the TX buffer is full because it's sending the XOFF char, the only way to be
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// sure the write() function will succeed is to wait for the XOFF char to be
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// completely sent. Since an extra character could be received during the wait
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// it must also be handled!
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while (!TEST(M_UCSRxA, M_UDREx)) {
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if (TEST(M_UCSRxA,M_RXCx)) {
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// A char arrived while waiting for the TX buffer to be empty - Receive and process it!
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i = (ring_buffer_pos_t)(h + 1) & (ring_buffer_pos_t)(RX_BUFFER_SIZE - 1);
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// Read the character from the USART
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c = M_UDRx;
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#if ENABLED(EMERGENCY_PARSER)
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emergency_parser.update(emergency_state, c);
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#endif
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// If the character is to be stored at the index just before the tail
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// (such that the head would advance to the current tail), the FIFO is
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// full, so don't write the character or advance the head.
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if (i != t) {
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rx_buffer.buffer[h] = c;
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h = i;
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}
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#if ENABLED(SERIAL_STATS_DROPPED_RX)
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else if (!++rx_dropped_bytes) --rx_dropped_bytes;
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#endif
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}
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sw_barrier();
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}
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// At this point everything is ready. The write() function won't
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// have any issues writing to the UART TX register if it needs to!
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}
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}
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#endif // SERIAL_XON_XOFF
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// Store the new head value
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rx_buffer.head = h;
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}
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}
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#if TX_BUFFER_SIZE > 0
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#if TX_BUFFER_SIZE > 0
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// (called with TX irqs disabled)
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// (called with TX irqs disabled)
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FORCE_INLINE void _tx_udr_empty_irq(void) {
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FORCE_INLINE void _tx_udr_empty_irq(void) {
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// If interrupts are enabled, there must be more data in the output
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// buffer.
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// Read positions
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uint8_t t = tx_buffer.tail;
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const uint8_t h = tx_buffer.head;
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#if ENABLED(SERIAL_XON_XOFF)
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#if ENABLED(SERIAL_XON_XOFF)
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// Do a priority insertion of an XON/XOFF char, if needed.
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// If an XON char is pending to be sent, do it now
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const uint8_t state = xon_xoff_state;
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if (xon_xoff_state == XON_CHAR) {
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if (!(state & XON_XOFF_CHAR_SENT)) {
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M_UDRx = state & XON_XOFF_CHAR_MASK;
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// Send the character
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xon_xoff_state = state | XON_XOFF_CHAR_SENT;
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M_UDRx = XON_CHAR;
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}
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else
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#endif
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{ // Send the next byte
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const uint8_t t = tx_buffer.tail, c = tx_buffer.buffer[t];
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tx_buffer.tail = (t + 1) & (TX_BUFFER_SIZE - 1);
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M_UDRx = c;
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}
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// clear the TXC bit -- "can be cleared by writing a one to its bit
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// clear the TXC bit -- "can be cleared by writing a one to its bit
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// location". This makes sure flush() won't return until the bytes
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// location". This makes sure flush() won't return until the bytes
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// actually got written
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// actually got written
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SBI(M_UCSRxA, M_TXCx);
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SBI(M_UCSRxA, M_TXCx);
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// Disable interrupts if the buffer is empty
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// Remember we sent it.
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if (tx_buffer.head == tx_buffer.tail)
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xon_xoff_state = XON_CHAR | XON_XOFF_CHAR_SENT;
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CBI(M_UCSRxB, M_UDRIEx);
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// If nothing else to transmit, just disable TX interrupts.
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if (h == t) CBI(M_UCSRxB, M_UDRIEx); // (Non-atomic, could be reenabled by the main program, but eventually this will succeed)
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return;
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}
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#endif
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// If nothing to transmit, just disable TX interrupts. This could
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// happen as the result of the non atomicity of the disabling of RX
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// interrupts that could end reenabling TX interrupts as a side effect.
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if (h == t) {
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CBI(M_UCSRxB, M_UDRIEx); // (Non-atomic, could be reenabled by the main program, but eventually this will succeed)
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return;
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}
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// There is something to TX, Send the next byte
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const uint8_t c = tx_buffer.buffer[t];
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t = (t + 1) & (TX_BUFFER_SIZE - 1);
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M_UDRx = c;
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tx_buffer.tail = t;
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// Clear the TXC bit (by writing a one to its bit location).
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// Ensures flush() won't return until the bytes are actually written/
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SBI(M_UCSRxA, M_TXCx);
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// Disable interrupts if there is nothing to transmit following this byte
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if (h == t) CBI(M_UCSRxB, M_UDRIEx); // (Non-atomic, could be reenabled by the main program, but eventually this will succeed)
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}
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}
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#ifdef M_USARTx_UDRE_vect
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#ifdef M_USARTx_UDRE_vect
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@ -253,8 +344,8 @@
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SBI(M_UCSRxB, M_RXCIEx);
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SBI(M_UCSRxB, M_RXCIEx);
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#if TX_BUFFER_SIZE > 0
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#if TX_BUFFER_SIZE > 0
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CBI(M_UCSRxB, M_UDRIEx);
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CBI(M_UCSRxB, M_UDRIEx);
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_written = false;
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#endif
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#endif
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_written = false;
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}
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}
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void MarlinSerial::end() {
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void MarlinSerial::end() {
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@ -281,11 +372,11 @@
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}
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}
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int MarlinSerial::read(void) {
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int MarlinSerial::read(void) {
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int v;
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#if RX_BUFFER_SIZE > 256
|
#if RX_BUFFER_SIZE > 256
|
||||||
// Disable RX interrupts to ensure atomic reads
|
// Disable RX interrupts to ensure atomic reads - This could reenable TX interrupts,
|
||||||
const bool isr_enabled = TEST(M_UCSRxB, M_RXCIEx);
|
// but this situation is explicitly handled at the TX isr, so no problems there
|
||||||
|
bool isr_enabled = TEST(M_UCSRxB, M_RXCIEx);
|
||||||
CBI(M_UCSRxB, M_RXCIEx);
|
CBI(M_UCSRxB, M_RXCIEx);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
@ -298,16 +389,19 @@
|
|||||||
|
|
||||||
ring_buffer_pos_t t = rx_buffer.tail;
|
ring_buffer_pos_t t = rx_buffer.tail;
|
||||||
|
|
||||||
if (h == t)
|
// If nothing to read, return now
|
||||||
v = -1;
|
if (h == t) return -1;
|
||||||
else {
|
|
||||||
v = rx_buffer.buffer[t];
|
// Get the next char
|
||||||
|
const int v = rx_buffer.buffer[t];
|
||||||
t = (ring_buffer_pos_t)(t + 1) & (RX_BUFFER_SIZE - 1);
|
t = (ring_buffer_pos_t)(t + 1) & (RX_BUFFER_SIZE - 1);
|
||||||
|
|
||||||
#if RX_BUFFER_SIZE > 256
|
#if RX_BUFFER_SIZE > 256
|
||||||
// Disable RX interrupts to ensure atomic write to tail, so
|
// Disable RX interrupts to ensure atomic write to tail, so
|
||||||
// the RX isr can't read partially updated values
|
// the RX isr can't read partially updated values - This could
|
||||||
const bool isr_enabled = TEST(M_UCSRxB, M_RXCIEx);
|
// reenable TX interrupts, but this situation is explicitly
|
||||||
|
// handled at the TX isr, so no problems there
|
||||||
|
isr_enabled = TEST(M_UCSRxB, M_RXCIEx);
|
||||||
CBI(M_UCSRxB, M_RXCIEx);
|
CBI(M_UCSRxB, M_RXCIEx);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
@ -320,21 +414,25 @@
|
|||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if ENABLED(SERIAL_XON_XOFF)
|
#if ENABLED(SERIAL_XON_XOFF)
|
||||||
|
// If the XOFF char was sent, or about to be sent...
|
||||||
if ((xon_xoff_state & XON_XOFF_CHAR_MASK) == XOFF_CHAR) {
|
if ((xon_xoff_state & XON_XOFF_CHAR_MASK) == XOFF_CHAR) {
|
||||||
|
|
||||||
// Get count of bytes in the RX buffer
|
// Get count of bytes in the RX buffer
|
||||||
ring_buffer_pos_t rx_count = (ring_buffer_pos_t)(h - t) & (ring_buffer_pos_t)(RX_BUFFER_SIZE - 1);
|
const ring_buffer_pos_t rx_count = (ring_buffer_pos_t)(h - t) & (ring_buffer_pos_t)(RX_BUFFER_SIZE - 1);
|
||||||
|
|
||||||
// When below 10% of RX buffer capacity, send XON before
|
|
||||||
// running out of RX buffer bytes
|
|
||||||
if (rx_count < (RX_BUFFER_SIZE) / 10) {
|
if (rx_count < (RX_BUFFER_SIZE) / 10) {
|
||||||
|
#if TX_BUFFER_SIZE > 0
|
||||||
|
// Signal we want an XON character to be sent.
|
||||||
|
xon_xoff_state = XON_CHAR;
|
||||||
|
// Enable TX isr. Non atomic, but it will eventually enable them
|
||||||
|
SBI(M_UCSRxB, M_UDRIEx);
|
||||||
|
#else
|
||||||
|
// If not using TX interrupts, we must send the XON char now
|
||||||
xon_xoff_state = XON_CHAR | XON_XOFF_CHAR_SENT;
|
xon_xoff_state = XON_CHAR | XON_XOFF_CHAR_SENT;
|
||||||
write(XON_CHAR);
|
while (!TEST(M_UCSRxA, M_UDREx)) sw_barrier();
|
||||||
return v;
|
M_UDRx = XON_CHAR;
|
||||||
|
#endif
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
}
|
|
||||||
|
|
||||||
return v;
|
return v;
|
||||||
}
|
}
|
||||||
@ -367,9 +465,19 @@
|
|||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if ENABLED(SERIAL_XON_XOFF)
|
#if ENABLED(SERIAL_XON_XOFF)
|
||||||
|
// If the XOFF char was sent, or about to be sent...
|
||||||
if ((xon_xoff_state & XON_XOFF_CHAR_MASK) == XOFF_CHAR) {
|
if ((xon_xoff_state & XON_XOFF_CHAR_MASK) == XOFF_CHAR) {
|
||||||
|
#if TX_BUFFER_SIZE > 0
|
||||||
|
// Signal we want an XON character to be sent.
|
||||||
|
xon_xoff_state = XON_CHAR;
|
||||||
|
// Enable TX isr. Non atomic, but it will eventually enable it.
|
||||||
|
SBI(M_UCSRxB, M_UDRIEx);
|
||||||
|
#else
|
||||||
|
// If not using TX interrupts, we must send the XON char now
|
||||||
xon_xoff_state = XON_CHAR | XON_XOFF_CHAR_SENT;
|
xon_xoff_state = XON_CHAR | XON_XOFF_CHAR_SENT;
|
||||||
write(XON_CHAR);
|
while (!TEST(M_UCSRxA, M_UDREx)) sw_barrier();
|
||||||
|
M_UDRx = XON_CHAR;
|
||||||
|
#endif
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
@ -383,6 +491,8 @@
|
|||||||
// be done. This shortcut helps significantly improve the
|
// be done. This shortcut helps significantly improve the
|
||||||
// effective datarate at high (>500kbit/s) bitrates, where
|
// effective datarate at high (>500kbit/s) bitrates, where
|
||||||
// interrupt overhead becomes a slowdown.
|
// interrupt overhead becomes a slowdown.
|
||||||
|
// Yes, there is a race condition between the sending of the
|
||||||
|
// XOFF char at the RX isr, but it is properly handled there
|
||||||
if (!TEST(M_UCSRxB, M_UDRIEx) && TEST(M_UCSRxA, M_UDREx)) {
|
if (!TEST(M_UCSRxB, M_UDRIEx) && TEST(M_UCSRxA, M_UDREx)) {
|
||||||
M_UDRx = c;
|
M_UDRx = c;
|
||||||
|
|
||||||
@ -395,61 +505,79 @@
|
|||||||
|
|
||||||
const uint8_t i = (tx_buffer.head + 1) & (TX_BUFFER_SIZE - 1);
|
const uint8_t i = (tx_buffer.head + 1) & (TX_BUFFER_SIZE - 1);
|
||||||
|
|
||||||
// If the output buffer is full, there's nothing for it other than to
|
// If global interrupts are disabled (as the result of being called from an ISR)...
|
||||||
// wait for the interrupt handler to empty it a bit
|
|
||||||
while (i == tx_buffer.tail) {
|
|
||||||
if (!ISRS_ENABLED()) {
|
if (!ISRS_ENABLED()) {
|
||||||
// Interrupts are disabled, so we'll have to poll the data
|
|
||||||
// register empty flag ourselves. If it is set, pretend an
|
// Make room by polling if it is possible to transmit, and do so!
|
||||||
// interrupt has happened and call the handler to free up
|
while (i == tx_buffer.tail) {
|
||||||
// space for us.
|
|
||||||
if (TEST(M_UCSRxA, M_UDREx))
|
// If we can transmit another byte, do it.
|
||||||
_tx_udr_empty_irq();
|
if (TEST(M_UCSRxA, M_UDREx)) _tx_udr_empty_irq();
|
||||||
}
|
|
||||||
// (else , the interrupt handler will free up space for us)
|
|
||||||
|
|
||||||
// Make sure compiler rereads tx_buffer.tail
|
// Make sure compiler rereads tx_buffer.tail
|
||||||
sw_barrier();
|
sw_barrier();
|
||||||
}
|
}
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
// Interrupts are enabled, just wait until there is space
|
||||||
|
while (i == tx_buffer.tail) { sw_barrier(); }
|
||||||
|
}
|
||||||
|
|
||||||
// Store new char. head is always safe to move
|
// Store new char. head is always safe to move
|
||||||
tx_buffer.buffer[tx_buffer.head] = c;
|
tx_buffer.buffer[tx_buffer.head] = c;
|
||||||
tx_buffer.head = i;
|
tx_buffer.head = i;
|
||||||
|
|
||||||
// Enable TX isr
|
// Enable TX isr - Non atomic, but it will eventually enable TX isr
|
||||||
SBI(M_UCSRxB, M_UDRIEx);
|
SBI(M_UCSRxB, M_UDRIEx);
|
||||||
return;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void MarlinSerial::flushTX(void) {
|
void MarlinSerial::flushTX(void) {
|
||||||
// TX
|
// No bytes written, no need to flush. This special case is needed since there's
|
||||||
// If we have never written a byte, no need to flush. This special
|
// no way to force the TXC (transmit complete) bit to 1 during initialization.
|
||||||
// case is needed since there is no way to force the TXC (transmit
|
if (!_written) return;
|
||||||
// complete) bit to 1 during initialization
|
|
||||||
if (!_written)
|
|
||||||
return;
|
|
||||||
|
|
||||||
while (TEST(M_UCSRxB, M_UDRIEx) || !TEST(M_UCSRxA, M_TXCx)) {
|
// If global interrupts are disabled (as the result of being called from an ISR)...
|
||||||
if (!ISRS_ENABLED()) {
|
if (!ISRS_ENABLED()) {
|
||||||
// Interrupts are globally disabled, but the DR empty
|
|
||||||
// interrupt should be enabled, so poll the DR empty flag to
|
// Wait until everything was transmitted - We must do polling, as interrupts are disabled
|
||||||
// prevent deadlock
|
while (tx_buffer.head != tx_buffer.tail || !TEST(M_UCSRxA, M_TXCx)) {
|
||||||
|
|
||||||
|
// If there is more space, send an extra character
|
||||||
if (TEST(M_UCSRxA, M_UDREx))
|
if (TEST(M_UCSRxA, M_UDREx))
|
||||||
_tx_udr_empty_irq();
|
_tx_udr_empty_irq();
|
||||||
}
|
|
||||||
sw_barrier();
|
sw_barrier();
|
||||||
}
|
}
|
||||||
// If we get here, nothing is queued anymore (DRIE is disabled) and
|
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
// Wait until everything was transmitted
|
||||||
|
while (tx_buffer.head != tx_buffer.tail || !TEST(M_UCSRxA, M_TXCx)) sw_barrier();
|
||||||
|
}
|
||||||
|
|
||||||
|
// At this point nothing is queued anymore (DRIE is disabled) and
|
||||||
// the hardware finished transmission (TXC is set).
|
// the hardware finished transmission (TXC is set).
|
||||||
}
|
}
|
||||||
|
|
||||||
#else // TX_BUFFER_SIZE == 0
|
#else // TX_BUFFER_SIZE == 0
|
||||||
|
|
||||||
void MarlinSerial::write(const uint8_t c) {
|
void MarlinSerial::write(const uint8_t c) {
|
||||||
|
_written = true;
|
||||||
while (!TEST(M_UCSRxA, M_UDREx)) sw_barrier();
|
while (!TEST(M_UCSRxA, M_UDREx)) sw_barrier();
|
||||||
M_UDRx = c;
|
M_UDRx = c;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void MarlinSerial::flushTX(void) {
|
||||||
|
// No bytes written, no need to flush. This special case is needed since there's
|
||||||
|
// no way to force the TXC (transmit complete) bit to 1 during initialization.
|
||||||
|
if (!_written) return;
|
||||||
|
|
||||||
|
// Wait until everything was transmitted
|
||||||
|
while (!TEST(M_UCSRxA, M_TXCx)) sw_barrier();
|
||||||
|
|
||||||
|
// At this point nothing is queued anymore (DRIE is disabled) and
|
||||||
|
// the hardware finished transmission (TXC is set).
|
||||||
|
}
|
||||||
#endif // TX_BUFFER_SIZE == 0
|
#endif // TX_BUFFER_SIZE == 0
|
||||||
|
|
||||||
/**
|
/**
|
||||||
@ -473,13 +601,9 @@
|
|||||||
}
|
}
|
||||||
|
|
||||||
void MarlinSerial::print(long n, int base) {
|
void MarlinSerial::print(long n, int base) {
|
||||||
if (base == 0)
|
if (base == 0) write(n);
|
||||||
write(n);
|
|
||||||
else if (base == 10) {
|
else if (base == 10) {
|
||||||
if (n < 0) {
|
if (n < 0) { print('-'); n = -n; }
|
||||||
print('-');
|
|
||||||
n = -n;
|
|
||||||
}
|
|
||||||
printNumber(n, 10);
|
printNumber(n, 10);
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
|
@ -62,6 +62,9 @@
|
|||||||
#define M_TXCx SERIAL_REGNAME(TXC,SERIAL_PORT,)
|
#define M_TXCx SERIAL_REGNAME(TXC,SERIAL_PORT,)
|
||||||
#define M_RXCIEx SERIAL_REGNAME(RXCIE,SERIAL_PORT,)
|
#define M_RXCIEx SERIAL_REGNAME(RXCIE,SERIAL_PORT,)
|
||||||
#define M_UDREx SERIAL_REGNAME(UDRE,SERIAL_PORT,)
|
#define M_UDREx SERIAL_REGNAME(UDRE,SERIAL_PORT,)
|
||||||
|
#define M_FEx SERIAL_REGNAME(FE,SERIAL_PORT,)
|
||||||
|
#define M_DORx SERIAL_REGNAME(DOR,SERIAL_PORT,)
|
||||||
|
#define M_UPEx SERIAL_REGNAME(UPE,SERIAL_PORT,)
|
||||||
#define M_UDRIEx SERIAL_REGNAME(UDRIE,SERIAL_PORT,)
|
#define M_UDRIEx SERIAL_REGNAME(UDRIE,SERIAL_PORT,)
|
||||||
#define M_UDRx SERIAL_REGNAME(UDR,SERIAL_PORT,)
|
#define M_UDRx SERIAL_REGNAME(UDR,SERIAL_PORT,)
|
||||||
#define M_UBRRxH SERIAL_REGNAME(UBRR,SERIAL_PORT,H)
|
#define M_UBRRxH SERIAL_REGNAME(UBRR,SERIAL_PORT,H)
|
||||||
@ -75,6 +78,7 @@
|
|||||||
#define HEX 16
|
#define HEX 16
|
||||||
#define OCT 8
|
#define OCT 8
|
||||||
#define BIN 2
|
#define BIN 2
|
||||||
|
#define BYTE 0
|
||||||
|
|
||||||
#ifndef USBCON
|
#ifndef USBCON
|
||||||
// We're using a ring buffer (I think), in which rx_buffer_head is the index of the
|
// We're using a ring buffer (I think), in which rx_buffer_head is the index of the
|
||||||
@ -90,6 +94,14 @@
|
|||||||
extern uint8_t rx_dropped_bytes;
|
extern uint8_t rx_dropped_bytes;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if ENABLED(SERIAL_STATS_RX_BUFFER_OVERRUNS)
|
||||||
|
extern uint8_t rx_buffer_overruns;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if ENABLED(SERIAL_STATS_RX_FRAMING_ERRORS)
|
||||||
|
extern uint8_t rx_framing_errors;
|
||||||
|
#endif
|
||||||
|
|
||||||
#if ENABLED(SERIAL_STATS_MAX_RX_QUEUED)
|
#if ENABLED(SERIAL_STATS_MAX_RX_QUEUED)
|
||||||
extern ring_buffer_pos_t rx_max_enqueued;
|
extern ring_buffer_pos_t rx_max_enqueued;
|
||||||
#endif
|
#endif
|
||||||
@ -105,14 +117,20 @@
|
|||||||
static void flush(void);
|
static void flush(void);
|
||||||
static ring_buffer_pos_t available(void);
|
static ring_buffer_pos_t available(void);
|
||||||
static void write(const uint8_t c);
|
static void write(const uint8_t c);
|
||||||
#if TX_BUFFER_SIZE > 0
|
|
||||||
static void flushTX(void);
|
static void flushTX(void);
|
||||||
#endif
|
|
||||||
|
|
||||||
#if ENABLED(SERIAL_STATS_DROPPED_RX)
|
#if ENABLED(SERIAL_STATS_DROPPED_RX)
|
||||||
FORCE_INLINE static uint32_t dropped() { return rx_dropped_bytes; }
|
FORCE_INLINE static uint32_t dropped() { return rx_dropped_bytes; }
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if ENABLED(SERIAL_STATS_RX_BUFFER_OVERRUNS)
|
||||||
|
FORCE_INLINE static uint32_t buffer_overruns() { return rx_buffer_overruns; }
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if ENABLED(SERIAL_STATS_RX_FRAMING_ERRORS)
|
||||||
|
FORCE_INLINE static uint32_t framing_errors() { return rx_framing_errors; }
|
||||||
|
#endif
|
||||||
|
|
||||||
#if ENABLED(SERIAL_STATS_MAX_RX_QUEUED)
|
#if ENABLED(SERIAL_STATS_MAX_RX_QUEUED)
|
||||||
FORCE_INLINE static ring_buffer_pos_t rxMaxEnqueued() { return rx_max_enqueued; }
|
FORCE_INLINE static ring_buffer_pos_t rxMaxEnqueued() { return rx_max_enqueued; }
|
||||||
#endif
|
#endif
|
||||||
@ -122,8 +140,8 @@
|
|||||||
FORCE_INLINE static void print(const String& s) { for (int i = 0; i < (int)s.length(); i++) write(s[i]); }
|
FORCE_INLINE static void print(const String& s) { for (int i = 0; i < (int)s.length(); i++) write(s[i]); }
|
||||||
FORCE_INLINE static void print(const char* str) { write(str); }
|
FORCE_INLINE static void print(const char* str) { write(str); }
|
||||||
|
|
||||||
static void print(char, int = 0);
|
static void print(char, int = BYTE);
|
||||||
static void print(unsigned char, int = 0);
|
static void print(unsigned char, int = BYTE);
|
||||||
static void print(int, int = DEC);
|
static void print(int, int = DEC);
|
||||||
static void print(unsigned int, int = DEC);
|
static void print(unsigned int, int = DEC);
|
||||||
static void print(long, int = DEC);
|
static void print(long, int = DEC);
|
||||||
@ -132,8 +150,8 @@
|
|||||||
|
|
||||||
static void println(const String& s);
|
static void println(const String& s);
|
||||||
static void println(const char[]);
|
static void println(const char[]);
|
||||||
static void println(char, int = 0);
|
static void println(char, int = BYTE);
|
||||||
static void println(unsigned char, int = 0);
|
static void println(unsigned char, int = BYTE);
|
||||||
static void println(int, int = DEC);
|
static void println(int, int = DEC);
|
||||||
static void println(unsigned int, int = DEC);
|
static void println(unsigned int, int = DEC);
|
||||||
static void println(long, int = DEC);
|
static void println(long, int = DEC);
|
||||||
|
@ -74,15 +74,14 @@
|
|||||||
ring_buffer_r rx_buffer = { { 0 }, 0, 0 };
|
ring_buffer_r rx_buffer = { { 0 }, 0, 0 };
|
||||||
#if TX_BUFFER_SIZE > 0
|
#if TX_BUFFER_SIZE > 0
|
||||||
ring_buffer_t tx_buffer = { { 0 }, 0, 0 };
|
ring_buffer_t tx_buffer = { { 0 }, 0, 0 };
|
||||||
static bool _written;
|
|
||||||
#endif
|
#endif
|
||||||
|
static bool _written;
|
||||||
|
|
||||||
#if ENABLED(SERIAL_XON_XOFF)
|
#if ENABLED(SERIAL_XON_XOFF)
|
||||||
constexpr uint8_t XON_XOFF_CHAR_SENT = 0x80; // XON / XOFF Character was sent
|
constexpr uint8_t XON_XOFF_CHAR_SENT = 0x80, // XON / XOFF Character was sent
|
||||||
constexpr uint8_t XON_XOFF_CHAR_MASK = 0x1F; // XON / XOFF character to send
|
XON_XOFF_CHAR_MASK = 0x1F; // XON / XOFF character to send
|
||||||
// XON / XOFF character definitions
|
// XON / XOFF character definitions
|
||||||
constexpr uint8_t XON_CHAR = 17;
|
constexpr uint8_t XON_CHAR = 17, XOFF_CHAR = 19;
|
||||||
constexpr uint8_t XOFF_CHAR = 19;
|
|
||||||
uint8_t xon_xoff_state = XON_XOFF_CHAR_SENT | XON_CHAR;
|
uint8_t xon_xoff_state = XON_XOFF_CHAR_SENT | XON_CHAR;
|
||||||
|
|
||||||
// Validate that RX buffer size is at least 4096 bytes- According to several experiments, on
|
// Validate that RX buffer size is at least 4096 bytes- According to several experiments, on
|
||||||
@ -99,6 +98,14 @@
|
|||||||
uint8_t rx_dropped_bytes = 0;
|
uint8_t rx_dropped_bytes = 0;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if ENABLED(SERIAL_STATS_RX_BUFFER_OVERRUNS)
|
||||||
|
uint8_t rx_buffer_overruns = 0;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if ENABLED(SERIAL_STATS_RX_FRAMING_ERRORS)
|
||||||
|
uint8_t rx_framing_errors = 0;
|
||||||
|
#endif
|
||||||
|
|
||||||
#if ENABLED(SERIAL_STATS_MAX_RX_QUEUED)
|
#if ENABLED(SERIAL_STATS_MAX_RX_QUEUED)
|
||||||
ring_buffer_pos_t rx_max_enqueued = 0;
|
ring_buffer_pos_t rx_max_enqueued = 0;
|
||||||
#endif
|
#endif
|
||||||
@ -110,132 +117,218 @@
|
|||||||
#include "../../feature/emergency_parser.h"
|
#include "../../feature/emergency_parser.h"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
// (called with RX interrupts disabled)
|
||||||
FORCE_INLINE void store_rxd_char() {
|
FORCE_INLINE void store_rxd_char() {
|
||||||
|
|
||||||
#if ENABLED(EMERGENCY_PARSER)
|
#if ENABLED(EMERGENCY_PARSER)
|
||||||
static EmergencyParser::State emergency_state; // = EP_RESET
|
static EmergencyParser::State emergency_state; // = EP_RESET
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
const ring_buffer_pos_t h = rx_buffer.head,
|
// Get the tail - Nothing can alter its value while we are at this ISR
|
||||||
i = (ring_buffer_pos_t)(h + 1) & (ring_buffer_pos_t)(RX_BUFFER_SIZE - 1);
|
const ring_buffer_pos_t t = rx_buffer.tail;
|
||||||
|
|
||||||
// Read the character
|
// Get the head pointer
|
||||||
const uint8_t c = HWUART->UART_RHR;
|
ring_buffer_pos_t h = rx_buffer.head;
|
||||||
|
|
||||||
|
// Get the next element
|
||||||
|
ring_buffer_pos_t i = (ring_buffer_pos_t)(h + 1) & (ring_buffer_pos_t)(RX_BUFFER_SIZE - 1);
|
||||||
|
|
||||||
|
// Read the character from the USART
|
||||||
|
uint8_t c = HWUART->UART_RHR;
|
||||||
|
|
||||||
|
#if ENABLED(EMERGENCY_PARSER)
|
||||||
|
emergency_parser.update(emergency_state, c);
|
||||||
|
#endif
|
||||||
|
|
||||||
// If the character is to be stored at the index just before the tail
|
// If the character is to be stored at the index just before the tail
|
||||||
// (such that the head would advance to the current tail), the buffer is
|
// (such that the head would advance to the current tail), the RX FIFO is
|
||||||
// critical, so don't write the character or advance the head.
|
// full, so don't write the character or advance the head.
|
||||||
if (i != rx_buffer.tail) {
|
if (i != t) {
|
||||||
rx_buffer.buffer[h] = c;
|
rx_buffer.buffer[h] = c;
|
||||||
rx_buffer.head = i;
|
h = i;
|
||||||
}
|
}
|
||||||
#if ENABLED(SERIAL_STATS_DROPPED_RX)
|
#if ENABLED(SERIAL_STATS_DROPPED_RX)
|
||||||
else if (!++rx_dropped_bytes) ++rx_dropped_bytes;
|
else if (!++rx_dropped_bytes) --rx_dropped_bytes;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if ENABLED(SERIAL_STATS_MAX_RX_QUEUED)
|
#if ENABLED(SERIAL_STATS_MAX_RX_QUEUED)
|
||||||
// calculate count of bytes stored into the RX buffer
|
const ring_buffer_pos_t rx_count = (ring_buffer_pos_t)(h - t) & (ring_buffer_pos_t)(RX_BUFFER_SIZE - 1);
|
||||||
ring_buffer_pos_t rx_count = (ring_buffer_pos_t)(rx_buffer.head - rx_buffer.tail) & (ring_buffer_pos_t)(RX_BUFFER_SIZE - 1);
|
// Calculate count of bytes stored into the RX buffer
|
||||||
|
|
||||||
// Keep track of the maximum count of enqueued bytes
|
// Keep track of the maximum count of enqueued bytes
|
||||||
NOLESS(rx_max_enqueued, rx_count);
|
NOLESS(rx_max_enqueued, rx_count);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if ENABLED(SERIAL_XON_XOFF)
|
#if ENABLED(SERIAL_XON_XOFF)
|
||||||
|
// If the last char that was sent was an XON
|
||||||
// for high speed transfers, we can use XON/XOFF protocol to do
|
|
||||||
// software handshake and avoid overruns.
|
|
||||||
if ((xon_xoff_state & XON_XOFF_CHAR_MASK) == XON_CHAR) {
|
if ((xon_xoff_state & XON_XOFF_CHAR_MASK) == XON_CHAR) {
|
||||||
|
|
||||||
// calculate count of bytes stored into the RX buffer
|
// Bytes stored into the RX buffer
|
||||||
ring_buffer_pos_t rx_count = (ring_buffer_pos_t)(rx_buffer.head - rx_buffer.tail) & (ring_buffer_pos_t)(RX_BUFFER_SIZE - 1);
|
const ring_buffer_pos_t rx_count = (ring_buffer_pos_t)(h - t) & (ring_buffer_pos_t)(RX_BUFFER_SIZE - 1);
|
||||||
|
|
||||||
// if we are above 12.5% of RX buffer capacity, send XOFF before
|
// If over 12.5% of RX buffer capacity, send XOFF before running out of
|
||||||
// we run out of RX buffer space .. We need 325 bytes @ 250kbits/s to
|
// RX buffer space .. 325 bytes @ 250kbits/s needed to let the host react
|
||||||
// let the host react and stop sending bytes. This translates to 13mS
|
// and stop sending bytes. This translates to 13mS propagation time.
|
||||||
// propagation time.
|
|
||||||
if (rx_count >= (RX_BUFFER_SIZE) / 8) {
|
if (rx_count >= (RX_BUFFER_SIZE) / 8) {
|
||||||
|
|
||||||
// If TX interrupts are disabled and data register is empty,
|
// At this point, definitely no TX interrupt was executing, since the TX isr can't be preempted.
|
||||||
// just write the byte to the data register and be done. This
|
// Don't enable the TX interrupt here as a means to trigger the XOFF char, because if it happens
|
||||||
// shortcut helps significantly improve the effective datarate
|
// to be in the middle of trying to disable the RX interrupt in the main program, eventually the
|
||||||
// at high (>500kbit/s) bitrates, where interrupt overhead
|
// enabling of the TX interrupt could be undone. The ONLY reliable thing this can do to ensure
|
||||||
// becomes a slowdown.
|
// the sending of the XOFF char is to send it HERE AND NOW.
|
||||||
if (!(HWUART->UART_IMR & UART_IMR_TXRDY) && (HWUART->UART_SR & UART_SR_TXRDY)) {
|
|
||||||
|
|
||||||
// Send an XOFF character
|
// About to send the XOFF char
|
||||||
HWUART->UART_THR = XOFF_CHAR;
|
|
||||||
|
|
||||||
// And remember it was sent
|
|
||||||
xon_xoff_state = XOFF_CHAR | XON_XOFF_CHAR_SENT;
|
xon_xoff_state = XOFF_CHAR | XON_XOFF_CHAR_SENT;
|
||||||
}
|
|
||||||
else {
|
|
||||||
// TX interrupts disabled, but buffer still not empty ... or
|
|
||||||
// TX interrupts enabled. Reenable TX ints and schedule XOFF
|
|
||||||
// character to be sent
|
|
||||||
#if TX_BUFFER_SIZE > 0
|
|
||||||
HWUART->UART_IER = UART_IER_TXRDY;
|
|
||||||
xon_xoff_state = XOFF_CHAR;
|
|
||||||
#else
|
|
||||||
// We are not using TX interrupts, we will have to send this manually
|
|
||||||
while (!(HWUART->UART_SR & UART_SR_TXRDY)) sw_barrier();
|
|
||||||
HWUART->UART_THR = XOFF_CHAR;
|
|
||||||
|
|
||||||
// And remember we already sent it
|
// Wait until the TX register becomes empty and send it - Here there could be a problem
|
||||||
xon_xoff_state = XOFF_CHAR | XON_XOFF_CHAR_SENT;
|
// - While waiting for the TX register to empty, the RX register could receive a new
|
||||||
#endif
|
// character. This must also handle that situation!
|
||||||
}
|
uint32_t status;
|
||||||
}
|
while (!((status = HWUART->UART_SR) & UART_SR_TXRDY)) {
|
||||||
}
|
|
||||||
#endif // SERIAL_XON_XOFF
|
if (status & UART_SR_RXRDY) {
|
||||||
|
// We received a char while waiting for the TX buffer to be empty - Receive and process it!
|
||||||
|
|
||||||
|
i = (ring_buffer_pos_t)(h + 1) & (ring_buffer_pos_t)(RX_BUFFER_SIZE - 1);
|
||||||
|
|
||||||
|
// Read the character from the USART
|
||||||
|
c = HWUART->UART_RHR;
|
||||||
|
|
||||||
#if ENABLED(EMERGENCY_PARSER)
|
#if ENABLED(EMERGENCY_PARSER)
|
||||||
emergency_parser.update(emergency_state, c);
|
emergency_parser.update(emergency_state, c);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
// If the character is to be stored at the index just before the tail
|
||||||
|
// (such that the head would advance to the current tail), the FIFO is
|
||||||
|
// full, so don't write the character or advance the head.
|
||||||
|
if (i != t) {
|
||||||
|
rx_buffer.buffer[h] = c;
|
||||||
|
h = i;
|
||||||
|
}
|
||||||
|
#if ENABLED(SERIAL_STATS_DROPPED_RX)
|
||||||
|
else if (!++rx_dropped_bytes) --rx_dropped_bytes;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
sw_barrier();
|
||||||
|
}
|
||||||
|
|
||||||
|
HWUART->UART_THR = XOFF_CHAR;
|
||||||
|
|
||||||
|
// At this point there could be a race condition between the write() function
|
||||||
|
// and this sending of the XOFF char. This interrupt could happen between the
|
||||||
|
// wait to be empty TX buffer loop and the actual write of the character. Since
|
||||||
|
// the TX buffer is full because it's sending the XOFF char, the only way to be
|
||||||
|
// sure the write() function will succeed is to wait for the XOFF char to be
|
||||||
|
// completely sent. Since an extra character could be received during the wait
|
||||||
|
// it must also be handled!
|
||||||
|
while (!((status = HWUART->UART_SR) & UART_SR_TXRDY)) {
|
||||||
|
|
||||||
|
if (status & UART_SR_RXRDY) {
|
||||||
|
// A char arrived while waiting for the TX buffer to be empty - Receive and process it!
|
||||||
|
|
||||||
|
i = (ring_buffer_pos_t)(h + 1) & (ring_buffer_pos_t)(RX_BUFFER_SIZE - 1);
|
||||||
|
|
||||||
|
// Read the character from the USART
|
||||||
|
c = HWUART->UART_RHR;
|
||||||
|
|
||||||
|
#if ENABLED(EMERGENCY_PARSER)
|
||||||
|
emergency_parser.update(emergency_state, c);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// If the character is to be stored at the index just before the tail
|
||||||
|
// (such that the head would advance to the current tail), the FIFO is
|
||||||
|
// full, so don't write the character or advance the head.
|
||||||
|
if (i != t) {
|
||||||
|
rx_buffer.buffer[h] = c;
|
||||||
|
h = i;
|
||||||
|
}
|
||||||
|
#if ENABLED(SERIAL_STATS_DROPPED_RX)
|
||||||
|
else if (!++rx_dropped_bytes) --rx_dropped_bytes;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
sw_barrier();
|
||||||
|
}
|
||||||
|
|
||||||
|
// At this point everything is ready. The write() function won't
|
||||||
|
// have any issues writing to the UART TX register if it needs to!
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif // SERIAL_XON_XOFF
|
||||||
|
|
||||||
|
// Store the new head value
|
||||||
|
rx_buffer.head = h;
|
||||||
}
|
}
|
||||||
|
|
||||||
#if TX_BUFFER_SIZE > 0
|
#if TX_BUFFER_SIZE > 0
|
||||||
|
|
||||||
FORCE_INLINE void _tx_thr_empty_irq(void) {
|
FORCE_INLINE void _tx_thr_empty_irq(void) {
|
||||||
// If interrupts are enabled, there must be more data in the output
|
// Read positions
|
||||||
// buffer.
|
uint8_t t = tx_buffer.tail;
|
||||||
|
const uint8_t h = tx_buffer.head;
|
||||||
|
|
||||||
#if ENABLED(SERIAL_XON_XOFF)
|
#if ENABLED(SERIAL_XON_XOFF)
|
||||||
// Do a priority insertion of an XON/XOFF char, if needed.
|
// If an XON char is pending to be sent, do it now
|
||||||
const uint8_t state = xon_xoff_state;
|
if (xon_xoff_state == XON_CHAR) {
|
||||||
if (!(state & XON_XOFF_CHAR_SENT)) {
|
|
||||||
HWUART->UART_THR = state & XON_XOFF_CHAR_MASK;
|
// Send the character
|
||||||
xon_xoff_state = state | XON_XOFF_CHAR_SENT;
|
HWUART->UART_THR = XON_CHAR;
|
||||||
|
|
||||||
|
// Remember we sent it.
|
||||||
|
xon_xoff_state = XON_CHAR | XON_XOFF_CHAR_SENT;
|
||||||
|
|
||||||
|
// If nothing else to transmit, just disable TX interrupts.
|
||||||
|
if (h == t) HWUART->UART_IDR = UART_IDR_TXRDY;
|
||||||
|
|
||||||
|
return;
|
||||||
}
|
}
|
||||||
else
|
|
||||||
#endif
|
#endif
|
||||||
{ // Send the next byte
|
|
||||||
const uint8_t t = tx_buffer.tail, c = tx_buffer.buffer[t];
|
// If nothing to transmit, just disable TX interrupts. This could
|
||||||
tx_buffer.tail = (t + 1) & (TX_BUFFER_SIZE - 1);
|
// happen as the result of the non atomicity of the disabling of RX
|
||||||
HWUART->UART_THR = c;
|
// interrupts that could end reenabling TX interrupts as a side effect.
|
||||||
|
if (h == t) {
|
||||||
|
HWUART->UART_IDR = UART_IDR_TXRDY;
|
||||||
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
// Disable interrupts if the buffer is empty
|
// There is something to TX, Send the next byte
|
||||||
if (tx_buffer.head == tx_buffer.tail)
|
const uint8_t c = tx_buffer.buffer[t];
|
||||||
HWUART->UART_IDR = UART_IDR_TXRDY;
|
t = (t + 1) & (TX_BUFFER_SIZE - 1);
|
||||||
|
HWUART->UART_THR = c;
|
||||||
|
tx_buffer.tail = t;
|
||||||
|
|
||||||
|
// Disable interrupts if there is nothing to transmit following this byte
|
||||||
|
if (h == t) HWUART->UART_IDR = UART_IDR_TXRDY;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif // TX_BUFFER_SIZE > 0
|
#endif // TX_BUFFER_SIZE > 0
|
||||||
|
|
||||||
static void UART_ISR(void) {
|
static void UART_ISR(void) {
|
||||||
uint32_t status = HWUART->UART_SR;
|
const uint32_t status = HWUART->UART_SR;
|
||||||
|
|
||||||
// Did we receive data?
|
// Data received?
|
||||||
if (status & UART_SR_RXRDY)
|
if (status & UART_SR_RXRDY) store_rxd_char();
|
||||||
store_rxd_char();
|
|
||||||
|
|
||||||
#if TX_BUFFER_SIZE > 0
|
#if TX_BUFFER_SIZE > 0
|
||||||
// Do we have something to send, and TX interrupts are enabled (meaning something to send) ?
|
// Something to send, and TX interrupts are enabled (meaning something to send)?
|
||||||
if ((status & UART_SR_TXRDY) && (HWUART->UART_IMR & UART_IMR_TXRDY))
|
if ((status & UART_SR_TXRDY) && (HWUART->UART_IMR & UART_IMR_TXRDY)) _tx_thr_empty_irq();
|
||||||
_tx_thr_empty_irq();
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
// Acknowledge errors
|
// Acknowledge errors
|
||||||
if ((status & UART_SR_OVRE) || (status & UART_SR_FRAME)) {
|
if ((status & UART_SR_OVRE) || (status & UART_SR_FRAME)) {
|
||||||
|
|
||||||
|
#if ENABLED(SERIAL_STATS_DROPPED_RX)
|
||||||
|
if (status & UART_SR_OVRE && !++rx_dropped_bytes) --rx_dropped_bytes;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if ENABLED(SERIAL_STATS_RX_BUFFER_OVERRUNS)
|
||||||
|
if (status & UART_SR_OVRE && !++rx_buffer_overruns) --rx_buffer_overruns;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if ENABLED(SERIAL_STATS_RX_FRAMING_ERRORS)
|
||||||
|
if (status & UART_SR_FRAME && !++rx_framing_errors) --rx_framing_errors;
|
||||||
|
#endif
|
||||||
|
|
||||||
// TODO: error reporting outside ISR
|
// TODO: error reporting outside ISR
|
||||||
HWUART->UART_CR = UART_CR_RSTSTA;
|
HWUART->UART_CR = UART_CR_RSTSTA;
|
||||||
}
|
}
|
||||||
@ -312,36 +405,40 @@
|
|||||||
}
|
}
|
||||||
|
|
||||||
int MarlinSerial::read(void) {
|
int MarlinSerial::read(void) {
|
||||||
int v;
|
|
||||||
|
|
||||||
const ring_buffer_pos_t h = rx_buffer.head;
|
const ring_buffer_pos_t h = rx_buffer.head;
|
||||||
ring_buffer_pos_t t = rx_buffer.tail;
|
ring_buffer_pos_t t = rx_buffer.tail;
|
||||||
|
|
||||||
if (h == t)
|
if (h == t) return -1;
|
||||||
v = -1;
|
|
||||||
else {
|
int v = rx_buffer.buffer[t];
|
||||||
v = rx_buffer.buffer[t];
|
|
||||||
t = (ring_buffer_pos_t)(t + 1) & (RX_BUFFER_SIZE - 1);
|
t = (ring_buffer_pos_t)(t + 1) & (RX_BUFFER_SIZE - 1);
|
||||||
|
|
||||||
// Advance tail
|
// Advance tail
|
||||||
rx_buffer.tail = t;
|
rx_buffer.tail = t;
|
||||||
|
|
||||||
#if ENABLED(SERIAL_XON_XOFF)
|
#if ENABLED(SERIAL_XON_XOFF)
|
||||||
|
// If the XOFF char was sent, or about to be sent...
|
||||||
if ((xon_xoff_state & XON_XOFF_CHAR_MASK) == XOFF_CHAR) {
|
if ((xon_xoff_state & XON_XOFF_CHAR_MASK) == XOFF_CHAR) {
|
||||||
|
|
||||||
// Get count of bytes in the RX buffer
|
// Get count of bytes in the RX buffer
|
||||||
ring_buffer_pos_t rx_count = (ring_buffer_pos_t)(h - t) & (ring_buffer_pos_t)(RX_BUFFER_SIZE - 1);
|
const ring_buffer_pos_t rx_count = (ring_buffer_pos_t)(h - t) & (ring_buffer_pos_t)(RX_BUFFER_SIZE - 1);
|
||||||
|
// When below 10% of RX buffer capacity, send XON before running out of RX buffer bytes
|
||||||
// When below 10% of RX buffer capacity, send XON before
|
|
||||||
// running out of RX buffer bytes
|
|
||||||
if (rx_count < (RX_BUFFER_SIZE) / 10) {
|
if (rx_count < (RX_BUFFER_SIZE) / 10) {
|
||||||
|
#if TX_BUFFER_SIZE > 0
|
||||||
|
// Signal we want an XON character to be sent.
|
||||||
|
xon_xoff_state = XON_CHAR;
|
||||||
|
// Enable TX isr.
|
||||||
|
HWUART->UART_IER = UART_IER_TXRDY;
|
||||||
|
#else
|
||||||
|
// If not using TX interrupts, we must send the XON char now
|
||||||
xon_xoff_state = XON_CHAR | XON_XOFF_CHAR_SENT;
|
xon_xoff_state = XON_CHAR | XON_XOFF_CHAR_SENT;
|
||||||
write(XON_CHAR);
|
while (!(HWUART->UART_SR & UART_SR_TXRDY)) sw_barrier();
|
||||||
return v;
|
HWUART->UART_THR = XON_CHAR;
|
||||||
|
#endif
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
}
|
|
||||||
return v;
|
return v;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -355,8 +452,17 @@
|
|||||||
|
|
||||||
#if ENABLED(SERIAL_XON_XOFF)
|
#if ENABLED(SERIAL_XON_XOFF)
|
||||||
if ((xon_xoff_state & XON_XOFF_CHAR_MASK) == XOFF_CHAR) {
|
if ((xon_xoff_state & XON_XOFF_CHAR_MASK) == XOFF_CHAR) {
|
||||||
|
#if TX_BUFFER_SIZE > 0
|
||||||
|
// Signal we want an XON character to be sent.
|
||||||
|
xon_xoff_state = XON_CHAR;
|
||||||
|
// Enable TX isr.
|
||||||
|
HWUART->UART_IER = UART_IER_TXRDY;
|
||||||
|
#else
|
||||||
|
// If not using TX interrupts, we must send the XON char now
|
||||||
xon_xoff_state = XON_CHAR | XON_XOFF_CHAR_SENT;
|
xon_xoff_state = XON_CHAR | XON_XOFF_CHAR_SENT;
|
||||||
write(XON_CHAR);
|
while (!(HWUART->UART_SR & UART_SR_TXRDY)) sw_barrier();
|
||||||
|
HWUART->UART_THR = XON_CHAR;
|
||||||
|
#endif
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
@ -370,6 +476,8 @@
|
|||||||
// be done. This shortcut helps significantly improve the
|
// be done. This shortcut helps significantly improve the
|
||||||
// effective datarate at high (>500kbit/s) bitrates, where
|
// effective datarate at high (>500kbit/s) bitrates, where
|
||||||
// interrupt overhead becomes a slowdown.
|
// interrupt overhead becomes a slowdown.
|
||||||
|
// Yes, there is a race condition between the sending of the
|
||||||
|
// XOFF char at the RX isr, but it is properly handled there
|
||||||
if (!(HWUART->UART_IMR & UART_IMR_TXRDY) && (HWUART->UART_SR & UART_SR_TXRDY)) {
|
if (!(HWUART->UART_IMR & UART_IMR_TXRDY) && (HWUART->UART_SR & UART_SR_TXRDY)) {
|
||||||
HWUART->UART_THR = c;
|
HWUART->UART_THR = c;
|
||||||
return;
|
return;
|
||||||
@ -377,54 +485,79 @@
|
|||||||
|
|
||||||
const uint8_t i = (tx_buffer.head + 1) & (TX_BUFFER_SIZE - 1);
|
const uint8_t i = (tx_buffer.head + 1) & (TX_BUFFER_SIZE - 1);
|
||||||
|
|
||||||
// If the output buffer is full, there's nothing for it other than to
|
// If global interrupts are disabled (as the result of being called from an ISR)...
|
||||||
// wait for the interrupt handler to empty it a bit
|
|
||||||
while (i == tx_buffer.tail) {
|
|
||||||
if (!ISRS_ENABLED()) {
|
if (!ISRS_ENABLED()) {
|
||||||
// Interrupts are disabled, so we'll have to poll the data
|
|
||||||
// register empty flag ourselves. If it is set, pretend an
|
|
||||||
// interrupt has happened and call the handler to free up
|
|
||||||
// space for us.
|
|
||||||
if (HWUART->UART_SR & UART_SR_TXRDY)
|
|
||||||
_tx_thr_empty_irq();
|
|
||||||
}
|
|
||||||
// (else , the interrupt handler will free up space for us)
|
|
||||||
|
|
||||||
|
// Make room by polling if it is possible to transmit, and do so!
|
||||||
|
while (i == tx_buffer.tail) {
|
||||||
|
// If we can transmit another byte, do it.
|
||||||
|
if (HWUART->UART_SR & UART_SR_TXRDY) _tx_thr_empty_irq();
|
||||||
// Make sure compiler rereads tx_buffer.tail
|
// Make sure compiler rereads tx_buffer.tail
|
||||||
sw_barrier();
|
sw_barrier();
|
||||||
}
|
}
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
// Interrupts are enabled, just wait until there is space
|
||||||
|
while (i == tx_buffer.tail) sw_barrier();
|
||||||
|
}
|
||||||
|
|
||||||
|
// Store new char. head is always safe to move
|
||||||
tx_buffer.buffer[tx_buffer.head] = c;
|
tx_buffer.buffer[tx_buffer.head] = c;
|
||||||
tx_buffer.head = i;
|
tx_buffer.head = i;
|
||||||
|
|
||||||
// Enable TX isr
|
// Enable TX isr - Non atomic, but it will eventually enable TX isr
|
||||||
HWUART->UART_IER = UART_IER_TXRDY;
|
HWUART->UART_IER = UART_IER_TXRDY;
|
||||||
return;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void MarlinSerial::flushTX(void) {
|
void MarlinSerial::flushTX(void) {
|
||||||
// TX
|
// TX
|
||||||
// If we have never written a byte, no need to flush.
|
|
||||||
|
// If we have never written a byte, no need to flush. This special
|
||||||
|
// case is needed since there is no way to force the TXC (transmit
|
||||||
|
// complete) bit to 1 during initialization
|
||||||
if (!_written) return;
|
if (!_written) return;
|
||||||
|
|
||||||
while ((HWUART->UART_IMR & UART_IMR_TXRDY) || !(HWUART->UART_SR & UART_SR_TXEMPTY)) {
|
// If global interrupts are disabled (as the result of being called from an ISR)...
|
||||||
if (!ISRS_ENABLED()) {
|
if (!ISRS_ENABLED()) {
|
||||||
if (HWUART->UART_SR & UART_SR_TXRDY)
|
|
||||||
_tx_thr_empty_irq();
|
// Wait until everything was transmitted - We must do polling, as interrupts are disabled
|
||||||
}
|
while (tx_buffer.head != tx_buffer.tail || !(HWUART->UART_SR & UART_SR_TXEMPTY)) {
|
||||||
|
// If there is more space, send an extra character
|
||||||
|
if (HWUART->UART_SR & UART_SR_TXRDY) _tx_thr_empty_irq();
|
||||||
sw_barrier();
|
sw_barrier();
|
||||||
}
|
}
|
||||||
// If we get here, nothing is queued anymore (TX interrupts are disabled) and
|
|
||||||
// the hardware finished tranmission (TXEMPTY is set).
|
}
|
||||||
|
else {
|
||||||
|
// Wait until everything was transmitted
|
||||||
|
while (tx_buffer.head != tx_buffer.tail || !(HWUART->UART_SR & UART_SR_TXEMPTY)) sw_barrier();
|
||||||
|
}
|
||||||
|
|
||||||
|
// At this point nothing is queued anymore (DRIE is disabled) and
|
||||||
|
// the hardware finished transmission (TXC is set).
|
||||||
}
|
}
|
||||||
|
|
||||||
#else // TX_BUFFER_SIZE == 0
|
#else // TX_BUFFER_SIZE == 0
|
||||||
|
|
||||||
void MarlinSerial::write(const uint8_t c) {
|
void MarlinSerial::write(const uint8_t c) {
|
||||||
|
_written = true;
|
||||||
while (!(HWUART->UART_SR & UART_SR_TXRDY)) sw_barrier();
|
while (!(HWUART->UART_SR & UART_SR_TXRDY)) sw_barrier();
|
||||||
HWUART->UART_THR = c;
|
HWUART->UART_THR = c;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void MarlinSerial::flushTX(void) {
|
||||||
|
// TX
|
||||||
|
|
||||||
|
// No bytes written, no need to flush. This special case is needed since there's
|
||||||
|
// no way to force the TXC (transmit complete) bit to 1 during initialization.
|
||||||
|
if (!_written) return;
|
||||||
|
|
||||||
|
// Wait until everything was transmitted
|
||||||
|
while (!(HWUART->UART_SR & UART_SR_TXEMPTY)) sw_barrier();
|
||||||
|
|
||||||
|
// At this point nothing is queued anymore (DRIE is disabled) and
|
||||||
|
// the hardware finished transmission (TXC is set).
|
||||||
|
}
|
||||||
#endif // TX_BUFFER_SIZE == 0
|
#endif // TX_BUFFER_SIZE == 0
|
||||||
|
|
||||||
/**
|
/**
|
||||||
@ -448,13 +581,9 @@
|
|||||||
}
|
}
|
||||||
|
|
||||||
void MarlinSerial::print(long n, int base) {
|
void MarlinSerial::print(long n, int base) {
|
||||||
if (base == 0)
|
if (base == 0) write(n);
|
||||||
write(n);
|
|
||||||
else if (base == 10) {
|
else if (base == 10) {
|
||||||
if (n < 0) {
|
if (n < 0) { print('-'); n = -n; }
|
||||||
print('-');
|
|
||||||
n = -n;
|
|
||||||
}
|
|
||||||
printNumber(n, 10);
|
printNumber(n, 10);
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
@ -546,9 +675,7 @@
|
|||||||
|
|
||||||
// Round correctly so that print(1.999, 2) prints as "2.00"
|
// Round correctly so that print(1.999, 2) prints as "2.00"
|
||||||
double rounding = 0.5;
|
double rounding = 0.5;
|
||||||
for (uint8_t i = 0; i < digits; ++i)
|
for (uint8_t i = 0; i < digits; ++i) rounding *= 0.1;
|
||||||
rounding *= 0.1;
|
|
||||||
|
|
||||||
number += rounding;
|
number += rounding;
|
||||||
|
|
||||||
// Extract the integer part of the number and print it
|
// Extract the integer part of the number and print it
|
||||||
|
@ -70,6 +70,14 @@
|
|||||||
extern uint8_t rx_dropped_bytes;
|
extern uint8_t rx_dropped_bytes;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if ENABLED(SERIAL_STATS_RX_BUFFER_OVERRUNS)
|
||||||
|
extern uint8_t rx_buffer_overruns;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if ENABLED(SERIAL_STATS_RX_FRAMING_ERRORS)
|
||||||
|
extern uint8_t rx_framing_errors;
|
||||||
|
#endif
|
||||||
|
|
||||||
#if ENABLED(SERIAL_STATS_MAX_RX_QUEUED)
|
#if ENABLED(SERIAL_STATS_MAX_RX_QUEUED)
|
||||||
extern ring_buffer_pos_t rx_max_enqueued;
|
extern ring_buffer_pos_t rx_max_enqueued;
|
||||||
#endif
|
#endif
|
||||||
@ -85,14 +93,20 @@ public:
|
|||||||
static void flush(void);
|
static void flush(void);
|
||||||
static ring_buffer_pos_t available(void);
|
static ring_buffer_pos_t available(void);
|
||||||
static void write(const uint8_t c);
|
static void write(const uint8_t c);
|
||||||
#if TX_BUFFER_SIZE > 0
|
|
||||||
static void flushTX(void);
|
static void flushTX(void);
|
||||||
#endif
|
|
||||||
|
|
||||||
#if ENABLED(SERIAL_STATS_DROPPED_RX)
|
#if ENABLED(SERIAL_STATS_DROPPED_RX)
|
||||||
FORCE_INLINE static uint32_t dropped() { return rx_dropped_bytes; }
|
FORCE_INLINE static uint32_t dropped() { return rx_dropped_bytes; }
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if ENABLED(SERIAL_STATS_RX_BUFFER_OVERRUNS)
|
||||||
|
FORCE_INLINE static uint32_t buffer_overruns() { return rx_buffer_overruns; }
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if ENABLED(SERIAL_STATS_RX_FRAMING_ERRORS)
|
||||||
|
FORCE_INLINE static uint32_t framing_errors() { return rx_framing_errors; }
|
||||||
|
#endif
|
||||||
|
|
||||||
#if ENABLED(SERIAL_STATS_MAX_RX_QUEUED)
|
#if ENABLED(SERIAL_STATS_MAX_RX_QUEUED)
|
||||||
FORCE_INLINE static ring_buffer_pos_t rxMaxEnqueued() { return rx_max_enqueued; }
|
FORCE_INLINE static ring_buffer_pos_t rxMaxEnqueued() { return rx_max_enqueued; }
|
||||||
#endif
|
#endif
|
||||||
|
@ -58,6 +58,23 @@ void GcodeSuite::M111() {
|
|||||||
}
|
}
|
||||||
else {
|
else {
|
||||||
SERIAL_ECHOPGM(MSG_DEBUG_OFF);
|
SERIAL_ECHOPGM(MSG_DEBUG_OFF);
|
||||||
|
#if !defined(__AVR__) || !defined(USBCON)
|
||||||
|
#if ENABLED(SERIAL_STATS_RX_BUFFER_OVERRUNS)
|
||||||
|
SERIAL_ECHOLNPAIR("Buffer Overruns: ", customizedSerial.buffer_overruns());
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if ENABLED(SERIAL_STATS_RX_FRAMING_ERRORS)
|
||||||
|
SERIAL_ECHOLNPAIR("Framing Errors: ", customizedSerial.framing_errors());
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if ENABLED(SERIAL_STATS_DROPPED_RX)
|
||||||
|
SERIAL_ECHOLNPAIR("Dropped bytes: ", customizedSerial.dropped());
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if ENABLED(SERIAL_STATS_MAX_RX_QUEUED)
|
||||||
|
SERIAL_ECHOLNPAIR("Max RX Queue Size: ", customizedSerial.rxMaxEnqueued());
|
||||||
|
#endif
|
||||||
|
#endif // !defined(__AVR__) || !defined(USBCON)
|
||||||
}
|
}
|
||||||
SERIAL_EOL();
|
SERIAL_EOL();
|
||||||
}
|
}
|
||||||
|
Loading…
Reference in New Issue
Block a user