Enable RRDFGSC on Due
This commit is contained in:
Bob-the-Kuhn
committed by
Scott Lahteine
Scott Lahteine
parent
b259bb4670
commit
a142fab155
212
Marlin/src/HAL/HAL_DUE/u8g_com_HAL_DUE_st7920_sw_spi.cpp
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212
Marlin/src/HAL/HAL_DUE/u8g_com_HAL_DUE_st7920_sw_spi.cpp
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/**
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* Marlin 3D Printer Firmware
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* Copyright (C) 2016, 2017 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
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*
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* Based on Sprinter and grbl.
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* Copyright (C) 2011 Camiel Gubbels / Erik van der Zalm
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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/*
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based on u8g_com_st7920_hw_spi.c
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Universal 8bit Graphics Library
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Copyright (c) 2011, olikraus@gmail.com
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice, this list
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of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright notice, this
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list of conditions and the following disclaimer in the documentation and/or other
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materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
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CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifdef __SAM3X8E__
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#include <U8glib.h>
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#include <Arduino.h>
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#include "../../core/macros.h"
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void u8g_SetPIOutput_DUE(u8g_t *u8g, uint8_t pin_index) {
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PIO_Configure(g_APinDescription[u8g->pin_list[pin_index]].pPort, PIO_OUTPUT_1,
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g_APinDescription[u8g->pin_list[pin_index]].ulPin, g_APinDescription[u8g->pin_list[pin_index]].ulPinConfiguration); // OUTPUT
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}
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void u8g_SetPILevel_DUE(u8g_t *u8g, uint8_t pin_index, uint8_t level) {
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volatile Pio* port = g_APinDescription[u8g->pin_list[pin_index]].pPort;
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uint32_t mask = g_APinDescription[u8g->pin_list[pin_index]].ulPin;
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if (level) port->PIO_SODR = mask;
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else port->PIO_CODR = mask;
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}
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#define nop() __asm__ __volatile__("nop;\n\t":::)
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void __delay_4cycles(uint32_t cy) __attribute__ ((weak));
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FORCE_INLINE void __delay_4cycles(uint32_t cy) { // +1 cycle
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#if ARCH_PIPELINE_RELOAD_CYCLES<2
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#define EXTRA_NOP_CYCLES "nop"
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#else
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#define EXTRA_NOP_CYCLES ""
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#endif
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__asm__ __volatile__(
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".syntax unified" "\n\t" // is to prevent CM0,CM1 non-unified syntax
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"loop%=:" "\n\t"
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" subs %[cnt],#1" "\n\t"
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EXTRA_NOP_CYCLES "\n\t"
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" bne loop%=" "\n\t"
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: [cnt]"+r"(cy) // output: +r means input+output
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: // input:
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: "cc" // clobbers:
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);
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}
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Pio *SCK_pPio, *MOSI_pPio;
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uint32_t SCK_dwMask, MOSI_dwMask;
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static void spiSend_sw_DUE(uint8_t val) // 800KHz
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{
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for (uint8_t i = 0; i < 8; i++) {
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if (val & 0x80)
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MOSI_pPio->PIO_SODR = MOSI_dwMask;
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else
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MOSI_pPio->PIO_CODR = MOSI_dwMask;
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val = val << 1;
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__delay_4cycles(2);
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SCK_pPio->PIO_SODR = SCK_dwMask;
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__delay_4cycles(22);
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SCK_pPio->PIO_CODR = SCK_dwMask;
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}
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}
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static uint8_t rs_last_state = 255;
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static void u8g_com_DUE_st7920_write_byte_sw_spi(uint8_t rs, uint8_t val)
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{
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uint8_t i;
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if ( rs != rs_last_state) { // time to send a command/data byte
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rs_last_state = rs;
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if ( rs == 0 )
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/* command */
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spiSend_sw_DUE(0x0f8);
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else
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/* data */
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spiSend_sw_DUE(0x0fa);
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for( i = 0; i < 4; i++ ) // give the controller some time to process the data
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u8g_10MicroDelay(); // 2 is bad, 3 is OK, 4 is safe
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}
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spiSend_sw_DUE(val & 0x0f0);
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spiSend_sw_DUE(val << 4);
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}
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uint8_t u8g_com_HAL_DUE_ST7920_sw_spi_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr)
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{
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switch(msg)
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{
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case U8G_COM_MSG_INIT:
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SCK_pPio = g_APinDescription[u8g->pin_list[U8G_PI_SCK]].pPort;
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SCK_dwMask = g_APinDescription[u8g->pin_list[U8G_PI_SCK]].ulPin;
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MOSI_pPio = g_APinDescription[u8g->pin_list[U8G_PI_MOSI]].pPort;
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MOSI_dwMask = g_APinDescription[u8g->pin_list[U8G_PI_MOSI]].ulPin;
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u8g_SetPILevel_DUE(u8g, U8G_PI_CS, 0);
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u8g_SetPIOutput_DUE(u8g, U8G_PI_CS);
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u8g_SetPILevel_DUE(u8g, U8G_PI_SCK, 0);
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u8g_SetPIOutput_DUE(u8g, U8G_PI_SCK);
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u8g_SetPILevel_DUE(u8g, U8G_PI_MOSI, 0);
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u8g_SetPILevel_DUE(u8g, U8G_PI_MOSI, 1);
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u8g_SetPIOutput_DUE(u8g, U8G_PI_MOSI);
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u8g_Delay(5);
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u8g->pin_list[U8G_PI_A0_STATE] = 0; /* inital RS state: command mode */
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break;
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case U8G_COM_MSG_STOP:
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break;
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case U8G_COM_MSG_RESET:
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if (U8G_PIN_NONE != u8g->pin_list[U8G_PI_RESET]) u8g_SetPILevel_DUE(u8g, U8G_PI_RESET, arg_val);
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break;
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case U8G_COM_MSG_ADDRESS: /* define cmd (arg_val = 0) or data mode (arg_val = 1) */
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u8g->pin_list[U8G_PI_A0_STATE] = arg_val;
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break;
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case U8G_COM_MSG_CHIP_SELECT:
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if (U8G_PIN_NONE != u8g->pin_list[U8G_PI_CS])
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u8g_SetPILevel_DUE(u8g, U8G_PI_CS, arg_val); //note: the st7920 has an active high chip select
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break;
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case U8G_COM_MSG_WRITE_BYTE:
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u8g_com_DUE_st7920_write_byte_sw_spi(u8g->pin_list[U8G_PI_A0_STATE], arg_val);
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break;
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case U8G_COM_MSG_WRITE_SEQ:
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{
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uint8_t *ptr = (uint8_t*) arg_ptr;
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while( arg_val > 0 )
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{
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u8g_com_DUE_st7920_write_byte_sw_spi(u8g->pin_list[U8G_PI_A0_STATE], *ptr++);
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arg_val--;
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}
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}
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break;
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case U8G_COM_MSG_WRITE_SEQ_P:
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{
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uint8_t *ptr = (uint8_t*) arg_ptr;
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while( arg_val > 0 )
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{
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u8g_com_DUE_st7920_write_byte_sw_spi(u8g->pin_list[U8G_PI_A0_STATE], *ptr++);
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arg_val--;
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}
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}
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break;
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}
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return 1;
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}
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#pragma GCC reset_options
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#endif //ARDUINO_ARCH_SAM
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