Anet ET4 / ET4P and Anet TFT28 / TFT35 (#20280)
This commit is contained in:
@ -48,13 +48,14 @@ void TFT_FSMC::Init() {
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uint32_t NSBank = (uint32_t)pinmap_peripheral(digitalPinToPinName(TFT_CS_PIN), PinMap_FSMC_CS);
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// Perform the SRAM1 memory initialization sequence
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SRAMx.Instance = FSMC_NORSRAM_DEVICE;
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SRAMx.Extended = FSMC_NORSRAM_EXTENDED_DEVICE;
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/* SRAMx.Init */
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// SRAMx.Init
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SRAMx.Init.NSBank = NSBank;
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SRAMx.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE;
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SRAMx.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM;
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SRAMx.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_16;
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SRAMx.Init.MemoryDataWidth = TERN(TFT_INTERFACE_FSMC_8BIT, FSMC_NORSRAM_MEM_BUS_WIDTH_8, FSMC_NORSRAM_MEM_BUS_WIDTH_16);
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SRAMx.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE;
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SRAMx.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW;
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SRAMx.Init.WrapMode = FSMC_WRAP_MODE_DISABLE;
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@ -67,8 +68,8 @@ void TFT_FSMC::Init() {
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#ifdef STM32F4xx
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SRAMx.Init.PageSize = FSMC_PAGE_SIZE_NONE;
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#endif
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/* Read Timing - relatively slow to ensure ID information is correctly read from TFT controller */
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/* Can be decreases from 15-15-24 to 4-4-8 with risk of stability loss */
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// Read Timing - relatively slow to ensure ID information is correctly read from TFT controller
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// Can be decreases from 15-15-24 to 4-4-8 with risk of stability loss
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Timing.AddressSetupTime = 15;
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Timing.AddressHoldTime = 15;
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Timing.DataSetupTime = 24;
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@ -76,8 +77,8 @@ void TFT_FSMC::Init() {
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Timing.CLKDivision = 16;
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Timing.DataLatency = 17;
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Timing.AccessMode = FSMC_ACCESS_MODE_A;
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/* Write Timing */
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/* Can be decreases from 8-15-8 to 0-0-1 with risk of stability loss */
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// Write Timing
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// Can be decreases from 8-15-8 to 0-0-1 with risk of stability loss
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ExtTiming.AddressSetupTime = 8;
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ExtTiming.AddressHoldTime = 15;
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ExtTiming.DataSetupTime = 8;
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@ -131,7 +132,7 @@ void TFT_FSMC::Init() {
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uint32_t TFT_FSMC::GetID() {
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uint32_t id;
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WriteReg(0x0000);
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WriteReg(0);
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id = LCD->RAM;
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if (id == 0)
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@ -141,16 +142,16 @@ uint32_t TFT_FSMC::GetID() {
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return id;
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}
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uint32_t TFT_FSMC::ReadID(uint16_t Reg) {
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uint32_t id;
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WriteReg(Reg);
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id = LCD->RAM; // dummy read
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id = Reg << 24;
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id |= (LCD->RAM & 0x00FF) << 16;
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id |= (LCD->RAM & 0x00FF) << 8;
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id |= LCD->RAM & 0x00FF;
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return id;
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}
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uint32_t TFT_FSMC::ReadID(tft_data_t Reg) {
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uint32_t id;
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WriteReg(Reg);
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id = LCD->RAM; // dummy read
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id = Reg << 24;
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id |= (LCD->RAM & 0x00FF) << 16;
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id |= (LCD->RAM & 0x00FF) << 8;
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id |= LCD->RAM & 0x00FF;
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return id;
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}
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bool TFT_FSMC::isBusy() {
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if (__IS_DMA_ENABLED(&DMAtx))
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@ -44,9 +44,12 @@
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#define DATASIZE_16BIT SPI_DATASIZE_16BIT
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#define TFT_IO_DRIVER TFT_FSMC
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#define TFT_DATASIZE TERN(TFT_INTERFACE_FSMC_8BIT, DATASIZE_8BIT, DATASIZE_16BIT)
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typedef TERN(TFT_INTERFACE_FSMC_8BIT, uint8_t, uint16_t) tft_data_t;
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typedef struct {
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__IO uint16_t REG;
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__IO uint16_t RAM;
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__IO tft_data_t REG;
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__IO tft_data_t RAM;
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} LCD_CONTROLLER_TypeDef;
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class TFT_FSMC {
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@ -56,8 +59,8 @@ class TFT_FSMC {
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static LCD_CONTROLLER_TypeDef *LCD;
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static uint32_t ReadID(uint16_t Reg);
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static void Transmit(uint16_t Data) { LCD->RAM = Data; __DSB(); }
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static uint32_t ReadID(tft_data_t Reg);
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static void Transmit(tft_data_t Data) { LCD->RAM = Data; __DSB(); }
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static void TransmitDMA(uint32_t MemoryIncrease, uint16_t *Data, uint16_t Count);
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public:
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@ -66,11 +69,11 @@ class TFT_FSMC {
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static bool isBusy();
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static void Abort() { __HAL_DMA_DISABLE(&DMAtx); }
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static void DataTransferBegin(uint16_t DataWidth = DATASIZE_16BIT) {}
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static void DataTransferBegin(uint16_t DataWidth = TFT_DATASIZE) {}
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static void DataTransferEnd() {};
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static void WriteData(uint16_t Data) { Transmit(Data); }
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static void WriteReg(uint16_t Reg) { LCD->REG = Reg; __DSB(); }
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static void WriteData(uint16_t Data) { Transmit(tft_data_t(Data)); }
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static void WriteReg(uint16_t Reg) { LCD->REG = tft_data_t(Reg); __DSB(); }
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static void WriteSequence(uint16_t *Data, uint16_t Count) { TransmitDMA(DMA_PINC_ENABLE, Data, Count); }
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static void WriteMultiple(uint16_t Color, uint16_t Count) { static uint16_t Data; Data = Color; TransmitDMA(DMA_PINC_DISABLE, &Data, Count); }
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@ -98,14 +101,16 @@ const PinMap PinMap_FSMC[] = {
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{PE_8, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D05
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{PE_9, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D06
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{PE_10, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D07
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{PE_11, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D08
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{PE_12, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D09
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{PE_13, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D10
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{PE_14, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D11
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{PE_15, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D12
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{PD_8, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D13
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{PD_9, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D14
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{PD_10, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D15
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#if DISABLED(TFT_INTERFACE_FSMC_8BIT)
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{PE_11, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D08
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{PE_12, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D09
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{PE_13, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D10
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{PE_14, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D11
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{PE_15, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D12
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{PD_8, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D13
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{PD_9, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D14
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{PD_10, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D15
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#endif
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{PD_4, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_NOE
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{PD_5, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_NWE
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{NC, NP, 0}
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@ -121,7 +126,11 @@ const PinMap PinMap_FSMC_CS[] = {
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{NC, NP, 0}
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};
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#define FSMC_RS(A) (void *)((2 << A) - 2)
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#if ENABLED(TFT_INTERFACE_FSMC_8BIT)
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#define FSMC_RS(A) (void *)((2 << (A-1)) - 1)
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#else
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#define FSMC_RS(A) (void *)((2 << A) - 2)
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#endif
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const PinMap PinMap_FSMC_RS[] = {
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#ifdef PF0
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@ -23,8 +23,10 @@
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#ifdef STM32F1xx
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#include <stm32f1xx_hal.h>
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#define __IS_DMA_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CCR & DMA_CCR_EN)
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#elif defined(STM32F4xx)
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#include <stm32f4xx_hal.h>
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#define __IS_DMA_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR & DMA_SxCR_EN)
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#endif
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#include "../../../inc/MarlinConfig.h"
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@ -60,13 +62,6 @@ enum XPTCoordinate : uint8_t {
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#define XPT2046_Z1_THRESHOLD 10
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#endif
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#ifdef STM32F1xx
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#define __IS_DMA_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CCR & DMA_CCR_EN)
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#elif defined(STM32F4xx)
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#define __IS_DMA_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR & DMA_SxCR_EN)
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#endif
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class XPT2046 {
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private:
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static SPI_HandleTypeDef SPIx;
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