🎨 Rename HAL timer elements
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committed by
Scott Lahteine
parent
d75e7784e5
commit
9b1c0a75e1
@ -30,7 +30,7 @@
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void HAL_timer_start(const uint8_t timer_num, const uint32_t frequency) {
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switch (timer_num) {
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case 0:
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case MF_TIMER_STEP:
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CCM_CSCMR1 &= ~CCM_CSCMR1_PERCLK_CLK_SEL; // turn off 24mhz mode
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CCM_CCGR1 |= CCM_CCGR1_GPT1_BUS(CCM_CCGR_ON);
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@ -48,7 +48,7 @@ void HAL_timer_start(const uint8_t timer_num, const uint32_t frequency) {
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attachInterruptVector(IRQ_GPT1, &stepTC_Handler);
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NVIC_SET_PRIORITY(IRQ_GPT1, 16);
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break;
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case 1:
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case MF_TIMER_TEMP:
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CCM_CSCMR1 &= ~CCM_CSCMR1_PERCLK_CLK_SEL; // turn off 24mhz mode
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CCM_CCGR0 |= CCM_CCGR0_GPT2_BUS(CCM_CCGR_ON);
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@ -71,19 +71,15 @@ void HAL_timer_start(const uint8_t timer_num, const uint32_t frequency) {
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void HAL_timer_enable_interrupt(const uint8_t timer_num) {
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switch (timer_num) {
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case 0:
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NVIC_ENABLE_IRQ(IRQ_GPT1);
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break;
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case 1:
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NVIC_ENABLE_IRQ(IRQ_GPT2);
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break;
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case MF_TIMER_STEP: NVIC_ENABLE_IRQ(IRQ_GPT1); break;
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case MF_TIMER_TEMP: NVIC_ENABLE_IRQ(IRQ_GPT2); break;
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}
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}
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void HAL_timer_disable_interrupt(const uint8_t timer_num) {
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switch (timer_num) {
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case 0: NVIC_DISABLE_IRQ(IRQ_GPT1); break;
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case 1: NVIC_DISABLE_IRQ(IRQ_GPT2); break;
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case MF_TIMER_STEP: NVIC_DISABLE_IRQ(IRQ_GPT1); break;
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case MF_TIMER_TEMP: NVIC_DISABLE_IRQ(IRQ_GPT2); break;
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}
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// We NEED memory barriers to ensure Interrupts are actually disabled!
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@ -93,20 +89,16 @@ void HAL_timer_disable_interrupt(const uint8_t timer_num) {
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bool HAL_timer_interrupt_enabled(const uint8_t timer_num) {
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switch (timer_num) {
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case 0: return (NVIC_IS_ENABLED(IRQ_GPT1));
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case 1: return (NVIC_IS_ENABLED(IRQ_GPT2));
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case MF_TIMER_STEP: return (NVIC_IS_ENABLED(IRQ_GPT1));
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case MF_TIMER_TEMP: return (NVIC_IS_ENABLED(IRQ_GPT2));
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}
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return false;
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}
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void HAL_timer_isr_prologue(const uint8_t timer_num) {
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switch (timer_num) {
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case 0:
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GPT1_SR = GPT_IR_OF1IE; // clear OF3 bit
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break;
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case 1:
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GPT2_SR = GPT_IR_OF1IE; // clear OF3 bit
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break;
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case MF_TIMER_STEP: GPT1_SR = GPT_IR_OF1IE; break; // clear OF3 bit
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case MF_TIMER_TEMP: GPT2_SR = GPT_IR_OF1IE; break; // clear OF3 bit
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}
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asm volatile("dsb");
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}
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@ -43,14 +43,14 @@ typedef uint32_t hal_timer_t;
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#define GPT1_TIMER_RATE (GPT_TIMER_RATE / GPT1_TIMER_PRESCALE) // 75MHz
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#define GPT2_TIMER_RATE (GPT_TIMER_RATE / GPT2_TIMER_PRESCALE) // 15MHz
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#ifndef STEP_TIMER_NUM
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#define STEP_TIMER_NUM 0 // Timer Index for Stepper
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#ifndef MF_TIMER_STEP
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#define MF_TIMER_STEP 0 // Timer Index for Stepper
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#endif
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#ifndef PULSE_TIMER_NUM
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#define PULSE_TIMER_NUM STEP_TIMER_NUM
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#ifndef MF_TIMER_PULSE
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#define MF_TIMER_PULSE MF_TIMER_STEP
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#endif
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#ifndef TEMP_TIMER_NUM
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#define TEMP_TIMER_NUM 1 // Timer Index for Temperature
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#ifndef MF_TIMER_TEMP
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#define MF_TIMER_TEMP 1 // Timer Index for Temperature
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#endif
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#define TEMP_TIMER_RATE 1000000
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@ -64,12 +64,12 @@ typedef uint32_t hal_timer_t;
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#define PULSE_TIMER_PRESCALE STEPPER_TIMER_PRESCALE
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#define PULSE_TIMER_TICKS_PER_US STEPPER_TIMER_TICKS_PER_US
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#define ENABLE_STEPPER_DRIVER_INTERRUPT() HAL_timer_enable_interrupt(STEP_TIMER_NUM)
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#define DISABLE_STEPPER_DRIVER_INTERRUPT() HAL_timer_disable_interrupt(STEP_TIMER_NUM)
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#define STEPPER_ISR_ENABLED() HAL_timer_interrupt_enabled(STEP_TIMER_NUM)
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#define ENABLE_STEPPER_DRIVER_INTERRUPT() HAL_timer_enable_interrupt(MF_TIMER_STEP)
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#define DISABLE_STEPPER_DRIVER_INTERRUPT() HAL_timer_disable_interrupt(MF_TIMER_STEP)
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#define STEPPER_ISR_ENABLED() HAL_timer_interrupt_enabled(MF_TIMER_STEP)
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#define ENABLE_TEMPERATURE_INTERRUPT() HAL_timer_enable_interrupt(TEMP_TIMER_NUM)
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#define DISABLE_TEMPERATURE_INTERRUPT() HAL_timer_disable_interrupt(TEMP_TIMER_NUM)
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#define ENABLE_TEMPERATURE_INTERRUPT() HAL_timer_enable_interrupt(MF_TIMER_TEMP)
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#define DISABLE_TEMPERATURE_INTERRUPT() HAL_timer_disable_interrupt(MF_TIMER_TEMP)
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#ifndef HAL_STEP_TIMER_ISR
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#define HAL_STEP_TIMER_ISR() extern "C" void stepTC_Handler() // GPT1_Handler()
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@ -87,27 +87,23 @@ void HAL_timer_start(const uint8_t timer_num, const uint32_t frequency);
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FORCE_INLINE static void HAL_timer_set_compare(const uint8_t timer_num, const hal_timer_t compare) {
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switch (timer_num) {
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case 0:
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GPT1_OCR1 = compare - 1;
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break;
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case 1:
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GPT2_OCR1 = compare - 1;
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break;
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case MF_TIMER_STEP: GPT1_OCR1 = compare - 1; break;
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case MF_TIMER_TEMP: GPT2_OCR1 = compare - 1; break;
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}
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}
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FORCE_INLINE static hal_timer_t HAL_timer_get_compare(const uint8_t timer_num) {
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switch (timer_num) {
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case 0: return GPT1_OCR1;
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case 1: return GPT2_OCR1;
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case MF_TIMER_STEP: return GPT1_OCR1;
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case MF_TIMER_TEMP: return GPT2_OCR1;
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}
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return 0;
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}
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FORCE_INLINE static hal_timer_t HAL_timer_get_count(const uint8_t timer_num) {
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switch (timer_num) {
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case 0: return GPT1_CNT;
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case 1: return GPT2_CNT;
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case MF_TIMER_STEP: return GPT1_CNT;
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case MF_TIMER_TEMP: return GPT2_CNT;
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}
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return 0;
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}
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