Add support for Mks Robin TFT display (#12706)
* Add support for MKS Robin TFT display - Add support for MKS Robin TFT display and encoder for MKS Robin board. - Generic 128x64 UI with x2 upscale is used (for now). - Tested on MKS Robin TFT V2.0 with ST7789V controller.
This commit is contained in:
jmz52
Scott Lahteine
@ -17,7 +17,7 @@ if __name__ == "__main__":
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"--specs=nano.specs",
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"--specs=nosys.specs",
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"-IMarlin/src/HAL",
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"-IMarlin/src/HAL/HAL_STM32F1",
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"-MMD",
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"-MP",
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255
Marlin/src/HAL/HAL_STM32F1/u8g_com_stm32duino_fsmc.cpp
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255
Marlin/src/HAL/HAL_STM32F1/u8g_com_stm32duino_fsmc.cpp
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@ -0,0 +1,255 @@
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/**
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* Marlin 3D Printer Firmware
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* Copyright (C) 2016, 2017 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
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*
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* Based on Sprinter and grbl.
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* Copyright (C) 2011 Camiel Gubbels / Erik van der Zalm
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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/**
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* u8g_com_stm32duino_fsmc.cpp
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*
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* Communication interface for FSMC
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*/
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#include "../../inc/MarlinConfig.h"
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#if HAS_GRAPHICAL_LCD
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#if defined(STM32F1) || defined(STM32F1xx)
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#include "U8glib.h"
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#include "libmaple/fsmc.h"
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#include "libmaple/gpio.h"
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#include "boards.h"
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#define LCD_READ_ID 0x04 /* Read display identification information */
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/* Timing configuration */
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#define FSMC_ADDRESS_SETUP_TIME 15 // AddressSetupTime
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#define FSMC_DATA_SETUP_TIME 15 // DataSetupTime
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void LCD_IO_Init(uint8_t cs, uint8_t rs);
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void LCD_IO_WriteData(uint16_t RegValue);
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void LCD_IO_WriteReg(uint8_t Reg);
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uint32_t LCD_IO_ReadData(uint16_t RegValue, uint8_t ReadSize);
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static uint8_t msgInitCount = 2; // Ignore all messages until 2nd U8G_COM_MSG_INIT
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uint8_t u8g_com_stm32duino_fsmc_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr) {
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if (msgInitCount) {
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if (msg == U8G_COM_MSG_INIT) msgInitCount--;
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if (msgInitCount) return -1;
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}
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static uint8_t isCommand;
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switch(msg) {
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case U8G_COM_MSG_STOP:
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break;
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case U8G_COM_MSG_INIT:
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u8g_SetPIOutput(u8g, U8G_PI_RESET);
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LCD_IO_Init(u8g->pin_list[U8G_PI_CS], u8g->pin_list[U8G_PI_A0]);
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u8g_Delay(100);
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if (arg_ptr != NULL)
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*((uint32_t *)arg_ptr) = LCD_IO_ReadData(LCD_READ_ID, 3);
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isCommand = 0;
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break;
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case U8G_COM_MSG_ADDRESS: // define cmd (arg_val = 0) or data mode (arg_val = 1)
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isCommand = arg_val == 0 ? 1 : 0;
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break;
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case U8G_COM_MSG_RESET:
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u8g_SetPILevel(u8g, U8G_PI_RESET, arg_val);
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break;
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case U8G_COM_MSG_WRITE_BYTE:
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if (isCommand)
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LCD_IO_WriteReg(arg_val);
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else
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LCD_IO_WriteData((uint16_t)arg_val);
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break;
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case U8G_COM_MSG_WRITE_SEQ:
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for (uint8_t i = 0; i < arg_val; i += 2)
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LCD_IO_WriteData(*(uint16_t *)(((uint32_t)arg_ptr) + i));
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break;
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}
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return 1;
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}
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/**
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* FSMC LCD IO
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*/
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#define __ASM __asm
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#define __STATIC_INLINE static inline
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__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) {
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__ASM volatile ("dsb 0xF":::"memory");
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}
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#define FSMC_CS_NE1 PD7
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#define FSMC_CS_NE2 PG9
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#define FSMC_CS_NE3 PG10
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#define FSMC_CS_NE4 PG12
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#define FSMC_RS_A0 PF0
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#define FSMC_RS_A1 PF1
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#define FSMC_RS_A2 PF2
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#define FSMC_RS_A3 PF3
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#define FSMC_RS_A4 PF4
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#define FSMC_RS_A5 PF5
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#define FSMC_RS_A6 PF12
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#define FSMC_RS_A7 PF13
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#define FSMC_RS_A8 PF14
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#define FSMC_RS_A9 PF15
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#define FSMC_RS_A10 PG0
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#define FSMC_RS_A11 PG1
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#define FSMC_RS_A12 PG2
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#define FSMC_RS_A13 PG3
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#define FSMC_RS_A14 PG4
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#define FSMC_RS_A15 PG5
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#define FSMC_RS_A16 PD11
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#define FSMC_RS_A17 PD12
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#define FSMC_RS_A18 PD13
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#define FSMC_RS_A19 PE3
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#define FSMC_RS_A20 PE4
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#define FSMC_RS_A21 PE5
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#define FSMC_RS_A22 PE6
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#define FSMC_RS_A23 PE2
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#define FSMC_RS_A24 PG13
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#define FSMC_RS_A25 PG14
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static uint8_t fsmcInit = 0;
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typedef struct {
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__IO uint16_t REG;
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__IO uint16_t RAM;
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} LCD_CONTROLLER_TypeDef;
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LCD_CONTROLLER_TypeDef *LCD;
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void LCD_IO_Init(uint8_t cs, uint8_t rs) {
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uint32_t controllerAddress;
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if (fsmcInit) return;
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fsmcInit = 1;
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switch(cs) {
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case FSMC_CS_NE1: controllerAddress = (uint32_t)FSMC_NOR_PSRAM_REGION1; break;
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case FSMC_CS_NE2: controllerAddress = (uint32_t)FSMC_NOR_PSRAM_REGION2; break;
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case FSMC_CS_NE3: controllerAddress = (uint32_t)FSMC_NOR_PSRAM_REGION3; break;
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case FSMC_CS_NE4: controllerAddress = (uint32_t)FSMC_NOR_PSRAM_REGION4; break;
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default: return;
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}
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#define _ORADDR(N) controllerAddress |= (_BV32(N) - 2)
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switch(rs) {
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case FSMC_RS_A0: _ORADDR( 1); break;
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case FSMC_RS_A1: _ORADDR( 2); break;
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case FSMC_RS_A2: _ORADDR( 3); break;
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case FSMC_RS_A3: _ORADDR( 4); break;
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case FSMC_RS_A4: _ORADDR( 5); break;
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case FSMC_RS_A5: _ORADDR( 6); break;
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case FSMC_RS_A6: _ORADDR( 7); break;
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case FSMC_RS_A7: _ORADDR( 8); break;
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case FSMC_RS_A8: _ORADDR( 9); break;
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case FSMC_RS_A9: _ORADDR(10); break;
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case FSMC_RS_A10: _ORADDR(11); break;
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case FSMC_RS_A11: _ORADDR(12); break;
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case FSMC_RS_A12: _ORADDR(13); break;
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case FSMC_RS_A13: _ORADDR(14); break;
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case FSMC_RS_A14: _ORADDR(15); break;
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case FSMC_RS_A15: _ORADDR(16); break;
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case FSMC_RS_A16: _ORADDR(17); break;
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case FSMC_RS_A17: _ORADDR(18); break;
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case FSMC_RS_A18: _ORADDR(19); break;
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case FSMC_RS_A19: _ORADDR(20); break;
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case FSMC_RS_A20: _ORADDR(21); break;
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case FSMC_RS_A21: _ORADDR(22); break;
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case FSMC_RS_A22: _ORADDR(23); break;
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case FSMC_RS_A23: _ORADDR(24); break;
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case FSMC_RS_A24: _ORADDR(25); break;
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case FSMC_RS_A25: _ORADDR(26); break;
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default: return;
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}
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rcc_clk_enable(RCC_FSMC);
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gpio_set_mode(GPIOD, 14, GPIO_AF_OUTPUT_PP); // FSMC_D00
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gpio_set_mode(GPIOD, 15, GPIO_AF_OUTPUT_PP); // FSMC_D01
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gpio_set_mode(GPIOD, 0, GPIO_AF_OUTPUT_PP); // FSMC_D02
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gpio_set_mode(GPIOD, 1, GPIO_AF_OUTPUT_PP); // FSMC_D03
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gpio_set_mode(GPIOE, 7, GPIO_AF_OUTPUT_PP); // FSMC_D04
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gpio_set_mode(GPIOE, 8, GPIO_AF_OUTPUT_PP); // FSMC_D05
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gpio_set_mode(GPIOE, 9, GPIO_AF_OUTPUT_PP); // FSMC_D06
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gpio_set_mode(GPIOE, 10, GPIO_AF_OUTPUT_PP); // FSMC_D07
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gpio_set_mode(GPIOE, 11, GPIO_AF_OUTPUT_PP); // FSMC_D08
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gpio_set_mode(GPIOE, 12, GPIO_AF_OUTPUT_PP); // FSMC_D09
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gpio_set_mode(GPIOE, 13, GPIO_AF_OUTPUT_PP); // FSMC_D10
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gpio_set_mode(GPIOE, 14, GPIO_AF_OUTPUT_PP); // FSMC_D11
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gpio_set_mode(GPIOE, 15, GPIO_AF_OUTPUT_PP); // FSMC_D12
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gpio_set_mode(GPIOD, 8, GPIO_AF_OUTPUT_PP); // FSMC_D13
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gpio_set_mode(GPIOD, 9, GPIO_AF_OUTPUT_PP); // FSMC_D14
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gpio_set_mode(GPIOD, 10, GPIO_AF_OUTPUT_PP); // FSMC_D15
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gpio_set_mode(GPIOD, 4, GPIO_AF_OUTPUT_PP); // FSMC_NOE
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gpio_set_mode(GPIOD, 5, GPIO_AF_OUTPUT_PP); // FSMC_NWE
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gpio_set_mode(PIN_MAP[cs].gpio_device, PIN_MAP[cs].gpio_bit, GPIO_AF_OUTPUT_PP); //FSMC_CS_NEx
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gpio_set_mode(PIN_MAP[rs].gpio_device, PIN_MAP[rs].gpio_bit, GPIO_AF_OUTPUT_PP); //FSMC_RS_Ax
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FSMC_NOR_PSRAM4_BASE->BCR = FSMC_BCR_WREN | FSMC_BCR_MTYP_SRAM | FSMC_BCR_MWID_16BITS | FSMC_BCR_MBKEN;
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FSMC_NOR_PSRAM4_BASE->BTR = (FSMC_DATA_SETUP_TIME << 8) | FSMC_ADDRESS_SETUP_TIME;
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afio_remap(AFIO_REMAP_FSMC_NADV);
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LCD = (LCD_CONTROLLER_TypeDef*)controllerAddress;
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}
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void LCD_IO_WriteData(uint16_t RegValue) {
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LCD->RAM = RegValue;
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__DSB();
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}
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void LCD_IO_WriteReg(uint8_t Reg) {
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LCD->REG = (uint16_t)Reg;
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__DSB();
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}
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uint32_t LCD_IO_ReadData(uint16_t RegValue, uint8_t ReadSize) {
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volatile uint32_t data;
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LCD->REG = (uint16_t)RegValue;
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__DSB();
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data = LCD->RAM; // dummy read
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data = LCD->RAM & 0x00FF;
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while (--ReadSize) {
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data <<= 8;
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data |= (LCD->RAM & 0x00FF);
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}
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return (uint32_t)data;
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}
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#endif // STM32F1 || STM32F1xx
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#endif // HAS_GRAPHICAL_LCD
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