Add Lerdge S,X,K (#18302)
This commit is contained in:
		
							
								
								
									
										418
									
								
								buildroot/share/PlatformIO/variants/LERDGE/PeripheralPins.c
									
									
									
									
									
										Normal file
									
								
							
							
						
						
									
										418
									
								
								buildroot/share/PlatformIO/variants/LERDGE/PeripheralPins.c
									
									
									
									
									
										Normal file
									
								
							| @@ -0,0 +1,418 @@ | ||||
| /* | ||||
|  ******************************************************************************* | ||||
|  * Copyright (c) 2019, STMicroelectronics | ||||
|  * All rights reserved. | ||||
|  * | ||||
|  * Redistribution and use in source and binary forms, with or without | ||||
|  * modification, are permitted provided that the following conditions are met: | ||||
|  * | ||||
|  * 1. Redistributions of source code must retain the above copyright notice, | ||||
|  *    this list of conditions and the following disclaimer. | ||||
|  * 2. Redistributions in binary form must reproduce the above copyright notice, | ||||
|  *    this list of conditions and the following disclaimer in the documentation | ||||
|  *    and/or other materials provided with the distribution. | ||||
|  * 3. Neither the name of STMicroelectronics nor the names of its contributors | ||||
|  *    may be used to endorse or promote products derived from this software | ||||
|  *    without specific prior written permission. | ||||
|  * | ||||
|  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | ||||
|  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | ||||
|  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | ||||
|  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | ||||
|  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | ||||
|  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | ||||
|  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | ||||
|  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | ||||
|  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | ||||
|  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||||
|  ******************************************************************************* | ||||
|  * Automatically generated from STM32F407Z(E-G)Tx.xml | ||||
|  */ | ||||
| #include <Arduino.h> | ||||
| #include <PeripheralPins.h> | ||||
|  | ||||
| /* ===== | ||||
|  * Note: Commented lines are alternative possibilities which are not used per default. | ||||
|  *       If you change them, you will have to know what you do | ||||
|  * ===== | ||||
|  */ | ||||
|  | ||||
| //*** ADC *** | ||||
|  | ||||
| #ifdef HAL_ADC_MODULE_ENABLED | ||||
| const PinMap PinMap_ADC[] = { | ||||
|   {PA_0,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 | ||||
|   //{PA_0,  ADC2,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_IN0 | ||||
|   //{PA_0,  ADC3,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_IN0 | ||||
|   {PA_1,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 | ||||
|   //{PA_1,  ADC2,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 | ||||
|   //{PA_1,  ADC3,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1 | ||||
|   //{PA_2,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 | ||||
|   {PA_2,  ADC2,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 | ||||
|   //{PA_2,  ADC3,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2 | ||||
|   //{PA_3,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 | ||||
|   //{PA_3,  ADC2,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 | ||||
|   {PA_3,  ADC3,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3 | ||||
|   {PA_4,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 | ||||
|   //{PA_4,  ADC2,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 | ||||
|   //{PA_5,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 | ||||
|   {PA_5,  ADC2,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 | ||||
|   {PA_6,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 | ||||
|   //{PA_6,  ADC2,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 | ||||
|   {PA_7,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 | ||||
|   //{PA_7,  ADC2,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 | ||||
|   //{PB_0,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 | ||||
|   {PB_0,  ADC2,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 | ||||
|   {PB_1,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 | ||||
|   //{PB_1,  ADC2,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9 | ||||
|   //{PC_0,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 | ||||
|   //{PC_0,  ADC2,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 | ||||
|   {PC_0,  ADC3,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_IN10 | ||||
|   {PC_1,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 | ||||
|   //{PC_1,  ADC2,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11 | ||||
|   //{PC_1,  ADC3,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_IN11 | ||||
|   //{PC_2,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 | ||||
|   {PC_2,  ADC2,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 | ||||
|   //{PC_2,  ADC3,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_IN12 | ||||
|   //{PC_3,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 | ||||
|   //{PC_3,  ADC2,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13 | ||||
|   {PC_3,  ADC3,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_IN13 | ||||
|   //{PC_4,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 | ||||
|   {PC_4,  ADC2,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14 | ||||
|   //{PC_5,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 | ||||
|   {PC_5,  ADC2,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 | ||||
|   {PF_3,  ADC3,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_IN9 | ||||
|   {PF_4,  ADC3,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_IN14 | ||||
|   {PF_5,  ADC3,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_IN15 | ||||
|   {PF_6,  ADC3,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4 | ||||
|   {PF_7,  ADC3,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_IN5 | ||||
|   {PF_8,  ADC3,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6 | ||||
|   //{PF_9,  ADC3,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7 | ||||
|   {PF_10, ADC3,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8 | ||||
|   {NC,    NP,    0} | ||||
| }; | ||||
| #endif | ||||
|  | ||||
| //*** DAC *** | ||||
|  | ||||
| #ifdef HAL_DAC_MODULE_ENABLED | ||||
| const PinMap PinMap_DAC[] = { | ||||
|   {PA_4,  DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT1 | ||||
|   {PA_5,  DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC_OUT2 | ||||
|   {NC,    NP,    0} | ||||
| }; | ||||
| #endif | ||||
|  | ||||
| //*** I2C *** | ||||
|  | ||||
| #ifdef HAL_I2C_MODULE_ENABLED | ||||
| const PinMap PinMap_I2C_SDA[] = { | ||||
|   {PB_7,  I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, | ||||
|   {PB_9,  I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, | ||||
|   {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, | ||||
|   {PC_9,  I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, | ||||
|   {PF_0,  I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, | ||||
|   {NC,    NP,    0} | ||||
| }; | ||||
| #endif | ||||
|  | ||||
| #ifdef HAL_I2C_MODULE_ENABLED | ||||
| const PinMap PinMap_I2C_SCL[] = { | ||||
|   {PA_8,  I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, | ||||
|   {PB_6,  I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, | ||||
|   {PB_8,  I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, | ||||
|   {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, | ||||
|   {PF_1,  I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, | ||||
|   {NC,    NP,    0} | ||||
| }; | ||||
| #endif | ||||
|  | ||||
| //*** PWM *** | ||||
|  | ||||
| #ifdef HAL_TIM_MODULE_ENABLED | ||||
| const PinMap PinMap_PWM[] = { | ||||
|   {PA_0,  TIM2,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 | ||||
|   //{PA_0,  TIM5,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 | ||||
|   {PA_1,  TIM2,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 | ||||
|   //{PA_1,  TIM5,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 | ||||
|   {PA_2,  TIM2,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 | ||||
|   //{PA_2,  TIM5,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 | ||||
|   //{PA_2,  TIM9,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 | ||||
|   {PA_3,  TIM2,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 | ||||
|   //{PA_3,  TIM5,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 | ||||
|   //{PA_3,  TIM9,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 | ||||
|   {PA_5,  TIM2,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 | ||||
|   //{PA_5,  TIM8,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N | ||||
|   {PA_6,  TIM3,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 | ||||
|   //{PA_6,  TIM13,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 | ||||
|   //{PA_7,  TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N | ||||
|   {PA_7,  TIM3,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 | ||||
|   //{PA_7,  TIM8,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N | ||||
|   //{PA_7,  TIM14,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 | ||||
|   {PA_8,  TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 | ||||
|   {PA_9,  TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 | ||||
|   {PA_10, TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 | ||||
|   {PA_11, TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 | ||||
|   //{PA_15, TIM2,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 | ||||
|   //{PB_0,  TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N | ||||
|   {PB_0,  TIM3,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 | ||||
|   //{PB_0,  TIM8,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N | ||||
|   //{PB_1,  TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N | ||||
|   {PB_1,  TIM3,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 | ||||
|   //{PB_1,  TIM8,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N | ||||
|   //{PB_3,  TIM2,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 | ||||
|   {PB_4,  TIM3,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 | ||||
|   {PB_5,  TIM3,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 | ||||
|   {PB_6,  TIM4,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 | ||||
|   {PB_7,  TIM4,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 | ||||
|   {PB_8,  TIM4,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 | ||||
|   {PB_8,  TIM10,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 | ||||
|   {PB_9,  TIM4,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 | ||||
|   {PB_9,  TIM11,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 | ||||
|   {PB_10, TIM2,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 | ||||
|   {PB_11, TIM2,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 | ||||
|   {PB_13, TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N | ||||
|   {PB_14, TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N | ||||
|   {PB_14, TIM8,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N | ||||
|   {PB_14, TIM12,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1 | ||||
|   {PB_15, TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N | ||||
|   {PB_15, TIM8,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N | ||||
|   {PB_15, TIM12,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2 | ||||
|   {PC_6,  TIM3,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 | ||||
|   {PC_6,  TIM8,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 | ||||
|   {PC_7,  TIM3,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 | ||||
|   {PC_7,  TIM8,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 | ||||
|   {PC_8,  TIM3,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 | ||||
|   {PC_8,  TIM8,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 | ||||
|   {PC_9,  TIM3,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 | ||||
|   {PC_9,  TIM8,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 | ||||
|   {PD_12, TIM4,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 | ||||
|   {PD_13, TIM4,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 | ||||
|   {PD_14, TIM4,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 | ||||
|   {PD_15, TIM4,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 | ||||
|   {PE_5,  TIM9,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 | ||||
|   {PE_6,  TIM9,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 | ||||
|   {PE_8,  TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N | ||||
|   {PE_9,  TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 | ||||
|   {PE_10, TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N | ||||
|   {PE_11, TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 | ||||
|   {PE_12, TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N | ||||
|   {PE_13, TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 | ||||
|   {PE_14, TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 | ||||
|   {PF_6,  TIM10,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 | ||||
|   {PF_7,  TIM11,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 | ||||
|   {PF_8,  TIM13,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 | ||||
|   {PF_9,  TIM14,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 | ||||
|   {NC,    NP,    0} | ||||
| }; | ||||
| #endif | ||||
|  | ||||
| //*** SERIAL *** | ||||
|  | ||||
| #ifdef HAL_UART_MODULE_ENABLED | ||||
| const PinMap PinMap_UART_TX[] = { | ||||
|   {PA_0,  UART4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, | ||||
|   {PA_2,  USART2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, | ||||
|   {PA_9,  USART1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, | ||||
|   {PB_6,  USART1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, | ||||
|   {PB_10, USART3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, | ||||
|   {PC_6,  USART6,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, | ||||
|   //{PC_10, UART4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, | ||||
|   {PC_10, USART3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, | ||||
|   {PC_12, UART5,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, | ||||
|   {PD_5,  USART2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, | ||||
|   {PD_8,  USART3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, | ||||
|   {PG_14, USART6,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, | ||||
|   {NC,    NP,    0} | ||||
| }; | ||||
| #endif | ||||
|  | ||||
| #ifdef HAL_UART_MODULE_ENABLED | ||||
| const PinMap PinMap_UART_RX[] = { | ||||
|   {PA_1,  UART4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, | ||||
|   {PA_3,  USART2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, | ||||
|   {PA_10, USART1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, | ||||
|   {PB_7,  USART1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, | ||||
|   {PB_11, USART3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, | ||||
|   {PC_7,  USART6,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, | ||||
|   //{PC_11, UART4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, | ||||
|   {PC_11, USART3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, | ||||
|   {PD_2,  UART5,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, | ||||
|   {PD_6,  USART2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, | ||||
|   {PD_9,  USART3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, | ||||
|   {PG_9,  USART6,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, | ||||
|   {NC,    NP,    0} | ||||
| }; | ||||
| #endif | ||||
|  | ||||
| #ifdef HAL_UART_MODULE_ENABLED | ||||
| const PinMap PinMap_UART_RTS[] = { | ||||
|   {PA_1,  USART2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, | ||||
|   {PA_12, USART1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, | ||||
|   {PB_14, USART3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, | ||||
|   {PD_4,  USART2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, | ||||
|   {PD_12, USART3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, | ||||
|   {PG_8,  USART6,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, | ||||
|   {PG_12, USART6,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, | ||||
|   {NC,    NP,    0} | ||||
| }; | ||||
| #endif | ||||
|  | ||||
| #ifdef HAL_UART_MODULE_ENABLED | ||||
| const PinMap PinMap_UART_CTS[] = { | ||||
|   {PA_0,  USART2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, | ||||
|   {PA_11, USART1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, | ||||
|   {PB_13, USART3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, | ||||
|   {PD_3,  USART2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, | ||||
|   {PD_11, USART3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, | ||||
|   {PG_13, USART6,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, | ||||
|   {PG_15, USART6,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, | ||||
|   {NC,    NP,    0} | ||||
| }; | ||||
| #endif | ||||
|  | ||||
| //*** SPI *** | ||||
|  | ||||
| #ifdef HAL_SPI_MODULE_ENABLED | ||||
| const PinMap PinMap_SPI_MOSI[] = { | ||||
|   {PA_7,  SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, | ||||
|   {PB_5,  SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, | ||||
|   {PB_5,  SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, | ||||
|   {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, | ||||
|   {PC_3,  SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, | ||||
|   {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, | ||||
|   {NC,    NP,    0} | ||||
| }; | ||||
| #endif | ||||
|  | ||||
| #ifdef HAL_SPI_MODULE_ENABLED | ||||
| const PinMap PinMap_SPI_MISO[] = { | ||||
|   {PA_6,  SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, | ||||
|   {PB_4,  SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, | ||||
|   {PB_4,  SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, | ||||
|   {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, | ||||
|   {PC_2,  SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, | ||||
|   {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, | ||||
|   {NC,    NP,    0} | ||||
| }; | ||||
| #endif | ||||
|  | ||||
| #ifdef HAL_SPI_MODULE_ENABLED | ||||
| const PinMap PinMap_SPI_SCLK[] = { | ||||
|   {PA_5,  SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, | ||||
|   {PB_3,  SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, | ||||
|   {PB_3,  SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, | ||||
|   {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, | ||||
|   {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, | ||||
|   {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, | ||||
|   {NC,    NP,    0} | ||||
| }; | ||||
| #endif | ||||
|  | ||||
| #ifdef HAL_SPI_MODULE_ENABLED | ||||
| const PinMap PinMap_SPI_SSEL[] = { | ||||
|   {PA_4,  SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, | ||||
|   {PA_4,  SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, | ||||
|   {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, | ||||
|   {PA_15, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, | ||||
|   {PB_9,  SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, | ||||
|   {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, | ||||
|   {NC,    NP,    0} | ||||
| }; | ||||
| #endif | ||||
|  | ||||
| //*** CAN *** | ||||
|  | ||||
| #ifdef HAL_CAN_MODULE_ENABLED | ||||
| const PinMap PinMap_CAN_RD[] = { | ||||
|   {PA_11, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, | ||||
|   {PB_5,  CAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, | ||||
|   {PB_8,  CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, | ||||
|   {PB_12, CAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, | ||||
|   {PD_0,  CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, | ||||
|   {NC,    NP,    0} | ||||
| }; | ||||
| #endif | ||||
|  | ||||
| #ifdef HAL_CAN_MODULE_ENABLED | ||||
| const PinMap PinMap_CAN_TD[] = { | ||||
|   {PA_12, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, | ||||
|   {PB_6,  CAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, | ||||
|   {PB_9,  CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, | ||||
|   {PB_13, CAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, | ||||
|   {PD_1,  CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, | ||||
|   {NC,    NP,    0} | ||||
| }; | ||||
| #endif | ||||
|  | ||||
| //*** ETHERNET *** | ||||
|  | ||||
| #ifdef HAL_ETH_MODULE_ENABLED | ||||
| const PinMap PinMap_Ethernet[] = { | ||||
|   {PA_0,  ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS | ||||
|   {PA_1,  ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK|ETH_RX_CLK | ||||
|   {PA_2,  ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDIO | ||||
|   {PA_3,  ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL | ||||
|   {PA_7,  ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS_DV|ETH_RX_DV | ||||
|   {PB_0,  ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2 | ||||
|   {PB_1,  ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3 | ||||
|   {PB_5,  ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT | ||||
|   {PB_8,  ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 | ||||
|   {PB_10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER | ||||
|   {PB_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN | ||||
|   {PB_12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 | ||||
|   {PB_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 | ||||
|   {PC_1,  ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDC | ||||
|   {PC_2,  ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2 | ||||
|   {PC_3,  ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK | ||||
|   {PC_4,  ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD0 | ||||
|   {PC_5,  ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD1 | ||||
|   {PE_2,  ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3 | ||||
|   {PG_8,  ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT | ||||
|   {PG_11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN | ||||
|   {PG_13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0 | ||||
|   {PG_14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1 | ||||
|   {NC,    NP,    0} | ||||
| }; | ||||
| #endif | ||||
|  | ||||
| //*** No QUADSPI *** | ||||
|  | ||||
| //*** USB *** | ||||
|  | ||||
| #ifdef HAL_PCD_MODULE_ENABLED | ||||
| const PinMap PinMap_USB_OTG_FS[] = { | ||||
|   //{PA_8,  USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_SOF | ||||
|   //{PA_9,  USB_OTG_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_FS_VBUS | ||||
|   //{PA_10, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_ID | ||||
|   {PA_11, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_DM | ||||
|   {PA_12, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_DP | ||||
|   {NC,    NP,    0} | ||||
| }; | ||||
| #endif | ||||
|  | ||||
| #ifdef HAL_PCD_MODULE_ENABLED | ||||
| const PinMap PinMap_USB_OTG_HS[] = { | ||||
| #ifdef USE_USB_HS_IN_FS | ||||
|   {PA_4,  USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_SOF | ||||
|   {PB_12, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_ID | ||||
|   {PB_13, USB_OTG_HS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_HS_VBUS | ||||
|   {PB_14, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_DM | ||||
|   {PB_15, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_DP | ||||
| #else | ||||
|   {PA_3,  USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D0 | ||||
|   {PA_5,  USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_CK | ||||
|   {PB_0,  USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D1 | ||||
|   {PB_1,  USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D2 | ||||
|   {PB_5,  USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D7 | ||||
|   {PB_10, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D3 | ||||
|   {PB_11, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D4 | ||||
|   {PB_12, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D5 | ||||
|   {PB_13, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D6 | ||||
|   {PC_0,  USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_STP | ||||
|   {PC_2,  USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_DIR | ||||
|   {PC_3,  USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_NXT | ||||
| #endif /* USE_USB_HS_IN_FS */ | ||||
|   {NC,    NP,    0} | ||||
| }; | ||||
| #endif | ||||
							
								
								
									
										50
									
								
								buildroot/share/PlatformIO/variants/LERDGE/PinNamesVar.h
									
									
									
									
									
										Normal file
									
								
							
							
						
						
									
										50
									
								
								buildroot/share/PlatformIO/variants/LERDGE/PinNamesVar.h
									
									
									
									
									
										Normal file
									
								
							| @@ -0,0 +1,50 @@ | ||||
| /* SYS_WKUP */ | ||||
| #ifdef PWR_WAKEUP_PIN1 | ||||
|   SYS_WKUP1 = PA_0, | ||||
| #endif | ||||
| #ifdef PWR_WAKEUP_PIN2 | ||||
|   SYS_WKUP2 = NC, | ||||
| #endif | ||||
| #ifdef PWR_WAKEUP_PIN3 | ||||
|   SYS_WKUP3 = NC, | ||||
| #endif | ||||
| #ifdef PWR_WAKEUP_PIN4 | ||||
|   SYS_WKUP4 = NC, | ||||
| #endif | ||||
| #ifdef PWR_WAKEUP_PIN5 | ||||
|   SYS_WKUP5 = NC, | ||||
| #endif | ||||
| #ifdef PWR_WAKEUP_PIN6 | ||||
|   SYS_WKUP6 = NC, | ||||
| #endif | ||||
| #ifdef PWR_WAKEUP_PIN7 | ||||
|   SYS_WKUP7 = NC, | ||||
| #endif | ||||
| #ifdef PWR_WAKEUP_PIN8 | ||||
|   SYS_WKUP8 = NC, | ||||
| #endif | ||||
| /* USB */ | ||||
| #ifdef USBCON | ||||
|   USB_OTG_FS_SOF      = PA_8, | ||||
|   USB_OTG_FS_VBUS     = PA_9, | ||||
|   USB_OTG_FS_ID       = PA_10, | ||||
|   USB_OTG_FS_DM       = PA_11, | ||||
|   USB_OTG_FS_DP       = PA_12, | ||||
|   USB_OTG_HS_ULPI_D0  = PA_3, | ||||
|   USB_OTG_HS_SOF      = PA_4, | ||||
|   USB_OTG_HS_ULPI_CK  = PA_5, | ||||
|   USB_OTG_HS_ULPI_D1  = PB_0, | ||||
|   USB_OTG_HS_ULPI_D2  = PB_1, | ||||
|   USB_OTG_HS_ULPI_D7  = PB_5, | ||||
|   USB_OTG_HS_ULPI_D3  = PB_10, | ||||
|   USB_OTG_HS_ULPI_D4  = PB_11, | ||||
|   USB_OTG_HS_ID       = PB_12, | ||||
|   USB_OTG_HS_ULPI_D5  = PB_12, | ||||
|   USB_OTG_HS_ULPI_D6  = PB_13, | ||||
|   USB_OTG_HS_VBUS     = PB_13, | ||||
|   USB_OTG_HS_DM       = PB_14, | ||||
|   USB_OTG_HS_DP       = PB_15, | ||||
|   USB_OTG_HS_ULPI_STP = PC_0, | ||||
|   USB_OTG_HS_ULPI_DIR = PC_2, | ||||
|   USB_OTG_HS_ULPI_NXT = PC_3, | ||||
| #endif | ||||
							
								
								
									
										297
									
								
								buildroot/share/PlatformIO/variants/LERDGE/variant.cpp
									
									
									
									
									
										Normal file
									
								
							
							
						
						
									
										297
									
								
								buildroot/share/PlatformIO/variants/LERDGE/variant.cpp
									
									
									
									
									
										Normal file
									
								
							| @@ -0,0 +1,297 @@ | ||||
| /* | ||||
|  ******************************************************************************* | ||||
|  * Copyright (c) 2017, STMicroelectronics | ||||
|  * All rights reserved. | ||||
|  * | ||||
|  * Redistribution and use in source and binary forms, with or without | ||||
|  * modification, are permitted provided that the following conditions are met: | ||||
|  * | ||||
|  * 1. Redistributions of source code must retain the above copyright notice, | ||||
|  *    this list of conditions and the following disclaimer. | ||||
|  * 2. Redistributions in binary form must reproduce the above copyright notice, | ||||
|  *    this list of conditions and the following disclaimer in the documentation | ||||
|  *    and/or other materials provided with the distribution. | ||||
|  * 3. Neither the name of STMicroelectronics nor the names of its contributors | ||||
|  *    may be used to endorse or promote products derived from this software | ||||
|  *    without specific prior written permission. | ||||
|  * | ||||
|  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | ||||
|  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | ||||
|  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | ||||
|  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | ||||
|  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | ||||
|  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | ||||
|  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | ||||
|  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | ||||
|  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | ||||
|  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||||
|  ******************************************************************************* | ||||
|  */ | ||||
|  | ||||
| #include "pins_arduino.h" | ||||
|  | ||||
| #ifdef __cplusplus | ||||
| extern "C" { | ||||
| #endif | ||||
|  | ||||
|  | ||||
| const PinName digitalPin[] = { | ||||
|  PB_12, | ||||
|  PB_13, | ||||
|  PB_14, | ||||
|  PB_15, | ||||
|  PD_8, | ||||
|  PD_9, | ||||
|  PD_10, | ||||
|  PD_11, | ||||
|  PD_12, | ||||
|  PD_13, | ||||
|  PD_14, | ||||
|  PD_15, | ||||
|  PG_2, | ||||
|  PG_3, | ||||
|  PG_4, | ||||
|  PG_5, | ||||
|  PG_6, | ||||
|  PG_7, | ||||
|  PG_8, | ||||
|  PC_6, | ||||
|  PC_7, | ||||
|  PC_8, | ||||
|  PC_9, | ||||
|  PA_8, | ||||
|  PA_9, | ||||
|  PA_10, | ||||
|  PA_11, | ||||
|  PA_12, | ||||
|  PA_13, | ||||
|  PA_14, | ||||
|  PA_15, | ||||
|  PC_10, | ||||
|  PC_11, | ||||
|  PC_12, | ||||
|  PD_0, | ||||
|  PD_1, | ||||
|  PD_2, | ||||
|  PD_3, | ||||
|  PD_4, | ||||
|  PD_5, | ||||
|  PD_6, | ||||
|  PD_7, | ||||
|  PG_9, | ||||
|  PG_10, | ||||
|  PG_11, | ||||
|  PG_12, | ||||
|  PG_13, | ||||
|  PG_14, | ||||
|  PG_15, | ||||
|  PB_3, | ||||
|  PB_4, | ||||
|  PB_5, | ||||
|  PB_6, | ||||
|  PB_7, | ||||
|  PB_8, | ||||
|  PB_9, | ||||
|  PB_10, | ||||
|  PB_11, | ||||
|  PE_14, | ||||
|  PE_15, | ||||
|  PE_12, | ||||
|  PE_13, | ||||
|  PE_10, | ||||
|  PE_11, | ||||
|  PE_8, | ||||
|  PE_9, | ||||
|  PG_1, | ||||
|  PE_7, | ||||
|  PF_15, | ||||
|  PG_0, | ||||
|  PF_13, | ||||
|  PF_14, | ||||
|  PF_11, | ||||
|  PF_12, | ||||
|  PB_2, | ||||
|  PB_1, | ||||
|  PC_5, | ||||
|  PB_0, | ||||
|  PA_7, | ||||
|  PC_4, | ||||
|  PA_5, | ||||
|  PA_6, | ||||
|  PA_3, | ||||
|  PA_4, | ||||
|  PA_1, | ||||
|  PA_2, | ||||
|  PC_3, | ||||
|  PA_0, | ||||
|  PC_1, | ||||
|  PC_2, | ||||
|  PC_0, | ||||
|  PF_8, | ||||
|  PF_6, | ||||
|  PF_7, | ||||
|  PF_9, | ||||
|  PF_10, | ||||
|  PF_4, | ||||
|  PF_5, | ||||
|  PF_2, | ||||
|  PF_3, | ||||
|  PF_0, | ||||
|  PF_1, | ||||
|  PE_6, | ||||
|  PC_13, | ||||
|  PE_4, | ||||
|  PE_5, | ||||
|  PE_2, | ||||
|  PE_3, | ||||
|  PE_0, | ||||
|  PE_1, | ||||
|  PC_14, | ||||
|  PC_15, | ||||
| }; | ||||
|  | ||||
| #ifdef __cplusplus | ||||
| } | ||||
| #endif | ||||
|  | ||||
| // ---------------------------------------------------------------------------- | ||||
|  | ||||
| #ifdef __cplusplus | ||||
| extern "C" { | ||||
| #endif | ||||
|  | ||||
| #define __fatal_error(X) | ||||
|  | ||||
|  | ||||
| /** | ||||
|   * @brief  System Clock Configuration | ||||
|   * | ||||
|   *         The system Clock is configured for F4/F7 as follows: | ||||
|   *            System Clock source            = PLL (HSE) | ||||
|   *            SYSCLK(Hz)                     = 168000000 | ||||
|   *            HCLK(Hz)                       = 168000000 | ||||
|   *            AHB Prescaler                  = 1 | ||||
|   *            APB1 Prescaler                 = 4 | ||||
|   *            APB2 Prescaler                 = 2 | ||||
|   *            HSE Frequency(Hz)              = HSE_VALUE | ||||
|   *            PLL_M                          = HSE_VALUE/1000000 | ||||
|   *            PLL_N                          = 336 | ||||
|   *            PLL_P                          = 2 | ||||
|   *            PLL_Q                          = 7 | ||||
|   *            VDD(V)                         = 3.3 | ||||
|   *            Main regulator output voltage  = Scale1 mode | ||||
|   *            Flash Latency(WS)              = 5 | ||||
|   * | ||||
|   *         The system Clock is configured for L4 as follows: | ||||
|   *            System Clock source            = PLL (MSI) | ||||
|   *            SYSCLK(Hz)                     = 80000000 | ||||
|   *            HCLK(Hz)                       = 80000000 | ||||
|   *            AHB Prescaler                  = 1 | ||||
|   *            APB1 Prescaler                 = 1 | ||||
|   *            APB2 Prescaler                 = 1 | ||||
|   *            MSI Frequency(Hz)              = MSI_VALUE (4000000) | ||||
|   *            LSE Frequency(Hz)              = 32768 | ||||
|   *            PLL_M                          = 1 | ||||
|   *            PLL_N                          = 40 | ||||
|   *            PLL_P                          = 7 | ||||
|   *            PLL_Q                          = 2 | ||||
|   *            PLL_R                          = 2 <= This is the source for SysClk, not as on F4/7 PLL_P | ||||
|   *            Flash Latency(WS)              = 4 | ||||
|   * @param  None | ||||
|   * @retval None | ||||
|   * | ||||
|   * PLL is configured as follows: | ||||
|   * | ||||
|   *     VCO_IN | ||||
|   *         F4/F7 = HSE / M | ||||
|   *         L4    = MSI / M | ||||
|   *     VCO_OUT | ||||
|   *         F4/F7 = HSE / M * N | ||||
|   *         L4    = MSI / M * N | ||||
|   *     PLLCLK | ||||
|   *         F4/F7 = HSE / M * N / P | ||||
|   *         L4    = MSI / M * N / R | ||||
|   *     PLL48CK | ||||
|   *         F4/F7 = HSE / M * N / Q | ||||
|   *         L4    = MSI / M * N / Q  USB Clock is obtained over PLLSAI1 | ||||
|   * | ||||
|   *     SYSCLK = PLLCLK | ||||
|   *     HCLK   = SYSCLK / AHB_PRESC | ||||
|   *     PCLKx  = HCLK / APBx_PRESC | ||||
|   * | ||||
|   * Constraints on parameters: | ||||
|   * | ||||
|   *     VCO_IN between 1MHz and 2MHz (2MHz recommended) | ||||
|   *     VCO_OUT between 192MHz and 432MHz | ||||
|   *     HSE = 8MHz | ||||
|   *     M = 2 .. 63 (inclusive) | ||||
|   *     N = 192 ... 432 (inclusive) | ||||
|   *     P = 2, 4, 6, 8 | ||||
|   *     Q = 2 .. 15 (inclusive) | ||||
|   * | ||||
|   *     AHB_PRESC=1,2,4,8,16,64,128,256,512 | ||||
|   *     APBx_PRESC=1,2,4,8,16 | ||||
|   * | ||||
|   * Output clocks: | ||||
|   * | ||||
|   * CPU             SYSCLK      max 168MHz | ||||
|   * USB,RNG,SDIO    PLL48CK     must be 48MHz for USB | ||||
|   * AHB             HCLK        max 168MHz | ||||
|   * APB1            PCLK1       max 42MHz | ||||
|   * APB2            PCLK2       max 84MHz | ||||
|   * | ||||
|   * Timers run from APBx if APBx_PRESC=1, else 2x APBx | ||||
|   */ | ||||
| void SystemClock_Config(void) | ||||
| { | ||||
|     RCC_ClkInitTypeDef RCC_ClkInitStruct; | ||||
|     RCC_OscInitTypeDef RCC_OscInitStruct; | ||||
|  | ||||
|     __PWR_CLK_ENABLE(); | ||||
|  | ||||
|     /* The voltage scaling allows optimizing the power consumption when the device is | ||||
|        clocked below the maximum system frequency, to update the voltage scaling value | ||||
|        regarding system frequency refer to product datasheet.  */ | ||||
|     __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); | ||||
|  | ||||
|     /* Enable HSE Oscillator and activate PLL with HSE as source */ | ||||
|     RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; | ||||
|     RCC_OscInitStruct.HSEState = RCC_HSE_ON; | ||||
|     RCC_OscInitStruct.HSIState = RCC_HSI_OFF; | ||||
|     RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; | ||||
|     /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 | ||||
|      clocks dividers */ | ||||
|     RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); | ||||
|     RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; | ||||
|  | ||||
|     RCC_OscInitStruct.PLL.PLLM = 25; | ||||
|     RCC_OscInitStruct.PLL.PLLN = 336; | ||||
|     RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; | ||||
|     RCC_OscInitStruct.PLL.PLLQ = 7; | ||||
|  | ||||
|     RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1; | ||||
|     RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; | ||||
|     RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; | ||||
|  | ||||
|     if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { | ||||
|       __fatal_error("HAL_RCC_OscConfig"); | ||||
|     } | ||||
|  | ||||
|     if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) | ||||
|     { | ||||
|       __fatal_error("HAL_RCC_ClockConfig"); | ||||
|     } | ||||
|  | ||||
|     /**Configure the Systick interrupt time */ | ||||
|     HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / 1000); | ||||
|  | ||||
|     /**Configure the Systick */ | ||||
|     HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); | ||||
|  | ||||
|     /* SysTick_IRQn interrupt configuration */ | ||||
|     HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); | ||||
| } | ||||
|  | ||||
| #ifdef __cplusplus | ||||
| } | ||||
| #endif | ||||
							
								
								
									
										238
									
								
								buildroot/share/PlatformIO/variants/LERDGE/variant.h
									
									
									
									
									
										Normal file
									
								
							
							
						
						
									
										238
									
								
								buildroot/share/PlatformIO/variants/LERDGE/variant.h
									
									
									
									
									
										Normal file
									
								
							| @@ -0,0 +1,238 @@ | ||||
| /* | ||||
|  ******************************************************************************* | ||||
|  * Copyright (c) 2017, STMicroelectronics | ||||
|  * All rights reserved. | ||||
|  * | ||||
|  * Redistribution and use in source and binary forms, with or without | ||||
|  * modification, are permitted provided that the following conditions are met: | ||||
|  * | ||||
|  * 1. Redistributions of source code must retain the above copyright notice, | ||||
|  *    this list of conditions and the following disclaimer. | ||||
|  * 2. Redistributions in binary form must reproduce the above copyright notice, | ||||
|  *    this list of conditions and the following disclaimer in the documentation | ||||
|  *    and/or other materials provided with the distribution. | ||||
|  * 3. Neither the name of STMicroelectronics nor the names of its contributors | ||||
|  *    may be used to endorse or promote products derived from this software | ||||
|  *    without specific prior written permission. | ||||
|  * | ||||
|  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | ||||
|  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | ||||
|  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | ||||
|  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | ||||
|  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | ||||
|  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | ||||
|  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | ||||
|  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | ||||
|  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | ||||
|  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||||
|  ******************************************************************************* | ||||
|  */ | ||||
|  | ||||
| #pragma once | ||||
|  | ||||
| #ifdef __cplusplus | ||||
| extern "C" { | ||||
| #endif // __cplusplus | ||||
|  | ||||
| /*---------------------------------------------------------------------------- | ||||
|  *        Pins | ||||
|  *----------------------------------------------------------------------------*/ | ||||
|  | ||||
| // Left Side | ||||
| #define PB12 0 | ||||
| #define PB13 1 | ||||
| #define PB14 2 | ||||
| #define PB15 3 | ||||
| #define PD8  4 | ||||
| #define PD9  5 | ||||
| #define PD10 6 | ||||
| #define PD11 7 | ||||
| #define PD12 8 | ||||
| #define PD13 9 | ||||
| #define PD14 10 | ||||
| #define PD15 11 | ||||
| #define PG2  12 | ||||
| #define PG3  13 | ||||
| #define PG4  14 | ||||
| #define PG5  15 | ||||
| #define PG6  16 | ||||
| #define PG7  17 | ||||
| #define PG8  18 | ||||
| #define PC6  19 | ||||
| #define PC7  20 | ||||
| #define PC8  21 | ||||
| #define PC9  22 | ||||
| #define PA8  23 | ||||
| #define PA9  24 | ||||
| #define PA10 25 | ||||
| #define PA11 26 // USB_DM | ||||
| #define PA12 27 // USB_DP | ||||
| #define PA13 28 | ||||
| #define PA14 29 | ||||
| #define PA15 30 | ||||
| #define PC10 31 | ||||
| #define PC11 32 | ||||
| #define PC12 33 | ||||
| #define PD0  34 | ||||
| #define PD1  35 | ||||
| #define PD2  36 | ||||
| #define PD3  37 | ||||
| #define PD4  38 | ||||
| #define PD5  39 | ||||
| #define PD6  40 | ||||
| #define PD7  41 | ||||
| #define PG9  42 | ||||
| #define PG10 43 | ||||
| #define PG11 44 | ||||
| #define PG12 45 | ||||
| #define PG13 46 | ||||
| #define PG14 47 | ||||
| #define PG15 48 | ||||
| #define PB3  49 | ||||
| #define PB4  50 | ||||
| #define PB5  51 | ||||
| #define PB6  52 | ||||
| #define PB7  53 | ||||
| #define PB8  54 | ||||
| #define PB9  55 | ||||
|  | ||||
| // Right Side | ||||
| #define PB10 56 | ||||
| #define PB11 57 | ||||
| #define PE14 58 | ||||
| #define PE15 59 | ||||
| #define PE12 60 | ||||
| #define PE13 61 | ||||
| #define PE10 62 | ||||
| #define PE11 63 | ||||
| #define PE8  64 | ||||
| #define PE9  65 | ||||
| #define PG1  66 | ||||
| #define PE7  67 | ||||
| #define PF15 68 | ||||
| #define PG0  69 | ||||
| #define PF13 70 | ||||
| #define PF14 71 | ||||
| #define PF11 72 | ||||
| #define PF12 73 | ||||
| #define PB2  74 | ||||
| #define PB1  75 // A0 | ||||
| #define PC5  76 // A1 | ||||
| #define PB0  77 // A2 | ||||
| #define PA7  78 // A3 | ||||
| #define PC4  79 // A4 | ||||
| #define PA5  80 // A5 | ||||
| #define PA6  81 // A6 | ||||
| #define PA3  82 // A7 | ||||
| #define PA4  83 // A8 | ||||
| #define PA1  84 // A9 | ||||
| #define PA2  85 // A10 | ||||
| #define PC3  86 // A11 | ||||
| #define PA0  87 // A12/PA_0(WK_UP): BUT K_UP) | ||||
| #define PC1  88 // A13 | ||||
| #define PC2  89 // A14 | ||||
| #define PC0  90 // A15 | ||||
| #define PF8  91 // A16 | ||||
| #define PF6  92 // A17 | ||||
| #define PF7  93 // A18 | ||||
| #define PF9  94 // LED D1 (active low) | ||||
| #define PF10 95 // LED D2 (active low) | ||||
| #define PF4  96 | ||||
| #define PF5  97 | ||||
| #define PF2  98 | ||||
| #define PF3  99 | ||||
| #define PF0  100 | ||||
| #define PF1  101 | ||||
| #define PE6  102 | ||||
| #define PC13 103 | ||||
| #define PE4  104 // BUT K0 | ||||
| #define PE5  105 // BUT K1 | ||||
| #define PE2  106 | ||||
| #define PE3  107 | ||||
| #define PE0  108 | ||||
| #define PE1  109 | ||||
| #define PC14  110 | ||||
| #define PC15  111 | ||||
| // This must be a literal | ||||
| #define NUM_DIGITAL_PINS        112 | ||||
| // This must be a literal with a value less than or equal to MAX_ANALOG_INPUTS | ||||
| #define NUM_ANALOG_INPUTS       23 | ||||
| #define NUM_ANALOG_FIRST        75 | ||||
|  | ||||
|  | ||||
| // Below SPI and I2C definitions already done in the core | ||||
| // Could be redefined here if differs from the default one | ||||
| // SPI Definitions | ||||
| #define PIN_SPI_SS              PF11 | ||||
| #define PIN_SPI_MOSI            PB15 | ||||
| #define PIN_SPI_MISO            PB14 | ||||
| #define PIN_SPI_SCK             PB13 | ||||
|  | ||||
|  | ||||
|  | ||||
| //max6675 | ||||
| //#define PIN_SPI_SS              PA4 | ||||
| //#define PIN_SPI_SCK             PA5 | ||||
| //#define PIN_SPI_MISO            PA6 | ||||
| //#define PIN_SPI_MOSI            PA7 | ||||
|  | ||||
|  | ||||
|  | ||||
|  | ||||
| // I2C Definitions | ||||
| #define PIN_WIRE_SDA            PB7 | ||||
| #define PIN_WIRE_SCL            PB6 | ||||
|  | ||||
| // Timer Definitions | ||||
| //Do not use timer used by PWM pins when possible. See PinMap_PWM in PeripheralPins.c | ||||
| #define TIMER_TONE              TIM6 | ||||
|  | ||||
| // Do not use basic timer: OC is required | ||||
| #define TIMER_SERVO             TIM1  //TODO: advanced-control timers don't work | ||||
|  | ||||
| // UART Definitions | ||||
| // Define here Serial instance number to map on Serial generic name | ||||
| #define SERIAL_UART_INSTANCE    1 //ex: 2 for Serial2 (USART2) | ||||
| // DEBUG_UART could be redefined to print on another instance than 'Serial' | ||||
| //#define DEBUG_UART              ((USART_TypeDef *) U(S)ARTX) // ex: USART3 | ||||
| // DEBUG_UART baudrate, default: 9600 if not defined | ||||
| //#define DEBUG_UART_BAUDRATE     x | ||||
| // DEBUG_UART Tx pin name, default: the first one found in PinMap_UART_TX for DEBUG_UART | ||||
| //#define DEBUG_PINNAME_TX        PX_n // PinName used for TX | ||||
|  | ||||
| // Default pin used for 'Serial' instance (ex: ST-Link) | ||||
| // Mandatory for Firmata | ||||
| #define PIN_SERIAL_RX           PA10 | ||||
| #define PIN_SERIAL_TX           PA9 | ||||
|  | ||||
| /* Extra HAL modules */ | ||||
| //#define HAL_DAC_MODULE_ENABLED | ||||
| #define HAL_SD_MODULE_ENABLED | ||||
|  | ||||
| #ifdef __cplusplus | ||||
| } // extern "C" | ||||
| #endif | ||||
| /*---------------------------------------------------------------------------- | ||||
|  *        Arduino objects - C++ only | ||||
|  *----------------------------------------------------------------------------*/ | ||||
|  | ||||
| #ifdef __cplusplus | ||||
| // These serial port names are intended to allow libraries and architecture-neutral | ||||
| // sketches to automatically default to the correct port name for a particular type | ||||
| // of use.  For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, | ||||
| // the first hardware serial port whose RX/TX pins are not dedicated to another use. | ||||
| // | ||||
| // SERIAL_PORT_MONITOR        Port which normally prints to the Arduino Serial Monitor | ||||
| // | ||||
| // SERIAL_PORT_USBVIRTUAL     Port which is USB virtual serial | ||||
| // | ||||
| // SERIAL_PORT_LINUXBRIDGE    Port which connects to a Linux system via Bridge library | ||||
| // | ||||
| // SERIAL_PORT_HARDWARE       Hardware serial port, physical RX & TX pins. | ||||
| // | ||||
| // SERIAL_PORT_HARDWARE_OPEN  Hardware serial ports which are open for use.  Their RX & TX | ||||
| //                            pins are NOT connected to anything by default. | ||||
| #define SERIAL_PORT_MONITOR     Serial | ||||
| #define SERIAL_PORT_HARDWARE    Serial1 | ||||
| #endif | ||||
|  | ||||
		Reference in New Issue
	
	Block a user