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[2.0.x] Enable hardware serial ports on LPC1768 (#8004)

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* Enable hardware serial ports on LPC1768

* Fix compilation errors with other HALs

* FIx order of includes in LPC1768 HAL main.cpp

* Add support for RX_BUFFER_SIZE and TX_BUFFER_SIZE options in Configuration_adv.h
This commit is contained in:
Thomas Moore
2017-10-24 17:28:33 -05:00
committed by Roxy-3D
parent 46aae4c6e7
commit 51fafccc16
21 changed files with 498 additions and 667 deletions
Download Patch File Download Diff File Expand all files Collapse all files

797
Marlin/src/HAL/HAL_LPC1768/HardwareSerial.cpp
View File

@ -22,313 +22,280 @@
#ifdef TARGET_LPC1768
#include "../../core/macros.h"
#include "../HAL.h"
#include "../../inc/MarlinConfig.h"
#include "HardwareSerial.h"
#define UART3 3
HardwareSerial Serial3 = HardwareSerial(UART3);
volatile uint32_t UART0Status, UART1Status, UART2Status, UART3Status;
volatile uint8_t UART0TxEmpty = 1, UART1TxEmpty = 1, UART2TxEmpty=1, UART3TxEmpty=1;
volatile uint8_t UART0Buffer[UARTRXQUEUESIZE], UART1Buffer[UARTRXQUEUESIZE], UART2Buffer[UARTRXQUEUESIZE], UART3Buffer[UARTRXQUEUESIZE];
volatile uint32_t UART0RxQueueWritePos = 0, UART1RxQueueWritePos = 0, UART2RxQueueWritePos = 0, UART3RxQueueWritePos = 0;
volatile uint32_t UART0RxQueueReadPos = 0, UART1RxQueueReadPos = 0, UART2RxQueueReadPos = 0, UART3RxQueueReadPos = 0;
volatile uint8_t dummy;
HardwareSerial Serial = HardwareSerial(LPC_UART0);
HardwareSerial Serial1 = HardwareSerial((LPC_UART_TypeDef *) LPC_UART1);
HardwareSerial Serial2 = HardwareSerial(LPC_UART2);
HardwareSerial Serial3 = HardwareSerial(LPC_UART3);
void HardwareSerial::begin(uint32_t baudrate) {
uint32_t Fdiv;
uint32_t pclkdiv, pclk;
void HardwareSerial::begin(uint32_t baudrate) {
if ( PortNum == 0 )
{
LPC_PINCON->PINSEL0 &= ~0x000000F0;
LPC_PINCON->PINSEL0 |= 0x00000050; /* RxD0 is P0.3 and TxD0 is P0.2 */
/* By default, the PCLKSELx value is zero, thus, the PCLK for
all the peripherals is 1/4 of the SystemFrequency. */
/* Bit 6~7 is for UART0 */
pclkdiv = (LPC_SC->PCLKSEL0 >> 6) & 0x03;
switch ( pclkdiv )
{
case 0x00:
default:
pclk = SystemCoreClock/4;
break;
case 0x01:
pclk = SystemCoreClock;
break;
case 0x02:
pclk = SystemCoreClock/2;
break;
case 0x03:
pclk = SystemCoreClock/8;
break;
}
UART_CFG_Type UARTConfigStruct;
PINSEL_CFG_Type PinCfg;
UART_FIFO_CFG_Type FIFOConfig;
LPC_UART0->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
Fdiv = ( pclk / 16 ) / baudrate ; /*baud rate */
LPC_UART0->DLM = Fdiv / 256;
LPC_UART0->DLL = Fdiv % 256;
LPC_UART0->LCR = 0x03; /* DLAB = 0 */
LPC_UART0->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
NVIC_EnableIRQ(UART0_IRQn);
LPC_UART0->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART0 interrupt */
}
else if ( PortNum == 1 )
{
LPC_PINCON->PINSEL4 &= ~0x0000000F;
LPC_PINCON->PINSEL4 |= 0x0000000A; /* Enable RxD1 P2.1, TxD1 P2.0 */
/* By default, the PCLKSELx value is zero, thus, the PCLK for
all the peripherals is 1/4 of the SystemFrequency. */
/* Bit 8,9 are for UART1 */
pclkdiv = (LPC_SC->PCLKSEL0 >> 8) & 0x03;
switch ( pclkdiv )
{
case 0x00:
default:
pclk = SystemCoreClock/4;
break;
case 0x01:
pclk = SystemCoreClock;
break;
case 0x02:
pclk = SystemCoreClock/2;
break;
case 0x03:
pclk = SystemCoreClock/8;
break;
}
LPC_UART1->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
Fdiv = ( pclk / 16 ) / baudrate ; /*baud rate */
LPC_UART1->DLM = Fdiv / 256;
LPC_UART1->DLL = Fdiv % 256;
LPC_UART1->LCR = 0x03; /* DLAB = 0 */
LPC_UART1->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
NVIC_EnableIRQ(UART1_IRQn);
LPC_UART1->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART1 interrupt */
}
else if ( PortNum == 2 )
{
//LPC_PINCON->PINSEL4 &= ~0x000F0000; /*Pinsel4 Bits 16-19*/
//LPC_PINCON->PINSEL4 |= 0x000A0000; /* RxD2 is P2.9 and TxD2 is P2.8, value 10*/
LPC_PINCON->PINSEL0 &= ~0x00F00000; /*Pinsel0 Bits 20-23*/
LPC_PINCON->PINSEL0 |= 0x00500000; /* RxD2 is P0.11 and TxD2 is P0.10, value 01*/
LPC_SC->PCONP |= 1<<24; //Enable PCUART2
/* By default, the PCLKSELx value is zero, thus, the PCLK for
all the peripherals is 1/4 of the SystemFrequency. */
/* Bit 6~7 is for UART3 */
pclkdiv = (LPC_SC->PCLKSEL1 >> 16) & 0x03;
switch ( pclkdiv )
{
case 0x00:
default:
pclk = SystemCoreClock/4;
break;
case 0x01:
pclk = SystemCoreClock;
break;
case 0x02:
pclk = SystemCoreClock/2;
break;
case 0x03:
pclk = SystemCoreClock/8;
break;
}
LPC_UART2->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
Fdiv = ( pclk / 16 ) / baudrate ; /*baud rate */
LPC_UART2->DLM = Fdiv / 256;
LPC_UART2->DLL = Fdiv % 256;
LPC_UART2->LCR = 0x03; /* DLAB = 0 */
LPC_UART2->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
NVIC_EnableIRQ(UART2_IRQn);
LPC_UART2->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART3 interrupt */
}
else if ( PortNum == 3 )
{
LPC_PINCON->PINSEL0 &= ~0x0000000F;
LPC_PINCON->PINSEL0 |= 0x0000000A; /* RxD3 is P0.1 and TxD3 is P0.0 */
LPC_SC->PCONP |= 1<<4 | 1<<25; //Enable PCUART1
/* By default, the PCLKSELx value is zero, thus, the PCLK for
all the peripherals is 1/4 of the SystemFrequency. */
/* Bit 6~7 is for UART3 */
pclkdiv = (LPC_SC->PCLKSEL1 >> 18) & 0x03;
switch ( pclkdiv )
{
case 0x00:
default:
pclk = SystemCoreClock/4;
break;
case 0x01:
pclk = SystemCoreClock;
break;
case 0x02:
pclk = SystemCoreClock/2;
break;
case 0x03:
pclk = SystemCoreClock/8;
break;
}
LPC_UART3->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
Fdiv = ( pclk / 16 ) / baudrate ; /*baud rate */
LPC_UART3->DLM = Fdiv / 256;
LPC_UART3->DLL = Fdiv % 256;
LPC_UART3->LCR = 0x03; /* DLAB = 0 */
LPC_UART3->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
NVIC_EnableIRQ(UART3_IRQn);
LPC_UART3->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART3 interrupt */
}
if (UARTx == LPC_UART0) {
/*
* Initialize UART0 pin connect
*/
PinCfg.Funcnum = 1;
PinCfg.OpenDrain = 0;
PinCfg.Pinmode = 0;
PinCfg.Pinnum = 2;
PinCfg.Portnum = 0;
PINSEL_ConfigPin(&PinCfg);
PinCfg.Pinnum = 3;
PINSEL_ConfigPin(&PinCfg);
}
else if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1) {
/*
* Initialize UART1 pin connect
*/
PinCfg.Funcnum = 1;
PinCfg.OpenDrain = 0;
PinCfg.Pinmode = 0;
PinCfg.Pinnum = 15;
PinCfg.Portnum = 0;
PINSEL_ConfigPin(&PinCfg);
PinCfg.Pinnum = 16;
PINSEL_ConfigPin(&PinCfg);
}
else if (UARTx == LPC_UART2) {
/*
* Initialize UART2 pin connect
*/
PinCfg.Funcnum = 1;
PinCfg.OpenDrain = 0;
PinCfg.Pinmode = 0;
PinCfg.Pinnum = 10;
PinCfg.Portnum = 0;
PINSEL_ConfigPin(&PinCfg);
PinCfg.Pinnum = 11;
PINSEL_ConfigPin(&PinCfg);
}
else if (UARTx == LPC_UART3) {
/*
* Initialize UART2 pin connect
*/
PinCfg.Funcnum = 1;
PinCfg.OpenDrain = 0;
PinCfg.Pinmode = 0;
PinCfg.Pinnum = 0;
PinCfg.Portnum = 0;
PINSEL_ConfigPin(&PinCfg);
PinCfg.Pinnum = 1;
PINSEL_ConfigPin(&PinCfg);
}
int HardwareSerial::read() {
uint8_t rx;
if ( PortNum == 0 )
{
if (UART0RxQueueReadPos == UART0RxQueueWritePos)
return -1;
/* Initialize UART Configuration parameter structure to default state:
* Baudrate = 9600bps
* 8 data bit
* 1 Stop bit
* None parity
*/
UART_ConfigStructInit(&UARTConfigStruct);
// Read from "head"
rx = UART0Buffer[UART0RxQueueReadPos]; // grab next byte
UART0RxQueueReadPos = (UART0RxQueueReadPos + 1) % UARTRXQUEUESIZE;
return rx;
}
if ( PortNum == 1 )
{
if (UART1RxQueueReadPos == UART1RxQueueWritePos)
return -1;
// Re-configure baudrate
UARTConfigStruct.Baud_rate = baudrate;
// Read from "head"
rx = UART1Buffer[UART1RxQueueReadPos]; // grab next byte
UART1RxQueueReadPos = (UART1RxQueueReadPos + 1) % UARTRXQUEUESIZE;
return rx;
}
if ( PortNum == 2 )
{
if (UART2RxQueueReadPos == UART2RxQueueWritePos)
return -1;
// Initialize eripheral with given to corresponding parameter
UART_Init(UARTx, &UARTConfigStruct);
// Enable and reset the TX and RX FIFOs
UART_FIFOConfigStructInit(&FIFOConfig);
UART_FIFOConfig(UARTx, &FIFOConfig);
// Read from "head"
rx = UART2Buffer[UART2RxQueueReadPos]; // grab next byte
UART2RxQueueReadPos = (UART2RxQueueReadPos + 1) % UARTRXQUEUESIZE;
return rx;
}
if ( PortNum == 3 )
{
if (UART3RxQueueReadPos == UART3RxQueueWritePos)
return -1;
// Enable UART Transmit
UART_TxCmd(UARTx, ENABLE);
// Read from "head"
rx = UART3Buffer[UART3RxQueueReadPos]; // grab next byte
UART3RxQueueReadPos = (UART3RxQueueReadPos + 1) % UARTRXQUEUESIZE;
return rx;
}
return 0;
// Configure Interrupts
UART_IntConfig(UARTx, UART_INTCFG_RBR, ENABLE);
UART_IntConfig(UARTx, UART_INTCFG_RLS, ENABLE);
if (UARTx == LPC_UART0)
NVIC_EnableIRQ(UART0_IRQn);
else if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1)
NVIC_EnableIRQ(UART1_IRQn);
else if (UARTx == LPC_UART2)
NVIC_EnableIRQ(UART2_IRQn);
else if (UARTx == LPC_UART3)
NVIC_EnableIRQ(UART3_IRQn);
RxQueueWritePos = RxQueueReadPos = 0;
#if TX_BUFFER_SIZE > 0
TxQueueWritePos = TxQueueReadPos = 0;
#endif
}
int HardwareSerial::peek() {
int byte = -1;
/* Temporarily lock out UART receive interrupts during this read so the UART receive
interrupt won't cause problems with the index values */
UART_IntConfig(UARTx, UART_INTCFG_RBR, DISABLE);
if (RxQueueReadPos != RxQueueWritePos)
byte = RxBuffer[RxQueueReadPos];
/* Re-enable UART interrupts */
UART_IntConfig(UARTx, UART_INTCFG_RBR, ENABLE);
return byte;
}
int HardwareSerial::read() {
int byte = -1;
/* Temporarily lock out UART receive interrupts during this read so the UART receive
interrupt won't cause problems with the index values */
UART_IntConfig(UARTx, UART_INTCFG_RBR, DISABLE);
if (RxQueueReadPos != RxQueueWritePos) {
byte = RxBuffer[RxQueueReadPos];
RxQueueReadPos = (RxQueueReadPos + 1) % RX_BUFFER_SIZE;
}
size_t HardwareSerial::write(uint8_t send) {
if ( PortNum == 0 )
{
/* THRE status, contain valid data */
while ( !(UART0TxEmpty & 0x01) );
LPC_UART0->THR = send;
UART0TxEmpty = 0; /* not empty in the THR until it shifts out */
}
else if (PortNum == 1)
{
/* THRE status, contain valid data */
while ( !(UART1TxEmpty & 0x01) );
LPC_UART1->THR = send;
UART1TxEmpty = 0; /* not empty in the THR until it shifts out */
}
else if ( PortNum == 2 )
{
/* THRE status, contain valid data */
while ( !(UART2TxEmpty & 0x01) );
LPC_UART2->THR = send;
UART2TxEmpty = 0; /* not empty in the THR until it shifts out */
}
else if ( PortNum == 3 )
{
/* THRE status, contain valid data */
while ( !(UART3TxEmpty & 0x01) );
LPC_UART3->THR = send;
UART3TxEmpty = 0; /* not empty in the THR until it shifts out */
}
return 0;
}
int HardwareSerial::available() {
if ( PortNum == 0 )
{
return (UART0RxQueueWritePos + UARTRXQUEUESIZE - UART0RxQueueReadPos) % UARTRXQUEUESIZE;
/* Re-enable UART interrupts */
UART_IntConfig(UARTx, UART_INTCFG_RBR, ENABLE);
return byte;
}
if ( PortNum == 1 )
{
return (UART1RxQueueWritePos + UARTRXQUEUESIZE - UART1RxQueueReadPos) % UARTRXQUEUESIZE;
}
if ( PortNum == 2 )
{
return (UART2RxQueueWritePos + UARTRXQUEUESIZE - UART2RxQueueReadPos) % UARTRXQUEUESIZE;
}
if ( PortNum == 3 )
{
return (UART3RxQueueWritePos + UARTRXQUEUESIZE - UART3RxQueueReadPos) % UARTRXQUEUESIZE;
}
return 0;
}
void HardwareSerial::flush() {
if ( PortNum == 0 )
{
UART0RxQueueWritePos = 0;
UART0RxQueueReadPos = 0;
size_t HardwareSerial::write(uint8_t send) {
#if TX_BUFFER_SIZE > 0
size_t bytes = 0;
uint32_t fifolvl = 0;
}
if ( PortNum == 1 )
{
UART1RxQueueWritePos = 0;
UART1RxQueueReadPos = 0;
}
if ( PortNum == 2 )
{
UART2RxQueueWritePos = 0;
UART2RxQueueReadPos = 0;
}
if ( PortNum == 3 )
{
UART3RxQueueWritePos = 0;
UART3RxQueueReadPos = 0;
}
return;
}
/* If the Tx Buffer is full, wait for space to clear */
if ((TxQueueWritePos+1) % TX_BUFFER_SIZE == TxQueueReadPos) flushTX();
/* Temporarily lock out UART transmit interrupts during this read so the UART transmit interrupt won't
cause problems with the index values */
UART_IntConfig(UARTx, UART_INTCFG_THRE, DISABLE);
void HardwareSerial::printf(const char *format, ...) {
static char buffer[256];
va_list vArgs;
va_start(vArgs, format);
int length = vsnprintf((char *) buffer, 256, (char const *) format, vArgs);
va_end(vArgs);
if (length > 0 && length < 256) {
for (int i = 0; i < length;) {
write(buffer[i]);
++i;
}
}
/* LPC17xx.h incorrectly defines FIFOLVL as a uint8_t, when it's actually a 32-bit register */
if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1)
fifolvl = *(reinterpret_cast<volatile uint32_t *>(&((LPC_UART1_TypeDef *) UARTx)->FIFOLVL));
else
fifolvl = *(reinterpret_cast<volatile uint32_t *>(&UARTx->FIFOLVL));
/* If the queue is empty and there's space in the FIFO, immediately send the byte */
if (TxQueueWritePos == TxQueueReadPos && fifolvl < UART_TX_FIFO_SIZE) {
bytes = UART_Send(UARTx, &send, 1, BLOCKING);
}
/* Otherwiise, write the byte to the transmit buffer */
else if ((TxQueueWritePos+1) % TX_BUFFER_SIZE != TxQueueReadPos) {
TxBuffer[TxQueueWritePos] = send;
TxQueueWritePos = (TxQueueWritePos+1) % TX_BUFFER_SIZE;
bytes++;
}
/* Re-enable the TX Interrupt */
UART_IntConfig(UARTx, UART_INTCFG_THRE, ENABLE);
return bytes;
#else
return UART_Send(UARTx, &send, 1, BLOCKING);
#endif
}
#if TX_BUFFER_SIZE > 0
void HardwareSerial::flushTX() {
/* Wait for the tx buffer and FIFO to drain */
while (TxQueueWritePos != TxQueueReadPos && UART_CheckBusy(UARTx) == SET);
}
#endif
int HardwareSerial::available() {
return (RxQueueWritePos + RX_BUFFER_SIZE - RxQueueReadPos) % RX_BUFFER_SIZE;
}
void HardwareSerial::flush() {
RxQueueWritePos = 0;
RxQueueReadPos = 0;
}
void HardwareSerial::printf(const char *format, ...) {
char RxBuffer[256];
va_list vArgs;
va_start(vArgs, format);
int length = vsnprintf(RxBuffer, 256, format, vArgs);
va_end(vArgs);
if (length > 0 && length < 256) {
for (int i = 0; i < length; ++i)
write(RxBuffer[i]);
}
}
void HardwareSerial::IRQHandler() {
uint32_t IIRValue;
uint8_t LSRValue, byte;
IIRValue = UART_GetIntId(UARTx);
IIRValue &= UART_IIR_INTID_MASK; /* check bit 1~3, interrupt identification */
if ( IIRValue == UART_IIR_INTID_RLS ) /* Receive Line Status */
{
LSRValue = UART_GetLineStatus(UARTx);
/* Receive Line Status */
if ( LSRValue & (UART_LSR_OE|UART_LSR_PE|UART_LSR_FE|UART_LSR_RXFE|UART_LSR_BI) )
{
/* There are errors or break interrupt */
/* Read LSR will clear the interrupt */
Status = LSRValue;
byte = UART_ReceiveByte(UARTx); /* Dummy read on RX to clear
interrupt, then bail out */
return;
}
}
if ( IIRValue == UART_IIR_INTID_RDA ) /* Receive Data Available */
{
/* Clear the FIFO */
while ( UART_Receive(UARTx, &byte, 1, NONE_BLOCKING) ) {
if ((RxQueueWritePos+1) % RX_BUFFER_SIZE != RxQueueReadPos)
{
RxBuffer[RxQueueWritePos] = byte;
RxQueueWritePos = (RxQueueWritePos+1) % RX_BUFFER_SIZE;
}
else
break;
}
}
else if ( IIRValue == UART_IIR_INTID_CTI ) /* Character timeout indicator */
{
/* Character Time-out indicator */
Status |= 0x100; /* Bit 9 as the CTI error */
}
#if TX_BUFFER_SIZE > 0
if (IIRValue == UART_IIR_INTID_THRE) {
/* Disable THRE interrupt */
UART_IntConfig(UARTx, UART_INTCFG_THRE, DISABLE);
/* Wait for FIFO buffer empty */
while (UART_CheckBusy(UARTx) == SET);
/* Transfer up to UART_TX_FIFO_SIZE bytes of data */
for (int i = 0; i < UART_TX_FIFO_SIZE && TxQueueWritePos != TxQueueReadPos; i++) {
/* Move a piece of data into the transmit FIFO */
if (UART_Send(UARTx, &TxBuffer[TxQueueReadPos], 1, NONE_BLOCKING))
TxQueueReadPos = (TxQueueReadPos+1) % TX_BUFFER_SIZE;
else
break;
}
/* If there is no more data to send, disable the transmit interrupt - else enable it or keep it enabled */
if (TxQueueWritePos == TxQueueReadPos)
UART_IntConfig(UARTx, UART_INTCFG_THRE, DISABLE);
else
UART_IntConfig(UARTx, UART_INTCFG_THRE, ENABLE);
}
#endif
}
#ifdef __cplusplus
extern "C" {
@ -345,68 +312,7 @@ extern "C" {
*****************************************************************************/
void UART0_IRQHandler (void)
{
uint8_t IIRValue, LSRValue;
IIRValue = LPC_UART0->IIR;
IIRValue >>= 1; /* skip pending bit in IIR */
IIRValue &= 0x07; /* check bit 1~3, interrupt identification */
if ( IIRValue == IIR_RLS ) /* Receive Line Status */
{
LSRValue = LPC_UART0->LSR;
/* Receive Line Status */
if ( LSRValue & (LSR_OE|LSR_PE|LSR_FE|LSR_RXFE|LSR_BI) )
{
/* There are errors or break interrupt */
/* Read LSR will clear the interrupt */
UART0Status = LSRValue;
dummy = LPC_UART0->RBR; /* Dummy read on RX to clear
interrupt, then bail out */
return;
}
if ( LSRValue & LSR_RDR ) /* Receive Data Ready */
{
/* If no error on RLS, normal ready, save into the data buffer. */
/* Note: read RBR will clear the interrupt */
if ((UART0RxQueueWritePos+1) % UARTRXQUEUESIZE != UART0RxQueueReadPos)
{
UART0Buffer[UART0RxQueueWritePos] = LPC_UART0->RBR;
UART0RxQueueWritePos = (UART0RxQueueWritePos+1) % UARTRXQUEUESIZE;
}
else
dummy = LPC_UART0->RBR;
}
}
else if ( IIRValue == IIR_RDA ) /* Receive Data Available */
{
/* Receive Data Available */
if ((UART0RxQueueWritePos+1) % UARTRXQUEUESIZE != UART0RxQueueReadPos)
{
UART0Buffer[UART0RxQueueWritePos] = LPC_UART0->RBR;
UART0RxQueueWritePos = (UART0RxQueueWritePos+1) % UARTRXQUEUESIZE;
}
else
dummy = LPC_UART1->RBR;
}
else if ( IIRValue == IIR_CTI ) /* Character timeout indicator */
{
/* Character Time-out indicator */
UART0Status |= 0x100; /* Bit 9 as the CTI error */
}
else if ( IIRValue == IIR_THRE ) /* THRE, transmit holding register empty */
{
/* THRE interrupt */
LSRValue = LPC_UART0->LSR; /* Check status in the LSR to see if
valid data in U0THR or not */
if ( LSRValue & LSR_THRE )
{
UART0TxEmpty = 1;
}
else
{
UART0TxEmpty = 0;
}
}
Serial.IRQHandler();
}
/*****************************************************************************
@ -420,69 +326,9 @@ void UART0_IRQHandler (void)
*****************************************************************************/
void UART1_IRQHandler (void)
{
uint8_t IIRValue, LSRValue;
IIRValue = LPC_UART1->IIR;
IIRValue >>= 1; /* skip pending bit in IIR */
IIRValue &= 0x07; /* check bit 1~3, interrupt identification */
if ( IIRValue == IIR_RLS ) /* Receive Line Status */
{
LSRValue = LPC_UART1->LSR;
/* Receive Line Status */
if ( LSRValue & (LSR_OE|LSR_PE|LSR_FE|LSR_RXFE|LSR_BI) )
{
/* There are errors or break interrupt */
/* Read LSR will clear the interrupt */
UART1Status = LSRValue;
dummy = LPC_UART1->RBR; /* Dummy read on RX to clear
interrupt, then bail out */
return;
}
if ( LSRValue & LSR_RDR ) /* Receive Data Ready */
{
/* If no error on RLS, normal ready, save into the data buffer. */
/* Note: read RBR will clear the interrupt */
if ((UART1RxQueueWritePos+1) % UARTRXQUEUESIZE != UART1RxQueueReadPos)
{
UART1Buffer[UART1RxQueueWritePos] = LPC_UART1->RBR;
UART1RxQueueWritePos =(UART1RxQueueWritePos+1) % UARTRXQUEUESIZE;
}
else
dummy = LPC_UART1->RBR;
}
}
else if ( IIRValue == IIR_RDA ) /* Receive Data Available */
{
/* Receive Data Available */
if ((UART1RxQueueWritePos+1) % UARTRXQUEUESIZE != UART1RxQueueReadPos)
{
UART1Buffer[UART1RxQueueWritePos] = LPC_UART1->RBR;
UART1RxQueueWritePos = (UART1RxQueueWritePos+1) % UARTRXQUEUESIZE;
}
else
dummy = LPC_UART1->RBR;
}
else if ( IIRValue == IIR_CTI ) /* Character timeout indicator */
{
/* Character Time-out indicator */
UART1Status |= 0x100; /* Bit 9 as the CTI error */
}
else if ( IIRValue == IIR_THRE ) /* THRE, transmit holding register empty */
{
/* THRE interrupt */
LSRValue = LPC_UART1->LSR; /* Check status in the LSR to see if
valid data in U0THR or not */
if ( LSRValue & LSR_THRE )
{
UART1TxEmpty = 1;
}
else
{
UART1TxEmpty = 0;
}
}
Serial1.IRQHandler();
}
/*****************************************************************************
** Function name: UART2_IRQHandler
**
@ -494,71 +340,13 @@ void UART1_IRQHandler (void)
*****************************************************************************/
void UART2_IRQHandler (void)
{
uint8_t IIRValue, LSRValue;
IIRValue = LPC_UART2->IIR;
IIRValue >>= 1; /* skip pending bit in IIR */
IIRValue &= 0x07; /* check bit 1~3, interrupt identification */
if ( IIRValue == IIR_RLS ) /* Receive Line Status */
{
LSRValue = LPC_UART2->LSR;
/* Receive Line Status */
if ( LSRValue & (LSR_OE|LSR_PE|LSR_FE|LSR_RXFE|LSR_BI) )
{
/* There are errors or break interrupt */
/* Read LSR will clear the interrupt */
UART2Status = LSRValue;
dummy = LPC_UART2->RBR; /* Dummy read on RX to clear
interrupt, then bail out */
return;
}
if ( LSRValue & LSR_RDR ) /* Receive Data Ready */
{
/* If no error on RLS, normal ready, save into the data buffer. */
/* Note: read RBR will clear the interrupt */
if ((UART2RxQueueWritePos+1) % UARTRXQUEUESIZE != UART2RxQueueReadPos)
{
UART2Buffer[UART2RxQueueWritePos] = LPC_UART2->RBR;
UART2RxQueueWritePos = (UART2RxQueueWritePos+1) % UARTRXQUEUESIZE;
}
}
}
else if ( IIRValue == IIR_RDA ) /* Receive Data Available */
{
/* Receive Data Available */
if ((UART2RxQueueWritePos+1) % UARTRXQUEUESIZE != UART2RxQueueReadPos)
{
UART2Buffer[UART2RxQueueWritePos] = LPC_UART2->RBR;
UART2RxQueueWritePos = (UART2RxQueueWritePos+1) % UARTRXQUEUESIZE;
}
else
dummy = LPC_UART2->RBR;
}
else if ( IIRValue == IIR_CTI ) /* Character timeout indicator */
{
/* Character Time-out indicator */
UART2Status |= 0x100; /* Bit 9 as the CTI error */
}
else if ( IIRValue == IIR_THRE ) /* THRE, transmit holding register empty */
{
/* THRE interrupt */
LSRValue = LPC_UART2->LSR; /* Check status in the LSR to see if
valid data in U0THR or not */
if ( LSRValue & LSR_THRE )
{
UART2TxEmpty = 1;
}
else
{
UART2TxEmpty = 0;
}
}
Serial2.IRQHandler();
}
/*****************************************************************************
** Function name: UART3_IRQHandler
**
** Descriptions: UART0 interrupt handler
** Descriptions: UART3 interrupt handler
**
** parameters: None
** Returned value: None
@ -566,66 +354,7 @@ void UART2_IRQHandler (void)
*****************************************************************************/
void UART3_IRQHandler (void)
{
uint8_t IIRValue, LSRValue;
IIRValue = LPC_UART3->IIR;
IIRValue >>= 1; /* skip pending bit in IIR */
IIRValue &= 0x07; /* check bit 1~3, interrupt identification */
if ( IIRValue == IIR_RLS ) /* Receive Line Status */
{
LSRValue = LPC_UART3->LSR;
/* Receive Line Status */
if ( LSRValue & (LSR_OE|LSR_PE|LSR_FE|LSR_RXFE|LSR_BI) )
{
/* There are errors or break interrupt */
/* Read LSR will clear the interrupt */
UART3Status = LSRValue;
dummy = LPC_UART3->RBR; /* Dummy read on RX to clear
interrupt, then bail out */
return;
}
if ( LSRValue & LSR_RDR ) /* Receive Data Ready */
{
/* If no error on RLS, normal ready, save into the data buffer. */
/* Note: read RBR will clear the interrupt */
if ((UART3RxQueueWritePos+1) % UARTRXQUEUESIZE != UART3RxQueueReadPos)
{
UART3Buffer[UART3RxQueueWritePos] = LPC_UART3->RBR;
UART3RxQueueWritePos = (UART3RxQueueWritePos+1) % UARTRXQUEUESIZE;
}
}
}
else if ( IIRValue == IIR_RDA ) /* Receive Data Available */
{
/* Receive Data Available */
if ((UART3RxQueueWritePos+1) % UARTRXQUEUESIZE != UART3RxQueueReadPos)
{
UART3Buffer[UART3RxQueueWritePos] = LPC_UART3->RBR;
UART3RxQueueWritePos = (UART3RxQueueWritePos+1) % UARTRXQUEUESIZE;
}
else
dummy = LPC_UART3->RBR;
}
else if ( IIRValue == IIR_CTI ) /* Character timeout indicator */
{
/* Character Time-out indicator */
UART3Status |= 0x100; /* Bit 9 as the CTI error */
}
else if ( IIRValue == IIR_THRE ) /* THRE, transmit holding register empty */
{
/* THRE interrupt */
LSRValue = LPC_UART3->LSR; /* Check status in the LSR to see if
valid data in U0THR or not */
if ( LSRValue & LSR_THRE )
{
UART3TxEmpty = 1;
}
else
{
UART3TxEmpty = 0;
}
}
Serial3.IRQHandler();
}
#ifdef __cplusplus