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HAL support for 8s watchdog

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This commit is contained in:
Scott Lahteine
2020-11-04 15:08:31 -06:00
parent 2a78fe0f81
commit 4fe1adc383
14 changed files with 82 additions and 73 deletions
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34
Marlin/src/HAL/SAMD51/watchdog.cpp
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@ -24,28 +24,30 @@
#if ENABLED(USE_WATCHDOG)
#include "watchdog.h"
#include "watchdog.h"
void watchdog_init() {
// The low-power oscillator used by the WDT runs at 32,768 Hz with
// a 1:32 prescale, thus 1024 Hz, though probably not super precise.
#define WDT_TIMEOUT_REG TERN(WATCHDOG_DURATION_8S, WDT_CONFIG_PER_CYC8192, WDT_CONFIG_PER_CYC4096) // 4 or 8 second timeout
// Setup WDT clocks
MCLK->APBAMASK.bit.OSC32KCTRL_ = true;
MCLK->APBAMASK.bit.WDT_ = true;
OSC32KCTRL->OSCULP32K.bit.EN1K = true; // Enable out 1K (this is what WDT uses)
void watchdog_init() {
// The low-power oscillator used by the WDT runs at 32,768 Hz with
// a 1:32 prescale, thus 1024 Hz, though probably not super precise.
WDT->CTRLA.bit.ENABLE = false; // Disable watchdog for config
SYNC(WDT->SYNCBUSY.bit.ENABLE);
// Setup WDT clocks
MCLK->APBAMASK.bit.OSC32KCTRL_ = true;
MCLK->APBAMASK.bit.WDT_ = true;
OSC32KCTRL->OSCULP32K.bit.EN1K = true; // Enable out 1K (this is what WDT uses)
WDT->INTENCLR.reg = WDT_INTENCLR_EW; // Disable early warning interrupt
WDT->CONFIG.reg = WDT_CONFIG_PER_CYC4096; // Set at least 4s period for chip reset
WDT->CTRLA.bit.ENABLE = false; // Disable watchdog for config
SYNC(WDT->SYNCBUSY.bit.ENABLE);
HAL_watchdog_refresh();
WDT->INTENCLR.reg = WDT_INTENCLR_EW; // Disable early warning interrupt
WDT->CONFIG.reg = WDT_TIMEOUT_REG; // Set a 4s or 8s period for chip reset
WDT->CTRLA.reg = WDT_CTRLA_ENABLE; // Start watchdog now in normal mode
SYNC(WDT->SYNCBUSY.bit.ENABLE);
}
HAL_watchdog_refresh();
WDT->CTRLA.reg = WDT_CTRLA_ENABLE; // Start watchdog now in normal mode
SYNC(WDT->SYNCBUSY.bit.ENABLE);
}
#endif // USE_WATCHDOG