Moved CMSIS and other LPC1768 dependencies
Fixes Arduino IDE builds for 8-bit AVR, misc: Adafruit NeoPixel currently incompatible with Teensy 3.5-6, blacklisted
This commit is contained in:
Christopher Pepper
committed by
Scott Lahteine
Scott Lahteine
parent
b55295ad33
commit
4183a249b6
180
Marlin/frameworks/CMSIS/LPC1768/Re-ARM/LPC1768.ld
Normal file
180
Marlin/frameworks/CMSIS/LPC1768/Re-ARM/LPC1768.ld
Normal file
@ -0,0 +1,180 @@
|
||||
/* Linker script for mbed LPC1768 */
|
||||
MEMORY
|
||||
{
|
||||
//FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
|
||||
FLASH (rx) : ORIGIN = 16K, LENGTH = (512K - 16K)
|
||||
RAM (rwx) : ORIGIN = 0x100000C8, LENGTH = (32K - 0xC8)
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||||
|
||||
USB_RAM(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K
|
||||
ETH_RAM(rwx) : ORIGIN = 0x20080000, LENGTH = 16K
|
||||
}
|
||||
|
||||
/* Linker script to place sections and symbol values. Should be used together
|
||||
* with other linker script that defines memory regions FLASH and RAM.
|
||||
* It references following symbols, which must be defined in code:
|
||||
* Reset_Handler : Entry of reset handler
|
||||
*
|
||||
* It defines following symbols, which code can use without definition:
|
||||
* __exidx_start
|
||||
* __exidx_end
|
||||
* __etext
|
||||
* __data_start__
|
||||
* __preinit_array_start
|
||||
* __preinit_array_end
|
||||
* __init_array_start
|
||||
* __init_array_end
|
||||
* __fini_array_start
|
||||
* __fini_array_end
|
||||
* __data_end__
|
||||
* __bss_start__
|
||||
* __bss_end__
|
||||
* __end__
|
||||
* end
|
||||
* __HeapLimit
|
||||
* __StackLimit
|
||||
* __StackTop
|
||||
* __stack
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||||
*/
|
||||
ENTRY(Reset_Handler)
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||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
KEEP(*(.isr_vector))
|
||||
*(.text*)
|
||||
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
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||||
*(.dtors)
|
||||
|
||||
*(.rodata*)
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||||
|
||||
KEEP(*(.eh_frame*))
|
||||
} > FLASH
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||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > FLASH
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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||||
} > FLASH
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||||
__exidx_end = .;
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||||
|
||||
__etext = .;
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||||
|
||||
.data : AT (__etext)
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||||
{
|
||||
__data_start__ = .;
|
||||
Image$$RW_IRAM1$$Base = .;
|
||||
*(vtable)
|
||||
*(.data*)
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||||
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE (__preinit_array_start = .);
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||||
KEEP(*(.preinit_array))
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||||
PROVIDE (__preinit_array_end = .);
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|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE (__init_array_start = .);
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||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE (__init_array_end = .);
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||||
|
||||
|
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. = ALIGN(4);
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||||
/* finit data */
|
||||
PROVIDE (__fini_array_start = .);
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||||
KEEP(*(SORT(.fini_array.*)))
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||||
KEEP(*(.fini_array))
|
||||
PROVIDE (__fini_array_end = .);
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||||
|
||||
. = ALIGN(4);
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||||
/* All data end */
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__data_end__ = .;
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||||
|
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} > RAM
|
||||
|
||||
.bss :
|
||||
{
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
__bss_end__ = .;
|
||||
Image$$RW_IRAM1$$ZI$$Limit = . ;
|
||||
} > RAM
|
||||
|
||||
.heap :
|
||||
{
|
||||
__end__ = .;
|
||||
end = __end__;
|
||||
*(.heap*)
|
||||
__HeapLimit = .;
|
||||
} > RAM
|
||||
|
||||
/* .stack_dummy section doesn't contains any symbols. It is only
|
||||
* used for linker to calculate size of stack sections, and assign
|
||||
* values to stack symbols later */
|
||||
.stack_dummy :
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||||
{
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*(.stack)
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||||
} > RAM
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||||
|
||||
/* Set stack top to end of RAM, and stack limit move down by
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* size of stack_dummy section */
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||||
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
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__StackLimit = __StackTop - SIZEOF(.stack_dummy);
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PROVIDE(__stack = __StackTop);
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PROVIDE(__heapLimit = __HeapLimit);
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||||
PROVIDE(__stackSize = __StackTop - __HeapLimit);
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||||
|
||||
/* Area of memory, heap and stack, to fill on startup - 8 bytes at a time. */
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__FillStart = ALIGN(__end__, 8);
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||||
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||||
/* Check if data + heap + stack exceeds RAM limit */
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||||
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
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||||
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||||
|
||||
/* Code can explicitly ask for data to be
|
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placed in these higher RAM banks where
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||||
they will be left uninitialized.
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||||
*/
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||||
.AHBSRAM0 (NOLOAD):
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||||
{
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||||
Image$$RW_IRAM2$$Base = . ;
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PROVIDE(__AHB0_block_start = .);
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||||
*(AHBSRAM0)
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Image$$RW_IRAM2$$ZI$$Limit = .;
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PROVIDE(__AHB0_dyn_start = .);
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PROVIDE(__AHB0_end = ORIGIN(USB_RAM) + LENGTH(USB_RAM));
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} > USB_RAM
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||||
|
||||
.AHBSRAM1 (NOLOAD):
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||||
{
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||||
Image$$RW_IRAM3$$Base = . ;
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||||
PROVIDE(__AHB1_block_start = .);
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||||
*(AHBSRAM1)
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||||
Image$$RW_IRAM3$$ZI$$Limit = .;
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||||
PROVIDE(__AHB1_dyn_start = .);
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PROVIDE(__AHB1_end = ORIGIN(ETH_RAM) + LENGTH(ETH_RAM));
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} > ETH_RAM
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}
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221
Marlin/frameworks/CMSIS/LPC1768/Re-ARM/startup_LPC17xx.S
Normal file
221
Marlin/frameworks/CMSIS/LPC1768/Re-ARM/startup_LPC17xx.S
Normal file
@ -0,0 +1,221 @@
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||||
/* File: startup_ARMCM3.s
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* Purpose: startup file for Cortex-M3/M4 devices. Should use with
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* GNU Tools for ARM Embedded Processors
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* Version: V1.1
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* Date: 17 June 2011
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*
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* Copyright (C) 2011 ARM Limited. All rights reserved.
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* ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4
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* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*/
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.syntax unified
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.arch armv7-m
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/* Memory Model
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The HEAP starts at the end of the DATA section and grows upward.
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The STACK starts at the end of the RAM and grows downward.
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The HEAP and stack STACK are only checked at compile time:
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(DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
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This is just a check for the bare minimum for the Heap+Stack area before
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aborting compilation, it is not the run time limit:
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Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
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*/
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.section .stack
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.align 3
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#ifdef __STACK_SIZE
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.equ Stack_Size, __STACK_SIZE
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#else
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.equ Stack_Size, 0xc00
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#endif
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.globl __StackTop
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.globl __StackLimit
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__StackLimit:
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.space Stack_Size
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.size __StackLimit, . - __StackLimit
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__StackTop:
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.size __StackTop, . - __StackTop
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.section .heap
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.align 3
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#ifdef __HEAP_SIZE
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.equ Heap_Size, __HEAP_SIZE
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#else
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.equ Heap_Size, 0x800
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#endif
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.globl __HeapBase
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.globl __HeapLimit
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__HeapBase:
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.space Heap_Size
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.size __HeapBase, . - __HeapBase
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__HeapLimit:
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.size __HeapLimit, . - __HeapLimit
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.section .isr_vector
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.align 2
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.globl __isr_vector
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__isr_vector:
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.long __StackTop /* Top of Stack */
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.long Reset_Handler /* Reset Handler */
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.long NMI_Handler /* NMI Handler */
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.long HardFault_Handler /* Hard Fault Handler */
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.long MemManage_Handler /* MPU Fault Handler */
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.long BusFault_Handler /* Bus Fault Handler */
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.long UsageFault_Handler /* Usage Fault Handler */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long SVC_Handler /* SVCall Handler */
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.long DebugMon_Handler /* Debug Monitor Handler */
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.long 0 /* Reserved */
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.long PendSV_Handler /* PendSV Handler */
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.long SysTick_Handler /* SysTick Handler */
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/* External interrupts */
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.long WDT_IRQHandler /* 16: Watchdog Timer */
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.long TIMER0_IRQHandler /* 17: Timer0 */
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.long TIMER1_IRQHandler /* 18: Timer1 */
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.long TIMER2_IRQHandler /* 19: Timer2 */
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.long TIMER3_IRQHandler /* 20: Timer3 */
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.long UART0_IRQHandler /* 21: UART0 */
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.long UART1_IRQHandler /* 22: UART1 */
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.long UART2_IRQHandler /* 23: UART2 */
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||||
.long UART3_IRQHandler /* 24: UART3 */
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||||
.long PWM1_IRQHandler /* 25: PWM1 */
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.long I2C0_IRQHandler /* 26: I2C0 */
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.long I2C1_IRQHandler /* 27: I2C1 */
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||||
.long I2C2_IRQHandler /* 28: I2C2 */
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.long SPI_IRQHandler /* 29: SPI */
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.long SSP0_IRQHandler /* 30: SSP0 */
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.long SSP1_IRQHandler /* 31: SSP1 */
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||||
.long PLL0_IRQHandler /* 32: PLL0 Lock (Main PLL) */
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||||
.long RTC_IRQHandler /* 33: Real Time Clock */
|
||||
.long EINT0_IRQHandler /* 34: External Interrupt 0 */
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||||
.long EINT1_IRQHandler /* 35: External Interrupt 1 */
|
||||
.long EINT2_IRQHandler /* 36: External Interrupt 2 */
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||||
.long EINT3_IRQHandler /* 37: External Interrupt 3 */
|
||||
.long ADC_IRQHandler /* 38: A/D Converter */
|
||||
.long BOD_IRQHandler /* 39: Brown-Out Detect */
|
||||
.long USB_IRQHandler /* 40: USB */
|
||||
.long CAN_IRQHandler /* 41: CAN */
|
||||
.long DMA_IRQHandler /* 42: General Purpose DMA */
|
||||
.long I2S_IRQHandler /* 43: I2S */
|
||||
.long ENET_IRQHandler /* 44: Ethernet */
|
||||
.long RIT_IRQHandler /* 45: Repetitive Interrupt Timer */
|
||||
.long MCPWM_IRQHandler /* 46: Motor Control PWM */
|
||||
.long QEI_IRQHandler /* 47: Quadrature Encoder Interface */
|
||||
.long PLL1_IRQHandler /* 48: PLL1 Lock (USB PLL) */
|
||||
.long USBActivity_IRQHandler /* 49: USB Activity */
|
||||
.long CANActivity_IRQHandler /* 50: CAN Activity */
|
||||
|
||||
.size __isr_vector, . - __isr_vector
|
||||
|
||||
.text
|
||||
.thumb
|
||||
.thumb_func
|
||||
.align 2
|
||||
.globl Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
/* Loop to copy data from read only memory to RAM. The ranges
|
||||
* of copy from/to are specified by following symbols evaluated in
|
||||
* linker script.
|
||||
* _etext: End of code section, i.e., begin of data sections to copy from.
|
||||
* __data_start__/__data_end__: RAM address range that data should be
|
||||
* copied to. Both must be aligned to 4 bytes boundary. */
|
||||
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__data_end__
|
||||
|
||||
.flash_to_ram_loop:
|
||||
cmp r2, r3
|
||||
ittt lt
|
||||
ldrlt r0, [r1], #4
|
||||
strlt r0, [r2], #4
|
||||
blt .flash_to_ram_loop
|
||||
|
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ldr r0, =SystemInit
|
||||
blx r0
|
||||
ldr r0, =SystemPostInit
|
||||
blx r0
|
||||
ldr r0, =_start
|
||||
bx r0
|
||||
.pool
|
||||
.size Reset_Handler, . - Reset_Handler
|
||||
|
||||
/* Macro to define default handlers. Default handler
|
||||
* will be weak symbol and just dead loops. They can be
|
||||
* overwritten by other handlers */
|
||||
.macro def_default_handler handler_name
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak \handler_name
|
||||
.type \handler_name, %function
|
||||
\handler_name :
|
||||
b .
|
||||
.size \handler_name, . - \handler_name
|
||||
.endm
|
||||
|
||||
def_default_handler NMI_Handler
|
||||
def_default_handler HardFault_Handler
|
||||
def_default_handler MemManage_Handler
|
||||
def_default_handler BusFault_Handler
|
||||
def_default_handler UsageFault_Handler
|
||||
def_default_handler SVC_Handler
|
||||
def_default_handler DebugMon_Handler
|
||||
def_default_handler PendSV_Handler
|
||||
def_default_handler SysTick_Handler
|
||||
def_default_handler Default_Handler
|
||||
|
||||
def_default_handler WDT_IRQHandler
|
||||
def_default_handler TIMER0_IRQHandler
|
||||
def_default_handler TIMER1_IRQHandler
|
||||
def_default_handler TIMER2_IRQHandler
|
||||
def_default_handler TIMER3_IRQHandler
|
||||
def_default_handler UART0_IRQHandler
|
||||
def_default_handler UART1_IRQHandler
|
||||
def_default_handler UART2_IRQHandler
|
||||
def_default_handler UART3_IRQHandler
|
||||
def_default_handler PWM1_IRQHandler
|
||||
def_default_handler I2C0_IRQHandler
|
||||
def_default_handler I2C1_IRQHandler
|
||||
def_default_handler I2C2_IRQHandler
|
||||
def_default_handler SPI_IRQHandler
|
||||
def_default_handler SSP0_IRQHandler
|
||||
def_default_handler SSP1_IRQHandler
|
||||
def_default_handler PLL0_IRQHandler
|
||||
def_default_handler RTC_IRQHandler
|
||||
def_default_handler EINT0_IRQHandler
|
||||
def_default_handler EINT1_IRQHandler
|
||||
def_default_handler EINT2_IRQHandler
|
||||
def_default_handler EINT3_IRQHandler
|
||||
def_default_handler ADC_IRQHandler
|
||||
def_default_handler BOD_IRQHandler
|
||||
def_default_handler USB_IRQHandler
|
||||
def_default_handler CAN_IRQHandler
|
||||
def_default_handler DMA_IRQHandler
|
||||
def_default_handler I2S_IRQHandler
|
||||
def_default_handler ENET_IRQHandler
|
||||
def_default_handler RIT_IRQHandler
|
||||
def_default_handler MCPWM_IRQHandler
|
||||
def_default_handler QEI_IRQHandler
|
||||
def_default_handler PLL1_IRQHandler
|
||||
def_default_handler USBActivity_IRQHandler
|
||||
def_default_handler CANActivity_IRQHandler
|
||||
|
||||
.weak DEF_IRQHandler
|
||||
.set DEF_IRQHandler, Default_Handler
|
||||
|
||||
.end
|
||||
|
||||
611
Marlin/frameworks/CMSIS/LPC1768/Re-ARM/system_LPC17xx.c
Normal file
611
Marlin/frameworks/CMSIS/LPC1768/Re-ARM/system_LPC17xx.c
Normal file
@ -0,0 +1,611 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_LPC17xx.c
|
||||
* @brief CMSIS Cortex-M3 Device System Source File for
|
||||
* NXP LPC17xx Device Series
|
||||
* @version V1.11
|
||||
* @date 21. June 2011
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#include "LPC17xx.h"
|
||||
|
||||
|
||||
/** @addtogroup LPC17xx_System
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
*/
|
||||
|
||||
/*--------------------- Clock Configuration ----------------------------------
|
||||
//
|
||||
// <e> Clock Configuration
|
||||
// <h> System Controls and Status Register (SCS)
|
||||
// <o1.4> OSCRANGE: Main Oscillator Range Select
|
||||
// <0=> 1 MHz to 20 MHz
|
||||
// <1=> 15 MHz to 25 MHz
|
||||
// <e1.5> OSCEN: Main Oscillator Enable
|
||||
// </e>
|
||||
// </h>
|
||||
//
|
||||
// <h> Clock Source Select Register (CLKSRCSEL)
|
||||
// <o2.0..1> CLKSRC: PLL Clock Source Selection
|
||||
// <0=> Internal RC oscillator
|
||||
// <1=> Main oscillator
|
||||
// <2=> RTC oscillator
|
||||
// </h>
|
||||
//
|
||||
// <e3> PLL0 Configuration (Main PLL)
|
||||
// <h> PLL0 Configuration Register (PLL0CFG)
|
||||
// <i> F_cco0 = (2 * M * F_in) / N
|
||||
// <i> F_in must be in the range of 32 kHz to 50 MHz
|
||||
// <i> F_cco0 must be in the range of 275 MHz to 550 MHz
|
||||
// <o4.0..14> MSEL: PLL Multiplier Selection
|
||||
// <6-32768><#-1>
|
||||
// <i> M Value
|
||||
// <o4.16..23> NSEL: PLL Divider Selection
|
||||
// <1-256><#-1>
|
||||
// <i> N Value
|
||||
// </h>
|
||||
// </e>
|
||||
//
|
||||
// <e5> PLL1 Configuration (USB PLL)
|
||||
// <h> PLL1 Configuration Register (PLL1CFG)
|
||||
// <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)
|
||||
// <i> F_cco1 = F_osc * M * 2 * P
|
||||
// <i> F_cco1 must be in the range of 156 MHz to 320 MHz
|
||||
// <o6.0..4> MSEL: PLL Multiplier Selection
|
||||
// <1-32><#-1>
|
||||
// <i> M Value (for USB maximum value is 4)
|
||||
// <o6.5..6> PSEL: PLL Divider Selection
|
||||
// <0=> 1
|
||||
// <1=> 2
|
||||
// <2=> 4
|
||||
// <3=> 8
|
||||
// <i> P Value
|
||||
// </h>
|
||||
// </e>
|
||||
//
|
||||
// <h> CPU Clock Configuration Register (CCLKCFG)
|
||||
// <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0
|
||||
// <1-256><#-1>
|
||||
// </h>
|
||||
//
|
||||
// <h> USB Clock Configuration Register (USBCLKCFG)
|
||||
// <o8.0..3> USBSEL: Divide Value for USB Clock from PLL0
|
||||
// <0-15>
|
||||
// <i> Divide is USBSEL + 1
|
||||
// </h>
|
||||
//
|
||||
// <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
|
||||
// <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 6
|
||||
// <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 6
|
||||
// <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 6
|
||||
// </h>
|
||||
//
|
||||
// <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
|
||||
// <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// </h>
|
||||
//
|
||||
// <h> Power Control for Peripherals Register (PCONP)
|
||||
// <o11.1> PCTIM0: Timer/Counter 0 power/clock enable
|
||||
// <o11.2> PCTIM1: Timer/Counter 1 power/clock enable
|
||||
// <o11.3> PCUART0: UART 0 power/clock enable
|
||||
// <o11.4> PCUART1: UART 1 power/clock enable
|
||||
// <o11.6> PCPWM1: PWM 1 power/clock enable
|
||||
// <o11.7> PCI2C0: I2C interface 0 power/clock enable
|
||||
// <o11.8> PCSPI: SPI interface power/clock enable
|
||||
// <o11.9> PCRTC: RTC power/clock enable
|
||||
// <o11.10> PCSSP1: SSP interface 1 power/clock enable
|
||||
// <o11.12> PCAD: A/D converter power/clock enable
|
||||
// <o11.13> PCCAN1: CAN controller 1 power/clock enable
|
||||
// <o11.14> PCCAN2: CAN controller 2 power/clock enable
|
||||
// <o11.15> PCGPIO: GPIOs power/clock enable
|
||||
// <o11.16> PCRIT: Repetitive interrupt timer power/clock enable
|
||||
// <o11.17> PCMC: Motor control PWM power/clock enable
|
||||
// <o11.18> PCQEI: Quadrature encoder interface power/clock enable
|
||||
// <o11.19> PCI2C1: I2C interface 1 power/clock enable
|
||||
// <o11.21> PCSSP0: SSP interface 0 power/clock enable
|
||||
// <o11.22> PCTIM2: Timer 2 power/clock enable
|
||||
// <o11.23> PCTIM3: Timer 3 power/clock enable
|
||||
// <o11.24> PCUART2: UART 2 power/clock enable
|
||||
// <o11.25> PCUART3: UART 3 power/clock enable
|
||||
// <o11.26> PCI2C2: I2C interface 2 power/clock enable
|
||||
// <o11.27> PCI2S: I2S interface power/clock enable
|
||||
// <o11.29> PCGPDMA: GP DMA function power/clock enable
|
||||
// <o11.30> PCENET: Ethernet block power/clock enable
|
||||
// <o11.31> PCUSB: USB interface power/clock enable
|
||||
// </h>
|
||||
//
|
||||
// <h> Clock Output Configuration Register (CLKOUTCFG)
|
||||
// <o12.0..3> CLKOUTSEL: Selects clock source for CLKOUT
|
||||
// <0=> CPU clock
|
||||
// <1=> Main oscillator
|
||||
// <2=> Internal RC oscillator
|
||||
// <3=> USB clock
|
||||
// <4=> RTC oscillator
|
||||
// <o12.4..7> CLKOUTDIV: Selects clock divider for CLKOUT
|
||||
// <1-16><#-1>
|
||||
// <o12.8> CLKOUT_EN: CLKOUT enable control
|
||||
// </h>
|
||||
//
|
||||
// </e>
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @addtogroup LPC17xx_System_Defines LPC17xx System Defines
|
||||
@{
|
||||
*/
|
||||
|
||||
#define CLOCK_SETUP 1
|
||||
#define SCS_Val 0x00000020
|
||||
#define CLKSRCSEL_Val 0x00000001
|
||||
#define PLL0_SETUP 1 // WARNING: NOT USED, see SystemInit() below
|
||||
|
||||
# define PLL0CFG_Val 0x0000000B // WARNING: NOT USED, see SystemInit() below
|
||||
# define PLL1_SETUP 0 // WARNING: NOT USED, see SystemInit() below
|
||||
# define PLL1CFG_Val 0x00000000 // WARNING: NOT USED, see SystemInit() below
|
||||
# define CCLKCFG_Val 0x00000002 // WARNING: NOT USED, see SystemInit() below
|
||||
# define USBCLKCFG_Val 0x00000005 // WARNING: NOT USED, see SystemInit() below
|
||||
|
||||
#define PCLKSEL0_Val 0x00000000
|
||||
#define PCLKSEL1_Val 0x00000000
|
||||
#define PCONP_Val 0x042887DE
|
||||
#define CLKOUTCFG_Val 0x00000000
|
||||
|
||||
|
||||
/*--------------------- Flash Accelerator Configuration ----------------------
|
||||
//
|
||||
// <e> Flash Accelerator Configuration
|
||||
// <o1.12..15> FLASHTIM: Flash Access Time
|
||||
// <0=> 1 CPU clock (for CPU clock up to 20 MHz)
|
||||
// <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
|
||||
// <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
|
||||
// <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
|
||||
// <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
|
||||
// <5=> 6 CPU clocks (for any CPU clock)
|
||||
// </e>
|
||||
*/
|
||||
#define FLASH_SETUP 1
|
||||
#define FLASHCFG_Val 0x0000303A
|
||||
|
||||
/*
|
||||
//-------- <<< end of configuration section >>> ------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Check the register settings
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
|
||||
#define CHECK_RSVD(val, mask) (val & mask)
|
||||
|
||||
/* Clock Configuration -------------------------------------------------------*/
|
||||
#if (CHECK_RSVD((SCS_Val), ~0x00000030))
|
||||
#error "SCS: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))
|
||||
#error "CLKSRCSEL: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF))
|
||||
#error "PLL0CFG: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
|
||||
#error "PLL1CFG: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (PLL0_SETUP) /* if PLL0 is used */
|
||||
#if (CCLKCFG_Val < 2) /* CCLKSEL must be greater then 1 */
|
||||
#error "CCLKCFG: CCLKSEL must be greater then 1 if PLL0 is used!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((CCLKCFG_Val), 2, 255))
|
||||
#error "CCLKCFG: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))
|
||||
#error "USBCLKCFG: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00))
|
||||
#error "PCLKSEL0: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300))
|
||||
#error "PCLKSEL1: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((PCONP_Val), 0x10100821))
|
||||
#error "PCONP: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
|
||||
#error "CLKOUTCFG: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
/* Flash Accelerator Configuration -------------------------------------------*/
|
||||
#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F))
|
||||
#error "FLASHCFG: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
DEFINES
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define XTAL (12000000UL) /* Oscillator frequency */
|
||||
#define OSC_CLK ( XTAL) /* Main oscillator frequency */
|
||||
#define RTC_CLK ( 32000UL) /* RTC oscillator frequency */
|
||||
#define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */
|
||||
|
||||
|
||||
/* F_cco0 = (2 * M * F_in) / N */
|
||||
#define __M (((PLL0CFG_Val ) & 0x7FFF) + 1)
|
||||
#define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
|
||||
#define __FCCO(__F_IN) ((2ULL * __M * __F_IN) / __N)
|
||||
#define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1)
|
||||
|
||||
/* Determine core clock frequency according to settings */
|
||||
#if (PLL0_SETUP)
|
||||
#if ((CLKSRCSEL_Val & 0x03) == 1)
|
||||
#define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
|
||||
#elif ((CLKSRCSEL_Val & 0x03) == 2)
|
||||
#define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
|
||||
#else
|
||||
#define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
|
||||
#endif
|
||||
#else
|
||||
#if ((CLKSRCSEL_Val & 0x03) == 1)
|
||||
#define __CORE_CLK (OSC_CLK / __CCLK_DIV)
|
||||
#elif ((CLKSRCSEL_Val & 0x03) == 2)
|
||||
#define __CORE_CLK (RTC_CLK / __CCLK_DIV)
|
||||
#else
|
||||
#define __CORE_CLK (IRC_OSC / __CCLK_DIV)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup LPC17xx_System_Public_Variables LPC17xx System Public Variables
|
||||
@{
|
||||
*/
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup LPC17xx_System_Public_Functions LPC17xx System Public Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
|
||||
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
|
||||
{
|
||||
/* Determine clock frequency according to clock register values */
|
||||
if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
|
||||
switch (LPC_SC->CLKSRCSEL & 0x03) {
|
||||
case 0: /* Int. RC oscillator => PLL0 */
|
||||
case 3: /* Reserved, default to Int. RC */
|
||||
SystemCoreClock = (IRC_OSC *
|
||||
((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
|
||||
(((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
|
||||
((LPC_SC->CCLKCFG & 0xFF)+ 1));
|
||||
break;
|
||||
case 1: /* Main oscillator => PLL0 */
|
||||
SystemCoreClock = (OSC_CLK *
|
||||
((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
|
||||
(((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
|
||||
((LPC_SC->CCLKCFG & 0xFF)+ 1));
|
||||
break;
|
||||
case 2: /* RTC oscillator => PLL0 */
|
||||
SystemCoreClock = (RTC_CLK *
|
||||
((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
|
||||
(((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
|
||||
((LPC_SC->CCLKCFG & 0xFF)+ 1));
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
switch (LPC_SC->CLKSRCSEL & 0x03) {
|
||||
case 0: /* Int. RC oscillator => PLL0 */
|
||||
case 3: /* Reserved, default to Int. RC */
|
||||
SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
|
||||
break;
|
||||
case 1: /* Main oscillator => PLL0 */
|
||||
SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
|
||||
break;
|
||||
case 2: /* RTC oscillator => PLL0 */
|
||||
SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
|
||||
void SystemInit (void)
|
||||
{
|
||||
#if (CLOCK_SETUP) /* Clock Setup */
|
||||
LPC_SC->SCS = SCS_Val;
|
||||
if (LPC_SC->SCS & (1 << 5)) { /* If Main Oscillator is enabled */
|
||||
while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
|
||||
}
|
||||
|
||||
/* Periphral clock must be selected before PLL0 enabling and connecting
|
||||
* - according errata.lpc1768-16.March.2010 -
|
||||
*/
|
||||
LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
|
||||
LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
|
||||
|
||||
/*
|
||||
* PLL0 MUST be 275 - 550MHz
|
||||
*
|
||||
* PLL0 = Fin * M * 2 / N
|
||||
*
|
||||
* Fcpu = PLL0 / D
|
||||
*
|
||||
* PLL0CFG = (M - 1) + ((N - 1) << 16)
|
||||
* CCLKCFG = D - 1
|
||||
*
|
||||
* Common combinations (assuming 12MHz crystal):
|
||||
*
|
||||
* | Fcpu |--| Fin | M | N | PLL0 | D | PLL0CFG | CCLKCFG |
|
||||
* 96MHz :2* 12MHz * 12 / 1 = 288MHz / 3 0x0000B 0x2
|
||||
* 100MHz :2* 12MHz * 25 / 2 = 300MHz / 3 0x10018 0x2
|
||||
* 120MHz :2* 12MHz * 15 / 1 = 360MHz / 3 0x0000E 0x2
|
||||
*
|
||||
*/
|
||||
|
||||
LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */
|
||||
|
||||
LPC_SC->CCLKCFG = 0x00000002; /* Setup CPU Clock Divider */
|
||||
|
||||
LPC_SC->PLL0CFG = 0x00010018; // 100MHz
|
||||
LPC_SC->PLL0FEED = 0xAA;
|
||||
LPC_SC->PLL0FEED = 0x55;
|
||||
|
||||
LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
|
||||
LPC_SC->PLL0FEED = 0xAA;
|
||||
LPC_SC->PLL0FEED = 0x55;
|
||||
while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */
|
||||
|
||||
LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */
|
||||
LPC_SC->PLL0FEED = 0xAA;
|
||||
LPC_SC->PLL0FEED = 0x55;
|
||||
while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */
|
||||
|
||||
/*
|
||||
* USBCLK = Fin * M, where M is (1..32)
|
||||
*
|
||||
* we need a USBCLK of 48MHz, so given a 12MHz crystal, M must be 4
|
||||
*
|
||||
* PLL1 = USBCLK * 2 * P, where P is one of (1, 2, 4, 8)
|
||||
*
|
||||
* PLL1 MUST be 156 to 320MHz.
|
||||
* P=2 gives 192MHz, the only valid value within range
|
||||
*
|
||||
* PLL1CFG = (log2(P) << 5) + (M - 1)
|
||||
* = (1 << 5) + 3
|
||||
* = 0x23 for a 12MHz crystal
|
||||
*/
|
||||
LPC_SC->PLL1CFG = 0x00000023;
|
||||
LPC_SC->PLL1FEED = 0xAA;
|
||||
LPC_SC->PLL1FEED = 0x55;
|
||||
|
||||
LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
|
||||
LPC_SC->PLL1FEED = 0xAA;
|
||||
LPC_SC->PLL1FEED = 0x55;
|
||||
while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
|
||||
|
||||
LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */
|
||||
LPC_SC->PLL1FEED = 0xAA;
|
||||
LPC_SC->PLL1FEED = 0x55;
|
||||
while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */
|
||||
|
||||
// this sets up {global uint32 SystemCoreClock} with the new speed
|
||||
SystemCoreClockUpdate();
|
||||
|
||||
LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
|
||||
|
||||
LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
|
||||
#endif
|
||||
|
||||
#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
|
||||
LPC_SC->FLASHCFG = (LPC_SC->FLASHCFG & ~0x0000F000) | FLASHCFG_Val;
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
Reference in New Issue
Block a user