bissen21/Marlin_Firmware
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Add memory barrier, optimal interrupt on-off

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Disabling an ISR on ARM has 3 instructions of latency. A Memory barrier is REQUIRED to ensure proper and predictable disabling. Memory barriers are expensive, so avoid disabling if already disabled (See https://mcuoneclipse.com/2015/10/16/nvic-disabling-interrupts-on-arm-cortex-m-and-the-need-for-a-memory-barrier-instruction/)
This commit is contained in:
etagle
2018-05-16 16:38:17 -03:00
committed by Scott Lahteine
parent c2fb2f54a1
commit 0566badcef
11 changed files with 87 additions and 6 deletions
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4
Marlin/src/feature/Max7219_Debug_LEDs.cpp
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@ -73,7 +73,6 @@ static uint8_t LEDs[8] = { 0 };
#endif
void Max7219_PutByte(uint8_t data) {
CRITICAL_SECTION_START;
for (uint8_t i = 8; i--;) {
SIG_DELAY();
WRITE(MAX7219_CLK_PIN, LOW); // tick
@ -84,12 +83,10 @@ void Max7219_PutByte(uint8_t data) {
SIG_DELAY();
data <<= 1;
}
CRITICAL_SECTION_END;
}
void Max7219(const uint8_t reg, const uint8_t data) {
SIG_DELAY();
CRITICAL_SECTION_START;
WRITE(MAX7219_LOAD_PIN, LOW); // begin
SIG_DELAY();
Max7219_PutByte(reg); // specify register
@ -99,7 +96,6 @@ void Max7219(const uint8_t reg, const uint8_t data) {
WRITE(MAX7219_LOAD_PIN, LOW); // and tell the chip to load the data
SIG_DELAY();
WRITE(MAX7219_LOAD_PIN, HIGH);
CRITICAL_SECTION_END;
SIG_DELAY();
}