#define WPCMD_DIS_SW 0 // command to disable Write Protect SW
#define WPRG_ALL (PWM_WPCR_WPRG0 | PWM_WPCR_WPRG1 | PWM_WPCR_WPRG2 | PWM_WPCR_WPRG3 | PWM_WPCR_WPRG4 | PWM_WPCR_WPRG5) // all Write Protect Groups
#define PWM_CLOCK_F F_CPU / 1000000UL // set clock to 1MHz
PMC->PMC_PCER1=PMC_PCER1_PID36;// enable PWM controller clock (disabled on power up)
PWM->PWM_WPCR=WPKEY|WPRG_ALL|WPCMD_DIS_SW;// enable setting of all PWM registers
PWM->PWM_CLK=PWM_CLOCK_F;// enable CLK_A and set it to 1MHz, leave CLK_B disabled
PWM->PWM_CH_NUM[0].PWM_CMR=0b1011;// set channel 0 to Clock A input & to left aligned
PWM->PWM_CH_NUM[1].PWM_CMR=0b1011;// set channel 1 to Clock A input & to left aligned
PWM->PWM_CH_NUM[2].PWM_CMR=0b1011;// set channel 2 to Clock A input & to left aligned
PWM->PWM_CH_NUM[3].PWM_CMR=0b1011;// set channel 3 to Clock A input & to left aligned
PWM->PWM_CH_NUM[4].PWM_CMR=0b1011;// set channel 4 to Clock A input & to left aligned
PWM->PWM_CH_NUM[0].PWM_CPRD=PWM_PERIOD_US;// set channel 0 Period
PWM->PWM_IER2=PWM_IER1_CHID0;// generate interrupt when counter0 overflows
PWM->PWM_IER2=PWM_IER2_CMPM0|PWM_IER2_CMPM1|PWM_IER2_CMPM2|PWM_IER2_CMPM3|PWM_IER2_CMPM4;// generate interrupt on compare event
PWM->PWM_CMP[1].PWM_CMPV=0x010000000LL|G2_VREF_COUNT(G2_VREF(motor_current_setting[0]));// interrupt when counter0 == CMPV - used to set Motor 1 PWM inactive
PWM->PWM_CMP[2].PWM_CMPV=0x010000000LL|G2_VREF_COUNT(G2_VREF(motor_current_setting[0]));// interrupt when counter0 == CMPV - used to set Motor 2 PWM inactive
PWM->PWM_CMP[3].PWM_CMPV=0x010000000LL|G2_VREF_COUNT(G2_VREF(motor_current_setting[1]));// interrupt when counter0 == CMPV - used to set Motor 3 PWM inactive
PWM->PWM_CMP[4].PWM_CMPV=0x010000000LL|G2_VREF_COUNT(G2_VREF(motor_current_setting[2]));// interrupt when counter0 == CMPV - used to set Motor 4 PWM inactive