598 lines
19 KiB
C
598 lines
19 KiB
C
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/***************************************************************************
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* ARM Stack Unwinder, Michael.McTernan.2001@cs.bris.ac.uk
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* Updated, adapted and several bug fixes on 2018 by Eduardo José Tagle
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*
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* This program is PUBLIC DOMAIN.
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* This means that there is no copyright and anyone is able to take a copy
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* for free and use it as they wish, with or without modifications, and in
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* any context, commercially or otherwise. The only limitation is that I
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* don't guarantee that the software is fit for any purpose or accept any
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* liability for it's use or misuse - this software is without warranty.
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***************************************************************************
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* File Description: Abstract interpreter for ARM mode.
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**************************************************************************/
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#ifdef ARDUINO_ARCH_SAM
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#define MODULE_NAME "UNWARM_ARM"
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#include <stdio.h>
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#include "unwarm.h"
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/** Check if some instruction is a data-processing instruction.
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* Decodes the passed instruction, checks if it is a data-processing and
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* verifies that the parameters and operation really indicate a data-
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* processing instruction. This is needed because some parts of the
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* instruction space under this instruction can be extended or represent
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* other operations such as MRS, MSR.
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*
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* \param[in] inst The instruction word.
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* \retval true Further decoding of the instruction indicates that this is
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* a valid data-processing instruction.
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* \retval false This is not a data-processing instruction,
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*/
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static bool isDataProc(uint32_t instr) {
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uint8_t opcode = (instr & 0x01e00000) >> 21;
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bool S = (instr & 0x00100000) ? true : false;
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if((instr & 0xfc000000) != 0xe0000000) {
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return false;
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} else
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if(!S && opcode >= 8 && opcode <= 11) {
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/* TST, TEQ, CMP and CMN all require S to be set */
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return false;
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} else {
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return true;
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}
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}
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UnwResult UnwStartArm(UnwState * const state) {
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bool found = false;
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uint16_t t = UNW_MAX_INSTR_COUNT;
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do {
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uint32_t instr;
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/* Attempt to read the instruction */
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if(!state->cb->readW(state->regData[15].v, &instr)) {
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return UNWIND_IREAD_W_FAIL;
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}
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UnwPrintd4("A %x %x %08x:", state->regData[13].v, state->regData[15].v, instr);
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/* Check that the PC is still on Arm alignment */
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if(state->regData[15].v & 0x3) {
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UnwPrintd1("\nError: PC misalignment\n");
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return UNWIND_INCONSISTENT;
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}
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/* Check that the SP and PC have not been invalidated */
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if(!M_IsOriginValid(state->regData[13].o) || !M_IsOriginValid(state->regData[15].o)) {
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UnwPrintd1("\nError: PC or SP invalidated\n");
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return UNWIND_INCONSISTENT;
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}
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/* Branch and Exchange (BX)
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* This is tested prior to data processing to prevent
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* mis-interpretation as an invalid TEQ instruction.
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*/
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if((instr & 0xfffffff0) == 0xe12fff10) {
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uint8_t rn = instr & 0xf;
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UnwPrintd4("BX r%d\t ; r%d %s\n", rn, rn, M_Origin2Str(state->regData[rn].o));
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if(!M_IsOriginValid(state->regData[rn].o)) {
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UnwPrintd1("\nUnwind failure: BX to untracked register\n");
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return UNWIND_FAILURE;
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}
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/* Set the new PC value */
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state->regData[15].v = state->regData[rn].v;
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/* Check if the return value is from the stack */
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if(state->regData[rn].o == REG_VAL_FROM_STACK) {
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/* Now have the return address */
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UnwPrintd2(" Return PC=%x\n", state->regData[15].v & (~0x1));
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/* Report the return address */
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if(!UnwReportRetAddr(state, state->regData[rn].v)) {
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return UNWIND_TRUNCATED;
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}
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}
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/* Determine the return mode */
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if(state->regData[rn].v & 0x1) {
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/* Branching to THUMB */
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return UnwStartThumb(state);
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}
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else {
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/* Branch to ARM */
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/* Account for the auto-increment which isn't needed */
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state->regData[15].v -= 4;
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}
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}
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/* Branch */
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else if((instr & 0xff000000) == 0xea000000) {
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int32_t offset = (instr & 0x00ffffff);
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/* Shift value */
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offset = offset << 2;
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/* Sign extend if needed */
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if(offset & 0x02000000) {
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offset |= 0xfc000000;
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}
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UnwPrintd2("B %d\n", offset);
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/* Adjust PC */
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state->regData[15].v += offset;
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/* Account for pre-fetch, where normally the PC is 8 bytes
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* ahead of the instruction just executed.
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*/
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state->regData[15].v += 4;
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}
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/* MRS */
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else if((instr & 0xffbf0fff) == 0xe10f0000) {
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#if defined(UNW_DEBUG)
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bool R = (instr & 0x00400000) ? true : false;
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#endif
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uint8_t rd = (instr & 0x0000f000) >> 12;
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UnwPrintd4("MRS r%d,%s\t; r%d invalidated", rd, R ? "SPSR" : "CPSR", rd);
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/* Status registers untracked */
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state->regData[rd].o = REG_VAL_INVALID;
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}
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/* MSR */
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else if((instr & 0xffb0f000) == 0xe120f000) {
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#if defined(UNW_DEBUG)
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bool R = (instr & 0x00400000) ? true : false;
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UnwPrintd2("MSR %s_?, ???", R ? "SPSR" : "CPSR");
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#endif
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/* Status registers untracked.
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* Potentially this could change processor mode and switch
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* banked registers r8-r14. Most likely is that r13 (sp) will
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* be banked. However, invalidating r13 will stop unwinding
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* when potentially this write is being used to disable/enable
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* interrupts (a common case). Therefore no invalidation is
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* performed.
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*/
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}
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/* Data processing */
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else if(isDataProc(instr)) {
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bool I = (instr & 0x02000000) ? true : false;
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uint8_t opcode = (instr & 0x01e00000) >> 21;
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#if defined(UNW_DEBUG)
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bool S = (instr & 0x00100000) ? true : false;
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#endif
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uint8_t rn = (instr & 0x000f0000) >> 16;
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uint8_t rd = (instr & 0x0000f000) >> 12;
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uint16_t operand2 = (instr & 0x00000fff);
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uint32_t op2val;
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RegValOrigin op2origin;
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switch(opcode) {
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case 0: UnwPrintd4("AND%s r%d,r%d,", S ? "S" : "", rd, rn); break;
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case 1: UnwPrintd4("EOR%s r%d,r%d,", S ? "S" : "", rd, rn); break;
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case 2: UnwPrintd4("SUB%s r%d,r%d,", S ? "S" : "", rd, rn); break;
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case 3: UnwPrintd4("RSB%s r%d,r%d,", S ? "S" : "", rd, rn); break;
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case 4: UnwPrintd4("ADD%s r%d,r%d,", S ? "S" : "", rd, rn); break;
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case 5: UnwPrintd4("ADC%s r%d,r%d,", S ? "S" : "", rd, rn); break;
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case 6: UnwPrintd4("SBC%s r%d,r%d,", S ? "S" : "", rd, rn); break;
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case 7: UnwPrintd4("RSC%s r%d,r%d,", S ? "S" : "", rd, rn); break;
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case 8: UnwPrintd3("TST%s r%d,", S ? "S" : "", rn); break;
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case 9: UnwPrintd3("TEQ%s r%d,", S ? "S" : "", rn); break;
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case 10: UnwPrintd3("CMP%s r%d,", S ? "S" : "", rn); break;
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case 11: UnwPrintd3("CMN%s r%d,", S ? "S" : "", rn); break;
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case 12: UnwPrintd3("ORR%s r%d,", S ? "S" : "", rn); break;
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case 13: UnwPrintd3("MOV%s r%d,", S ? "S" : "", rd); break;
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case 14: UnwPrintd4("BIC%s r%d,r%d", S ? "S" : "", rd, rn); break;
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case 15: UnwPrintd3("MVN%s r%d,", S ? "S" : "", rd); break;
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}
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/* Decode operand 2 */
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if (I) {
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uint8_t shiftDist = (operand2 & 0x0f00) >> 8;
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uint8_t shiftConst = (operand2 & 0x00ff);
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/* rotate const right by 2 * shiftDist */
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shiftDist *= 2;
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op2val = (shiftConst >> shiftDist) |
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(shiftConst << (32 - shiftDist));
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op2origin = REG_VAL_FROM_CONST;
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UnwPrintd2("#0x%x", op2val);
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}
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else {
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/* Register and shift */
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uint8_t rm = (operand2 & 0x000f);
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uint8_t regShift = (operand2 & 0x0010) ? true : false;
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uint8_t shiftType = (operand2 & 0x0060) >> 5;
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uint32_t shiftDist;
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#if defined(UNW_DEBUG)
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const char * const shiftMnu[4] = { "LSL", "LSR", "ASR", "ROR" };
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#endif
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UnwPrintd2("r%d ", rm);
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/* Get the shift distance */
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if(regShift) {
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uint8_t rs = (operand2 & 0x0f00) >> 8;
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if(operand2 & 0x00800) {
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UnwPrintd1("\nError: Bit should be zero\n");
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return UNWIND_ILLEGAL_INSTR;
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}
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else if(rs == 15) {
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UnwPrintd1("\nError: Cannot use R15 with register shift\n");
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return UNWIND_ILLEGAL_INSTR;
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}
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/* Get shift distance */
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shiftDist = state->regData[rs].v;
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op2origin = state->regData[rs].o;
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UnwPrintd7("%s r%d\t; r%d %s r%d %s", shiftMnu[shiftType], rs, rm, M_Origin2Str(state->regData[rm].o), rs, M_Origin2Str(state->regData[rs].o));
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}
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else {
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shiftDist = (operand2 & 0x0f80) >> 7;
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op2origin = REG_VAL_FROM_CONST;
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if(shiftDist) {
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UnwPrintd3("%s #%d", shiftMnu[shiftType], shiftDist);
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}
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UnwPrintd3("\t; r%d %s", rm, M_Origin2Str(state->regData[rm].o));
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}
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/* Apply the shift type to the source register */
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switch(shiftType) {
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case 0: /* logical left */
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op2val = state->regData[rm].v << shiftDist;
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break;
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case 1: /* logical right */
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if(!regShift && shiftDist == 0) {
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shiftDist = 32;
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}
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op2val = state->regData[rm].v >> shiftDist;
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break;
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case 2: /* arithmetic right */
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if(!regShift && shiftDist == 0) {
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shiftDist = 32;
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}
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if(state->regData[rm].v & 0x80000000) {
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/* Register shifts maybe greater than 32 */
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if(shiftDist >= 32) {
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op2val = 0xffffffff;
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}
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else {
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op2val = state->regData[rm].v >> shiftDist;
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op2val |= 0xffffffff << (32 - shiftDist);
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}
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}
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else {
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op2val = state->regData[rm].v >> shiftDist;
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}
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break;
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case 3: /* rotate right */
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if(!regShift && shiftDist == 0) {
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/* Rotate right with extend.
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* This uses the carry bit and so always has an
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* untracked result.
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*/
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op2origin = REG_VAL_INVALID;
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op2val = 0;
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}
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else {
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/* Limit shift distance to 0-31 incase of register shift */
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shiftDist &= 0x1f;
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op2val = (state->regData[rm].v >> shiftDist) |
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(state->regData[rm].v << (32 - shiftDist));
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}
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break;
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default:
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UnwPrintd2("\nError: Invalid shift type: %d\n", shiftType);
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return UNWIND_FAILURE;
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}
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/* Decide the data origin */
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if(M_IsOriginValid(op2origin) &&
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M_IsOriginValid(state->regData[rm].o)) {
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op2origin = state->regData[rm].o;
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op2origin |= REG_VAL_ARITHMETIC;
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}
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else {
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op2origin = REG_VAL_INVALID;
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}
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}
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/* Propagate register validity */
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switch(opcode) {
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case 0: /* AND: Rd := Op1 AND Op2 */
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case 1: /* EOR: Rd := Op1 EOR Op2 */
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case 2: /* SUB: Rd:= Op1 - Op2 */
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case 3: /* RSB: Rd:= Op2 - Op1 */
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case 4: /* ADD: Rd:= Op1 + Op2 */
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case 12: /* ORR: Rd:= Op1 OR Op2 */
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case 14: /* BIC: Rd:= Op1 AND NOT Op2 */
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if(!M_IsOriginValid(state->regData[rn].o) ||
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!M_IsOriginValid(op2origin)) {
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state->regData[rd].o = REG_VAL_INVALID;
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}
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else {
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state->regData[rd].o = state->regData[rn].o;
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state->regData[rd].o |= op2origin;
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}
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break;
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case 5: /* ADC: Rd:= Op1 + Op2 + C */
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case 6: /* SBC: Rd:= Op1 - Op2 + C */
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case 7: /* RSC: Rd:= Op2 - Op1 + C */
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/* CPSR is not tracked */
|
||
|
|
state->regData[rd].o = REG_VAL_INVALID;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 8: /* TST: set condition codes on Op1 AND Op2 */
|
||
|
|
case 9: /* TEQ: set condition codes on Op1 EOR Op2 */
|
||
|
|
case 10: /* CMP: set condition codes on Op1 - Op2 */
|
||
|
|
case 11: /* CMN: set condition codes on Op1 + Op2 */
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 13: /* MOV: Rd:= Op2 */
|
||
|
|
case 15: /* MVN: Rd:= NOT Op2 */
|
||
|
|
state->regData[rd].o = op2origin;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Account for pre-fetch by temporarily adjusting PC */
|
||
|
|
if(rn == 15) {
|
||
|
|
|
||
|
|
/* If the shift amount is specified in the instruction,
|
||
|
|
* the PC will be 8 bytes ahead. If a register is used
|
||
|
|
* to specify the shift amount the PC will be 12 bytes
|
||
|
|
* ahead.
|
||
|
|
*/
|
||
|
|
if(!I && (operand2 & 0x0010))
|
||
|
|
state->regData[rn].v += 12;
|
||
|
|
else
|
||
|
|
state->regData[rn].v += 8;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Compute values */
|
||
|
|
switch(opcode) {
|
||
|
|
case 0: /* AND: Rd := Op1 AND Op2 */
|
||
|
|
state->regData[rd].v = state->regData[rn].v & op2val;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 1: /* EOR: Rd := Op1 EOR Op2 */
|
||
|
|
state->regData[rd].v = state->regData[rn].v ^ op2val;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 2: /* SUB: Rd:= Op1 - Op2 */
|
||
|
|
state->regData[rd].v = state->regData[rn].v - op2val;
|
||
|
|
break;
|
||
|
|
case 3: /* RSB: Rd:= Op2 - Op1 */
|
||
|
|
state->regData[rd].v = op2val - state->regData[rn].v;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 4: /* ADD: Rd:= Op1 + Op2 */
|
||
|
|
state->regData[rd].v = state->regData[rn].v + op2val;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 5: /* ADC: Rd:= Op1 + Op2 + C */
|
||
|
|
case 6: /* SBC: Rd:= Op1 - Op2 + C */
|
||
|
|
case 7: /* RSC: Rd:= Op2 - Op1 + C */
|
||
|
|
case 8: /* TST: set condition codes on Op1 AND Op2 */
|
||
|
|
case 9: /* TEQ: set condition codes on Op1 EOR Op2 */
|
||
|
|
case 10: /* CMP: set condition codes on Op1 - Op2 */
|
||
|
|
case 11: /* CMN: set condition codes on Op1 + Op2 */
|
||
|
|
UnwPrintd1("\t; ????");
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 12: /* ORR: Rd:= Op1 OR Op2 */
|
||
|
|
state->regData[rd].v = state->regData[rn].v | op2val;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 13: /* MOV: Rd:= Op2 */
|
||
|
|
state->regData[rd].v = op2val;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 14: /* BIC: Rd:= Op1 AND NOT Op2 */
|
||
|
|
state->regData[rd].v = state->regData[rn].v & (~op2val);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 15: /* MVN: Rd:= NOT Op2 */
|
||
|
|
state->regData[rd].v = ~op2val;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Remove the prefetch offset from the PC */
|
||
|
|
if(rd != 15 && rn == 15) {
|
||
|
|
if(!I && (operand2 & 0x0010))
|
||
|
|
state->regData[rn].v -= 12;
|
||
|
|
else
|
||
|
|
state->regData[rn].v -= 8;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Block Data Transfer
|
||
|
|
* LDM, STM
|
||
|
|
*/
|
||
|
|
else if((instr & 0xfe000000) == 0xe8000000) {
|
||
|
|
|
||
|
|
bool P = (instr & 0x01000000) ? true : false;
|
||
|
|
bool U = (instr & 0x00800000) ? true : false;
|
||
|
|
bool S = (instr & 0x00400000) ? true : false;
|
||
|
|
bool W = (instr & 0x00200000) ? true : false;
|
||
|
|
bool L = (instr & 0x00100000) ? true : false;
|
||
|
|
uint16_t baseReg = (instr & 0x000f0000) >> 16;
|
||
|
|
uint16_t regList = (instr & 0x0000ffff);
|
||
|
|
uint32_t addr = state->regData[baseReg].v;
|
||
|
|
bool addrValid = M_IsOriginValid(state->regData[baseReg].o);
|
||
|
|
int8_t r;
|
||
|
|
|
||
|
|
#if defined(UNW_DEBUG)
|
||
|
|
/* Display the instruction */
|
||
|
|
if(L) {
|
||
|
|
UnwPrintd6("LDM%c%c r%d%s, {reglist}%s\n", P ? 'E' : 'F', U ? 'D' : 'A', baseReg, W ? "!" : "", S ? "^" : "");
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
UnwPrintd6("STM%c%c r%d%s, {reglist}%s\n", !P ? 'E' : 'F', !U ? 'D' : 'A', baseReg, W ? "!" : "", S ? "^" : "");
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
/* S indicates that banked registers (untracked) are used, unless
|
||
|
|
* this is a load including the PC when the S-bit indicates that
|
||
|
|
* that CPSR is loaded from SPSR (also untracked, but ignored).
|
||
|
|
*/
|
||
|
|
if(S && (!L || (regList & (0x01 << 15)) == 0)) {
|
||
|
|
UnwPrintd1("\nError:S-bit set requiring banked registers\n");
|
||
|
|
return UNWIND_FAILURE;
|
||
|
|
}
|
||
|
|
else if(baseReg == 15) {
|
||
|
|
UnwPrintd1("\nError: r15 used as base register\n");
|
||
|
|
return UNWIND_FAILURE;
|
||
|
|
}
|
||
|
|
else if(regList == 0) {
|
||
|
|
UnwPrintd1("\nError: Register list empty\n");
|
||
|
|
return UNWIND_FAILURE;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Check if ascending or descending.
|
||
|
|
* Registers are loaded/stored in order of address.
|
||
|
|
* i.e. r0 is at the lowest address, r15 at the highest.
|
||
|
|
*/
|
||
|
|
r = U ? 0 : 15;
|
||
|
|
do {
|
||
|
|
|
||
|
|
/* Check if the register is to be transferred */
|
||
|
|
if(regList & (0x01 << r)) {
|
||
|
|
|
||
|
|
if(P)
|
||
|
|
addr += U ? 4 : -4;
|
||
|
|
|
||
|
|
if(L) {
|
||
|
|
|
||
|
|
if(addrValid) {
|
||
|
|
|
||
|
|
if(!UnwMemReadRegister(state, addr, &state->regData[r])) {
|
||
|
|
return UNWIND_DREAD_W_FAIL;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Update the origin if read via the stack pointer */
|
||
|
|
if(M_IsOriginValid(state->regData[r].o) && baseReg == 13) {
|
||
|
|
state->regData[r].o = REG_VAL_FROM_STACK;
|
||
|
|
}
|
||
|
|
|
||
|
|
UnwPrintd5(" R%d = 0x%08x\t; r%d %s\n",r,state->regData[r].v,r, M_Origin2Str(state->regData[r].o));
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
|
||
|
|
/* Invalidate the register as the base reg was invalid */
|
||
|
|
state->regData[r].o = REG_VAL_INVALID;
|
||
|
|
|
||
|
|
UnwPrintd2(" R%d = ???\n", r);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
if(addrValid) {
|
||
|
|
if(!UnwMemWriteRegister(state, state->regData[13].v, &state->regData[r])) {
|
||
|
|
return UNWIND_DWRITE_W_FAIL;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
UnwPrintd2(" R%d = 0x%08x\n", r);
|
||
|
|
}
|
||
|
|
|
||
|
|
if(!P)
|
||
|
|
addr += U ? 4 : -4;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Check the next register */
|
||
|
|
r += U ? 1 : -1;
|
||
|
|
|
||
|
|
} while(r >= 0 && r <= 15);
|
||
|
|
|
||
|
|
/* Check the writeback bit */
|
||
|
|
if(W)
|
||
|
|
state->regData[baseReg].v = addr;
|
||
|
|
|
||
|
|
/* Check if the PC was loaded */
|
||
|
|
if(L && (regList & (0x01 << 15))) {
|
||
|
|
if(!M_IsOriginValid(state->regData[15].o)) {
|
||
|
|
/* Return address is not valid */
|
||
|
|
UnwPrintd1("PC popped with invalid address\n");
|
||
|
|
return UNWIND_FAILURE;
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
/* Store the return address */
|
||
|
|
if(!UnwReportRetAddr(state, state->regData[15].v)) {
|
||
|
|
return UNWIND_TRUNCATED;
|
||
|
|
}
|
||
|
|
|
||
|
|
UnwPrintd2(" Return PC=0x%x", state->regData[15].v);
|
||
|
|
|
||
|
|
/* Determine the return mode */
|
||
|
|
if(state->regData[15].v & 0x1) {
|
||
|
|
/* Branching to THUMB */
|
||
|
|
return UnwStartThumb(state);
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
/* Branch to ARM */
|
||
|
|
|
||
|
|
/* Account for the auto-increment which isn't needed */
|
||
|
|
state->regData[15].v -= 4;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
UnwPrintd1("????");
|
||
|
|
|
||
|
|
/* Unknown/undecoded. May alter some register, so invalidate file */
|
||
|
|
UnwInvalidateRegisterFile(state->regData);
|
||
|
|
}
|
||
|
|
|
||
|
|
UnwPrintd1("\n");
|
||
|
|
|
||
|
|
/* Should never hit the reset vector */
|
||
|
|
if(state->regData[15].v == 0) return UNWIND_RESET;
|
||
|
|
|
||
|
|
/* Check next address */
|
||
|
|
state->regData[15].v += 4;
|
||
|
|
|
||
|
|
/* Garbage collect the memory hash (used only for the stack) */
|
||
|
|
UnwMemHashGC(state);
|
||
|
|
|
||
|
|
t--;
|
||
|
|
if(t == 0)
|
||
|
|
return UNWIND_EXHAUSTED;
|
||
|
|
|
||
|
|
} while(!found);
|
||
|
|
|
||
|
|
return UNWIND_UNSUPPORTED;
|
||
|
|
}
|
||
|
|
#endif
|