2020-02-04 01:24:11 -06:00
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/**
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* Marlin 3D Printer Firmware
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* Copyright (c) 2020 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
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*
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* Based on Sprinter and grbl.
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* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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2020-07-22 22:20:14 -05:00
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* along with this program. If not, see <https://www.gnu.org/licenses/>.
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2020-02-04 01:24:11 -06:00
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*
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*/
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2020-11-26 03:47:07 -06:00
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#if defined(ARDUINO_ARCH_STM32) && !defined(STM32GENERIC)
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2020-02-04 01:24:11 -06:00
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#include "../../inc/MarlinConfig.h"
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2020-11-26 03:47:07 -06:00
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#if ENABLED(SDIO_SUPPORT)
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2020-02-04 01:24:11 -06:00
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#include <stdint.h>
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#include <stdbool.h>
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2020-04-22 15:00:10 -05:00
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#if NONE(STM32F103xE, STM32F103xG, STM32F4xx, STM32F7xx)
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2020-02-04 01:24:11 -06:00
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#error "ERROR - Only STM32F103xE, STM32F103xG, STM32F4xx or STM32F7xx CPUs supported"
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#endif
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2020-11-17 23:48:14 -06:00
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#if HAS_SD_HOST_DRIVE
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2020-02-04 01:24:11 -06:00
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2020-04-22 15:00:10 -05:00
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// use USB drivers
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2020-02-04 01:24:11 -06:00
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2021-03-29 21:52:30 -05:00
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extern "C" {
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int8_t SD_MSC_Read(uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len);
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int8_t SD_MSC_Write(uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len);
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extern SD_HandleTypeDef hsd;
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2020-04-22 15:00:10 -05:00
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}
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bool SDIO_Init() {
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2020-07-25 01:53:07 -05:00
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return hsd.State == HAL_SD_STATE_READY; // return pass/fail status
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2020-04-22 15:00:10 -05:00
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}
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bool SDIO_ReadBlock(uint32_t block, uint8_t *src) {
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int8_t status = SD_MSC_Read(0, (uint8_t*)src, block, 1); // read one 512 byte block
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return (bool) status;
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}
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bool SDIO_WriteBlock(uint32_t block, const uint8_t *src) {
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int8_t status = SD_MSC_Write(0, (uint8_t*)src, block, 1); // write one 512 byte block
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return (bool) status;
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}
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2020-02-04 01:24:11 -06:00
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2020-04-22 15:00:10 -05:00
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#else // !USBD_USE_CDC_COMPOSITE
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// use local drivers
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#if defined(STM32F103xE) || defined(STM32F103xG)
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#include <stm32f1xx_hal_rcc_ex.h>
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#include <stm32f1xx_hal_sd.h>
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#elif defined(STM32F4xx)
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#include <stm32f4xx_hal_rcc.h>
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#include <stm32f4xx_hal_dma.h>
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#include <stm32f4xx_hal_gpio.h>
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#include <stm32f4xx_hal_sd.h>
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#elif defined(STM32F7xx)
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#include <stm32f7xx_hal_rcc.h>
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#include <stm32f7xx_hal_dma.h>
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#include <stm32f7xx_hal_gpio.h>
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#include <stm32f7xx_hal_sd.h>
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#else
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#error "ERROR - Only STM32F103xE, STM32F103xG, STM32F4xx or STM32F7xx CPUs supported"
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#endif
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2020-02-04 01:24:11 -06:00
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2021-03-29 21:52:30 -05:00
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// Fixed
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#define SDIO_D0_PIN PC8
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#define SDIO_D1_PIN PC9
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#define SDIO_D2_PIN PC10
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#define SDIO_D3_PIN PC11
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#define SDIO_CK_PIN PC12
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#define SDIO_CMD_PIN PD2
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2020-04-22 15:00:10 -05:00
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SD_HandleTypeDef hsd; // create SDIO structure
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2021-03-29 21:52:30 -05:00
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// F4 support one dma for RX and another for TX.
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// But Marlin will never do read and write at same time, so we use always one dma for both.
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DMA_HandleTypeDef hdma_sdio;
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2020-02-04 01:24:11 -06:00
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2020-07-30 01:43:19 -05:00
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/*
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SDIO_INIT_CLK_DIV is 118
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SDIO clock frequency is 48MHz / (TRANSFER_CLOCK_DIV + 2)
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SDIO init clock frequency should not exceed 400KHz = 48MHz / (118 + 2)
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Default TRANSFER_CLOCK_DIV is 2 (118 / 40)
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Default SDIO clock frequency is 48MHz / (2 + 2) = 12 MHz
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This might be too fast for stable SDIO operations
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MKS Robin board seems to have stable SDIO with BusWide 1bit and ClockDiv 8 i.e. 4.8MHz SDIO clock frequency
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Additional testing is required as there are clearly some 4bit initialization problems
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*/
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2020-04-22 15:00:10 -05:00
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#ifndef USBD_OK
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#define USBD_OK 0
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#endif
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2020-02-04 01:24:11 -06:00
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2020-12-27 23:08:06 -06:00
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// Target Clock, configurable. Default is 18MHz, from STM32F1
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#ifndef SDIO_CLOCK
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2021-03-29 21:52:30 -05:00
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#define SDIO_CLOCK 18000000 // 18 MHz
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2020-12-27 23:08:06 -06:00
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#endif
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// SDIO retries, configurable. Default is 3, from STM32F1
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#ifndef SDIO_READ_RETRIES
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2021-03-29 21:52:30 -05:00
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#define SDIO_READ_RETRIES 3
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2020-12-27 23:08:06 -06:00
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#endif
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// SDIO Max Clock (naming from STM Manual, don't change)
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#define SDIOCLK 48000000
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static uint32_t clock_to_divider(uint32_t clk) {
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// limit the SDIO master clock to 8/3 of PCLK2. See STM32 Manuals
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// Also limited to no more than 48Mhz (SDIOCLK).
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const uint32_t pclk2 = HAL_RCC_GetPCLK2Freq();
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clk = min(clk, (uint32_t)(pclk2 * 8 / 3));
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clk = min(clk, (uint32_t)SDIOCLK);
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// Round up divider, so we don't run the card over the speed supported,
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// and subtract by 2, because STM32 will add 2, as written in the manual:
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// SDIO_CK frequency = SDIOCLK / [CLKDIV + 2]
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return pclk2 / clk + (pclk2 % clk != 0) - 2;
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}
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2020-04-22 15:00:10 -05:00
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void go_to_transfer_speed() {
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/* Default SDIO peripheral configuration for SD card initialization */
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2021-03-29 21:52:30 -05:00
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hsd.Init.ClockEdge = hsd.Init.ClockEdge;
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hsd.Init.ClockBypass = hsd.Init.ClockBypass;
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hsd.Init.ClockPowerSave = hsd.Init.ClockPowerSave;
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hsd.Init.BusWide = hsd.Init.BusWide;
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hsd.Init.HardwareFlowControl = hsd.Init.HardwareFlowControl;
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hsd.Init.ClockDiv = clock_to_divider(SDIO_CLOCK);
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2020-02-04 01:24:11 -06:00
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2020-04-22 15:00:10 -05:00
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/* Initialize SDIO peripheral interface with default configuration */
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2021-03-29 21:52:30 -05:00
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SDIO_Init(hsd.Instance, hsd.Init);
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2020-04-22 15:00:10 -05:00
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}
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2020-02-04 01:24:11 -06:00
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2020-04-22 15:00:10 -05:00
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void SD_LowLevel_Init(void) {
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uint32_t tempreg;
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2020-02-04 01:24:11 -06:00
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2020-04-22 15:00:10 -05:00
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__HAL_RCC_GPIOC_CLK_ENABLE(); //enable GPIO clocks
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__HAL_RCC_GPIOD_CLK_ENABLE(); //enable GPIO clocks
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2020-07-30 01:43:19 -05:00
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GPIO_InitTypeDef GPIO_InitStruct;
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2020-02-04 01:24:11 -06:00
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStruct.Pull = 1; //GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
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2020-07-30 01:43:19 -05:00
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#if DISABLED(STM32F1xx)
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GPIO_InitStruct.Alternate = GPIO_AF12_SDIO;
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#endif
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GPIO_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_12; // D0 & SCK
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2020-02-04 01:24:11 -06:00
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HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
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2020-04-22 15:00:10 -05:00
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#if PINS_EXIST(SDIO_D1, SDIO_D2, SDIO_D3) // define D1-D3 only if have a four bit wide SDIO bus
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GPIO_InitStruct.Pin = GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11; // D1-D3
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HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
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#endif
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// Configure PD.02 CMD line
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GPIO_InitStruct.Pin = GPIO_PIN_2;
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HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
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2021-03-29 21:52:30 -05:00
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// Setup DMA
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#if defined(STM32F1xx)
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hdma_sdio.Init.Mode = DMA_NORMAL;
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hdma_sdio.Instance = DMA2_Channel4;
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HAL_NVIC_EnableIRQ(DMA2_Channel4_5_IRQn);
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#elif defined(STM32F4xx)
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hdma_sdio.Init.Mode = DMA_PFCTRL;
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hdma_sdio.Instance = DMA2_Stream3;
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hdma_sdio.Init.Channel = DMA_CHANNEL_4;
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hdma_sdio.Init.FIFOMode = DMA_FIFOMODE_ENABLE;
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hdma_sdio.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
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hdma_sdio.Init.MemBurst = DMA_MBURST_INC4;
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hdma_sdio.Init.PeriphBurst = DMA_PBURST_INC4;
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HAL_NVIC_EnableIRQ(DMA2_Stream3_IRQn);
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#endif
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HAL_NVIC_EnableIRQ(SDIO_IRQn);
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hdma_sdio.Init.PeriphInc = DMA_PINC_DISABLE;
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hdma_sdio.Init.MemInc = DMA_MINC_ENABLE;
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hdma_sdio.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
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hdma_sdio.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
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hdma_sdio.Init.Priority = DMA_PRIORITY_LOW;
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__HAL_LINKDMA(&hsd, hdmarx, hdma_sdio);
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__HAL_LINKDMA(&hsd, hdmatx, hdma_sdio);
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#if defined(STM32F1xx)
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__HAL_RCC_SDIO_CLK_ENABLE();
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__HAL_RCC_DMA2_CLK_ENABLE();
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#else
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__HAL_RCC_SDIO_FORCE_RESET();
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delay(2);
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__HAL_RCC_SDIO_RELEASE_RESET();
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delay(2);
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__HAL_RCC_SDIO_CLK_ENABLE();
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__HAL_RCC_DMA2_FORCE_RESET();
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delay(2);
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__HAL_RCC_DMA2_RELEASE_RESET();
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delay(2);
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__HAL_RCC_DMA2_CLK_ENABLE();
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2020-07-30 01:43:19 -05:00
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#endif
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2020-04-22 15:00:10 -05:00
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//Initialize the SDIO (with initial <400Khz Clock)
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tempreg = 0; //Reset value
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tempreg |= SDIO_CLKCR_CLKEN; // Clock enabled
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2020-12-27 23:08:06 -06:00
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tempreg |= SDIO_INIT_CLK_DIV; // Clock Divider. Clock = 48000 / (118 + 2) = 400Khz
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2020-04-22 15:00:10 -05:00
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// Keep the rest at 0 => HW_Flow Disabled, Rising Clock Edge, Disable CLK ByPass, Bus Width = 0, Power save Disable
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SDIO->CLKCR = tempreg;
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// Power up the SDIO
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2020-12-27 23:08:06 -06:00
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SDIO_PowerState_ON(SDIO);
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2021-03-29 21:52:30 -05:00
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hsd.Instance = SDIO;
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2020-04-22 15:00:10 -05:00
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}
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2020-02-04 01:24:11 -06:00
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2020-04-22 15:00:10 -05:00
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void HAL_SD_MspInit(SD_HandleTypeDef *hsd) { // application specific init
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2020-12-27 23:08:06 -06:00
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UNUSED(hsd); // Prevent unused argument(s) compilation warning
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2020-04-22 15:00:10 -05:00
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__HAL_RCC_SDIO_CLK_ENABLE(); // turn on SDIO clock
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}
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2020-02-04 01:24:11 -06:00
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2020-04-22 15:00:10 -05:00
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bool SDIO_Init() {
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2020-12-27 23:08:06 -06:00
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uint8_t retryCnt = SDIO_READ_RETRIES;
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2020-02-04 01:24:11 -06:00
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2020-04-22 15:00:10 -05:00
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bool status;
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hsd.Instance = SDIO;
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2020-12-27 23:08:06 -06:00
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hsd.State = HAL_SD_STATE_RESET;
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2020-07-30 01:43:19 -05:00
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2020-04-22 15:00:10 -05:00
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SD_LowLevel_Init();
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2020-02-04 01:24:11 -06:00
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2020-04-22 15:00:10 -05:00
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uint8_t retry_Cnt = retryCnt;
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for (;;) {
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2020-07-30 01:43:19 -05:00
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TERN_(USE_WATCHDOG, HAL_watchdog_refresh());
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2020-04-22 15:00:10 -05:00
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status = (bool) HAL_SD_Init(&hsd);
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if (!status) break;
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if (!--retry_Cnt) return false; // return failing status if retries are exhausted
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}
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2020-02-04 01:24:11 -06:00
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2020-04-22 15:00:10 -05:00
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go_to_transfer_speed();
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2020-02-04 01:24:11 -06:00
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2020-04-22 15:00:10 -05:00
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#if PINS_EXIST(SDIO_D1, SDIO_D2, SDIO_D3) // go to 4 bit wide mode if pins are defined
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retry_Cnt = retryCnt;
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for (;;) {
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2020-07-30 01:43:19 -05:00
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TERN_(USE_WATCHDOG, HAL_watchdog_refresh());
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2020-04-22 15:00:10 -05:00
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if (!HAL_SD_ConfigWideBusOperation(&hsd, SDIO_BUS_WIDE_4B)) break; // some cards are only 1 bit wide so a pass here is not required
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if (!--retry_Cnt) break;
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}
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if (!retry_Cnt) { // wide bus failed, go back to one bit wide mode
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hsd.State = (HAL_SD_StateTypeDef) 0; // HAL_SD_STATE_RESET
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SD_LowLevel_Init();
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retry_Cnt = retryCnt;
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for (;;) {
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2020-07-30 01:43:19 -05:00
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TERN_(USE_WATCHDOG, HAL_watchdog_refresh());
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2020-04-22 15:00:10 -05:00
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status = (bool) HAL_SD_Init(&hsd);
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if (!status) break;
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if (!--retry_Cnt) return false; // return failing status if retries are exhausted
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}
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2021-03-29 21:52:30 -05:00
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go_to_transfer_speed();
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2020-04-22 15:00:10 -05:00
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}
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#endif
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return true;
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}
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2021-03-29 21:52:30 -05:00
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static bool SDIO_ReadWriteBlock_DMA(uint32_t block, const uint8_t *src, uint8_t *dst) {
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if(HAL_SD_GetCardState(&hsd) != HAL_SD_CARD_TRANSFER) return false;
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2020-04-22 15:00:10 -05:00
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2021-03-29 21:52:30 -05:00
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TERN_(USE_WATCHDOG, HAL_watchdog_refresh());
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2020-02-04 01:24:11 -06:00
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2021-03-29 21:52:30 -05:00
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HAL_StatusTypeDef ret;
|
|
|
|
if (src) {
|
|
|
|
hdma_sdio.Init.Direction = DMA_MEMORY_TO_PERIPH;
|
|
|
|
HAL_DMA_Init(&hdma_sdio);
|
|
|
|
ret = HAL_SD_WriteBlocks_DMA(&hsd, (uint8_t *)src, block, 1);
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
hdma_sdio.Init.Direction = DMA_PERIPH_TO_MEMORY;
|
|
|
|
HAL_DMA_Init(&hdma_sdio);
|
|
|
|
ret = HAL_SD_ReadBlocks_DMA(&hsd, (uint8_t *)dst, block, 1);
|
2020-02-04 01:24:11 -06:00
|
|
|
}
|
|
|
|
|
2021-03-29 21:52:30 -05:00
|
|
|
if (ret != HAL_OK) {
|
|
|
|
HAL_DMA_Abort_IT(&hdma_sdio);
|
|
|
|
HAL_DMA_DeInit(&hdma_sdio);
|
2020-04-22 15:00:10 -05:00
|
|
|
return false;
|
|
|
|
}
|
2020-02-04 01:24:11 -06:00
|
|
|
|
2021-03-29 21:52:30 -05:00
|
|
|
uint32_t timeout = millis() + 500;
|
|
|
|
// Wait the transfer
|
|
|
|
while (hsd.State != HAL_SD_STATE_READY) {
|
|
|
|
if (millis() > timeout) {
|
|
|
|
HAL_DMA_Abort_IT(&hdma_sdio);
|
|
|
|
HAL_DMA_DeInit(&hdma_sdio);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
2020-02-04 01:24:11 -06:00
|
|
|
|
2021-03-29 21:52:30 -05:00
|
|
|
while (__HAL_DMA_GET_FLAG(&hdma_sdio, __HAL_DMA_GET_TC_FLAG_INDEX(&hdma_sdio)) != 0
|
|
|
|
|| __HAL_DMA_GET_FLAG(&hdma_sdio, __HAL_DMA_GET_TE_FLAG_INDEX(&hdma_sdio)) != 0) { /* nada */ }
|
2020-02-04 01:24:11 -06:00
|
|
|
|
2021-03-29 21:52:30 -05:00
|
|
|
HAL_DMA_Abort_IT(&hdma_sdio);
|
|
|
|
HAL_DMA_DeInit(&hdma_sdio);
|
2020-02-04 01:24:11 -06:00
|
|
|
|
2021-03-29 21:52:30 -05:00
|
|
|
timeout = millis() + 500;
|
|
|
|
while (HAL_SD_GetCardState(&hsd) != HAL_SD_CARD_TRANSFER)
|
|
|
|
if (millis() > timeout) return false;
|
2020-02-04 01:24:11 -06:00
|
|
|
|
2020-04-22 15:00:10 -05:00
|
|
|
return true;
|
2020-02-04 01:24:11 -06:00
|
|
|
}
|
|
|
|
|
2021-03-29 21:52:30 -05:00
|
|
|
bool SDIO_ReadBlock(uint32_t block, uint8_t *dst) {
|
|
|
|
uint8_t retries = SDIO_READ_RETRIES;
|
|
|
|
while (retries--) if (SDIO_ReadWriteBlock_DMA(block, NULL, dst)) return true;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2020-04-22 15:00:10 -05:00
|
|
|
bool SDIO_WriteBlock(uint32_t block, const uint8_t *src) {
|
2021-03-29 21:52:30 -05:00
|
|
|
uint8_t retries = SDIO_READ_RETRIES;
|
|
|
|
while (retries--) if (SDIO_ReadWriteBlock_DMA(block, src, NULL)) return true;
|
|
|
|
return false;
|
2020-02-04 01:24:11 -06:00
|
|
|
}
|
|
|
|
|
2021-03-29 21:52:30 -05:00
|
|
|
#if defined(STM32F1xx)
|
|
|
|
#define DMA_IRQ_HANDLER DMA2_Channel4_5_IRQHandler
|
|
|
|
#elif defined(STM32F4xx)
|
|
|
|
#define DMA_IRQ_HANDLER DMA2_Stream3_IRQHandler
|
|
|
|
#else
|
|
|
|
#error "Unknown STM32 architecture."
|
|
|
|
#endif
|
|
|
|
|
|
|
|
extern "C" void SDIO_IRQHandler(void) { HAL_SD_IRQHandler(&hsd); }
|
|
|
|
extern "C" void DMA_IRQ_HANDLER(void) { HAL_DMA_IRQHandler(&hdma_sdio); }
|
|
|
|
|
2020-04-22 15:00:10 -05:00
|
|
|
#endif // !USBD_USE_CDC_COMPOSITE
|
2020-02-04 01:24:11 -06:00
|
|
|
#endif // SDIO_SUPPORT
|
2020-11-26 03:47:07 -06:00
|
|
|
#endif // ARDUINO_ARCH_STM32 && !STM32GENERIC
|