PWM working, reading input voltage signal.
This commit is contained in:
515
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c
Normal file
515
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c
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@@ -0,0 +1,515 @@
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/**
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******************************************************************************
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* @file stm32f0xx_hal.c
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* @author MCD Application Team
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* @brief HAL module driver.
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* This is the common part of the HAL initialization
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*
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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@verbatim
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==============================================================================
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##### How to use this driver #####
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==============================================================================
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[..]
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The common HAL driver contains a set of generic and common APIs that can be
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used by the PPP peripheral drivers and the user to start using the HAL.
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[..]
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The HAL contains two APIs categories:
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(+) HAL Initialization and de-initialization functions
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(+) HAL Control functions
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@endverbatim
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f0xx_hal.h"
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/** @addtogroup STM32F0xx_HAL_Driver
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* @{
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*/
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/** @defgroup HAL HAL
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* @brief HAL module driver.
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* @{
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*/
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#ifdef HAL_MODULE_ENABLED
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/** @defgroup HAL_Private_Constants HAL Private Constants
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* @{
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*/
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/**
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* @brief STM32F0xx HAL Driver version number
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*/
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#define __STM32F0xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
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#define __STM32F0xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */
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#define __STM32F0xx_HAL_VERSION_SUB2 (0x08U) /*!< [15:8] sub2 version */
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#define __STM32F0xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
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#define __STM32F0xx_HAL_VERSION ((__STM32F0xx_HAL_VERSION_MAIN << 24U)\
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|(__STM32F0xx_HAL_VERSION_SUB1 << 16U)\
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|(__STM32F0xx_HAL_VERSION_SUB2 << 8U )\
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|(__STM32F0xx_HAL_VERSION_RC))
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#define IDCODE_DEVID_MASK (0x00000FFFU)
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/**
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* @}
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*/
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/* Private macro -------------------------------------------------------------*/
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/** @defgroup HAL_Private_Macros HAL Private Macros
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* @{
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*/
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/**
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* @}
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*/
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/* Exported variables ---------------------------------------------------------*/
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/** @defgroup HAL_Private_Variables HAL Exported Variables
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* @{
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*/
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__IO uint32_t uwTick;
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uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
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HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
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/**
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* @}
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*/
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/* Private function prototypes -----------------------------------------------*/
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/* Exported functions ---------------------------------------------------------*/
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/** @defgroup HAL_Exported_Functions HAL Exported Functions
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* @{
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*/
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/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
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* @brief Initialization and de-initialization functions
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*
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@verbatim
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===============================================================================
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##### Initialization and de-initialization functions #####
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===============================================================================
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[..] This section provides functions allowing to:
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(+) Initializes the Flash interface, the NVIC allocation and initial clock
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configuration. It initializes the systick also when timeout is needed
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and the backup domain when enabled.
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(+) de-Initializes common part of the HAL.
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(+) Configure The time base source to have 1ms time base with a dedicated
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Tick interrupt priority.
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(++) SysTick timer is used by default as source of time base, but user
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can eventually implement his proper time base source (a general purpose
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timer for example or other time source), keeping in mind that Time base
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duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
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handled in milliseconds basis.
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(++) Time base configuration function (HAL_InitTick ()) is called automatically
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at the beginning of the program after reset by HAL_Init() or at any time
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when clock is configured, by HAL_RCC_ClockConfig().
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(++) Source of time base is configured to generate interrupts at regular
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time intervals. Care must be taken if HAL_Delay() is called from a
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peripheral ISR process, the Tick interrupt line must have higher priority
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(numerically lower) than the peripheral interrupt. Otherwise the caller
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ISR process will be blocked.
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(++) functions affecting time base configurations are declared as __Weak
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to make override possible in case of other implementations in user file.
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@endverbatim
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* @{
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*/
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/**
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* @brief This function configures the Flash prefetch,
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* Configures time base source, NVIC and Low level hardware
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* @note This function is called at the beginning of program after reset and before
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* the clock configuration
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* @note The time base configuration is based on HSI clock when exiting from Reset.
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* Once done, time base tick start incrementing.
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* In the default implementation,Systick is used as source of time base.
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* The tick variable is incremented each 1ms in its ISR.
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_Init(void)
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{
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/* Configure Flash prefetch */
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#if (PREFETCH_ENABLE != 0)
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__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
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#endif /* PREFETCH_ENABLE */
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/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
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HAL_InitTick(TICK_INT_PRIORITY);
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/* Init the low level hardware */
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HAL_MspInit();
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/* Return function status */
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return HAL_OK;
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}
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/**
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* @brief This function de-Initialize common part of the HAL and stops the SysTick
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* of time base.
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* @note This function is optional.
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_DeInit(void)
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{
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/* Reset of all peripherals */
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__HAL_RCC_APB1_FORCE_RESET();
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__HAL_RCC_APB1_RELEASE_RESET();
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__HAL_RCC_APB2_FORCE_RESET();
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__HAL_RCC_APB2_RELEASE_RESET();
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__HAL_RCC_AHB_FORCE_RESET();
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__HAL_RCC_AHB_RELEASE_RESET();
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/* De-Init the low level hardware */
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HAL_MspDeInit();
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/* Return function status */
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return HAL_OK;
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}
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/**
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* @brief Initialize the MSP.
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* @retval None
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*/
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__weak void HAL_MspInit(void)
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{
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/* NOTE : This function should not be modified, when the callback is needed,
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the HAL_MspInit could be implemented in the user file
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*/
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}
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/**
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* @brief DeInitializes the MSP.
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* @retval None
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*/
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__weak void HAL_MspDeInit(void)
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{
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/* NOTE : This function should not be modified, when the callback is needed,
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the HAL_MspDeInit could be implemented in the user file
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*/
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}
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/**
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* @brief This function configures the source of the time base.
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* The time source is configured to have 1ms time base with a dedicated
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* Tick interrupt priority.
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* @note This function is called automatically at the beginning of program after
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* reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
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* @note In the default implementation, SysTick timer is the source of time base.
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* It is used to generate interrupts at regular time intervals.
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||||
* Care must be taken if HAL_Delay() is called from a peripheral ISR process,
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||||
* The SysTick interrupt must have higher priority (numerically lower)
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||||
* than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
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||||
* The function is declared as __Weak to be overwritten in case of other
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* implementation in user file.
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* @param TickPriority Tick interrupt priority.
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* @retval HAL status
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*/
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__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
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{
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/*Configure the SysTick to have interrupt in 1ms time basis*/
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if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
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{
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return HAL_ERROR;
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}
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/* Configure the SysTick IRQ priority */
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if (TickPriority < (1UL << __NVIC_PRIO_BITS))
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{
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HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
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uwTickPrio = TickPriority;
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}
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else
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{
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return HAL_ERROR;
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}
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/* Return function status */
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return HAL_OK;
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}
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/**
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* @}
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*/
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/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
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* @brief HAL Control functions
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*
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@verbatim
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===============================================================================
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||||
##### HAL Control functions #####
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||||
===============================================================================
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||||
[..] This section provides functions allowing to:
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(+) Provide a tick value in millisecond
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(+) Provide a blocking delay in millisecond
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(+) Suspend the time base source interrupt
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(+) Resume the time base source interrupt
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(+) Get the HAL API driver version
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(+) Get the device identifier
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(+) Get the device revision identifier
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(+) Enable/Disable Debug module during Sleep mode
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(+) Enable/Disable Debug module during STOP mode
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(+) Enable/Disable Debug module during STANDBY mode
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@endverbatim
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* @{
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*/
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/**
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* @brief This function is called to increment a global variable "uwTick"
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* used as application time base.
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* @note In the default implementation, this variable is incremented each 1ms
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* in SysTick ISR.
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* @note This function is declared as __weak to be overwritten in case of other
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* implementations in user file.
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* @retval None
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*/
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__weak void HAL_IncTick(void)
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{
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uwTick += uwTickFreq;
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}
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/**
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||||
* @brief Provides a tick value in millisecond.
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||||
* @note This function is declared as __weak to be overwritten in case of other
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||||
* implementations in user file.
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* @retval tick value
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||||
*/
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__weak uint32_t HAL_GetTick(void)
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{
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return uwTick;
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}
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/**
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* @brief This function returns a tick priority.
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* @retval tick priority
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*/
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uint32_t HAL_GetTickPrio(void)
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{
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return uwTickPrio;
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}
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/**
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* @brief Set new tick Freq.
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* @retval status
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*/
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HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
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{
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HAL_StatusTypeDef status = HAL_OK;
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HAL_TickFreqTypeDef prevTickFreq;
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assert_param(IS_TICKFREQ(Freq));
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||||
if (uwTickFreq != Freq)
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||||
{
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||||
/* Back up uwTickFreq frequency */
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||||
prevTickFreq = uwTickFreq;
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||||
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||||
/* Update uwTickFreq global variable used by HAL_InitTick() */
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uwTickFreq = Freq;
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||||
|
||||
/* Apply the new tick Freq */
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||||
status = HAL_InitTick(uwTickPrio);
|
||||
|
||||
if (status != HAL_OK)
|
||||
{
|
||||
/* Restore previous tick frequency */
|
||||
uwTickFreq = prevTickFreq;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief return tick frequency.
|
||||
* @retval Tick frequency.
|
||||
* Value of @ref HAL_TickFreqTypeDef.
|
||||
*/
|
||||
HAL_TickFreqTypeDef HAL_GetTickFreq(void)
|
||||
{
|
||||
return uwTickFreq;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function provides accurate delay (in milliseconds) based
|
||||
* on variable incremented.
|
||||
* @note In the default implementation , SysTick timer is the source of time base.
|
||||
* It is used to generate interrupts at regular time intervals where uwTick
|
||||
* is incremented.
|
||||
* @note ThiS function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @param Delay specifies the delay time length, in milliseconds.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_Delay(uint32_t Delay)
|
||||
{
|
||||
uint32_t tickstart = HAL_GetTick();
|
||||
uint32_t wait = Delay;
|
||||
|
||||
/* Add a freq to guarantee minimum wait */
|
||||
if (wait < HAL_MAX_DELAY)
|
||||
{
|
||||
wait += (uint32_t)(uwTickFreq);
|
||||
}
|
||||
|
||||
while((HAL_GetTick() - tickstart) < wait)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Suspend Tick increment.
|
||||
* @note In the default implementation , SysTick timer is the source of time base. It is
|
||||
* used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
|
||||
* is called, the the SysTick interrupt will be disabled and so Tick increment
|
||||
* is suspended.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_SuspendTick(void)
|
||||
|
||||
{
|
||||
/* Disable SysTick Interrupt */
|
||||
CLEAR_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resume Tick increment.
|
||||
* @note In the default implementation , SysTick timer is the source of time base. It is
|
||||
* used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
|
||||
* is called, the the SysTick interrupt will be enabled and so Tick increment
|
||||
* is resumed.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_ResumeTick(void)
|
||||
{
|
||||
/* Enable SysTick Interrupt */
|
||||
SET_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This method returns the HAL revision
|
||||
* @retval version 0xXYZR (8bits for each decimal, R for RC)
|
||||
*/
|
||||
uint32_t HAL_GetHalVersion(void)
|
||||
{
|
||||
return __STM32F0xx_HAL_VERSION;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the device revision identifier.
|
||||
* @retval Device revision identifier
|
||||
*/
|
||||
uint32_t HAL_GetREVID(void)
|
||||
{
|
||||
return((DBGMCU->IDCODE) >> 16U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the device identifier.
|
||||
* @retval Device identifier
|
||||
*/
|
||||
uint32_t HAL_GetDEVID(void)
|
||||
{
|
||||
return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns first word of the unique device identifier (UID based on 96 bits)
|
||||
* @retval Device identifier
|
||||
*/
|
||||
uint32_t HAL_GetUIDw0(void)
|
||||
{
|
||||
return(READ_REG(*((uint32_t *)UID_BASE)));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns second word of the unique device identifier (UID based on 96 bits)
|
||||
* @retval Device identifier
|
||||
*/
|
||||
uint32_t HAL_GetUIDw1(void)
|
||||
{
|
||||
return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns third word of the unique device identifier (UID based on 96 bits)
|
||||
* @retval Device identifier
|
||||
*/
|
||||
uint32_t HAL_GetUIDw2(void)
|
||||
{
|
||||
return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the Debug Module during STOP mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_EnableDBGStopMode(void)
|
||||
{
|
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Debug Module during STOP mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_DisableDBGStopMode(void)
|
||||
{
|
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the Debug Module during STANDBY mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_EnableDBGStandbyMode(void)
|
||||
{
|
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Debug Module during STANDBY mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_DisableDBGStandbyMode(void)
|
||||
{
|
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
2490
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c
Normal file
2490
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c
Normal file
File diff suppressed because it is too large
Load Diff
189
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.c
Normal file
189
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.c
Normal file
@@ -0,0 +1,189 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_adc_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Analog to Digital Convertor (ADC)
|
||||
* peripheral:
|
||||
* + Peripheral Control functions
|
||||
* Other functions (generic functions) are available in file
|
||||
* "stm32f0xx_hal_adc.c".
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
[..]
|
||||
(@) Sections "ADC peripheral features" and "How to use this driver" are
|
||||
available in file of generic functions "stm32l1xx_hal_adc.c".
|
||||
[..]
|
||||
@endverbatim
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ADCEx ADCEx
|
||||
* @brief ADC HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_ADC_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @defgroup ADCEx_Private_Constants ADCEx Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Fixed timeout values for ADC calibration, enable settling time, disable */
|
||||
/* settling time. */
|
||||
/* Values defined to be higher than worst cases: low clock frequency, */
|
||||
/* maximum prescaler. */
|
||||
/* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
|
||||
/* prescaler 4. */
|
||||
/* Unit: ms */
|
||||
#define ADC_DISABLE_TIMEOUT 2
|
||||
#define ADC_CALIBRATION_TIMEOUT 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ADCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions
|
||||
* @brief Extended Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Perform the ADC calibration.
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Perform an ADC automatic self-calibration
|
||||
* Calibration prerequisite: ADC must be disabled (execute this
|
||||
* function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
|
||||
* @note Calibration factor can be read after calibration, using function
|
||||
* HAL_ADC_GetValue() (value on 7 bits: from DR[6;0]).
|
||||
* @param hadc ADC handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
|
||||
{
|
||||
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
|
||||
uint32_t tickstart = 0U;
|
||||
uint32_t backup_setting_adc_dma_transfer = 0; /* Note: Variable not declared as volatile because register read is already declared as volatile */
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hadc);
|
||||
|
||||
/* Calibration prerequisite: ADC must be disabled. */
|
||||
if (ADC_IS_ENABLE(hadc) == RESET)
|
||||
{
|
||||
/* Set ADC state */
|
||||
ADC_STATE_CLR_SET(hadc->State,
|
||||
HAL_ADC_STATE_REG_BUSY,
|
||||
HAL_ADC_STATE_BUSY_INTERNAL);
|
||||
|
||||
/* Disable ADC DMA transfer request during calibration */
|
||||
/* Note: Specificity of this STM32 series: Calibration factor is */
|
||||
/* available in data register and also transferred by DMA. */
|
||||
/* To not insert ADC calibration factor among ADC conversion data */
|
||||
/* in array variable, DMA transfer must be disabled during */
|
||||
/* calibration. */
|
||||
backup_setting_adc_dma_transfer = READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG);
|
||||
CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG);
|
||||
|
||||
/* Start ADC calibration */
|
||||
hadc->Instance->CR |= ADC_CR_ADCAL;
|
||||
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait for calibration completion */
|
||||
while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL))
|
||||
{
|
||||
if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
|
||||
{
|
||||
/* New check to avoid false timeout detection in case of preemption */
|
||||
if(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL))
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
ADC_STATE_CLR_SET(hadc->State,
|
||||
HAL_ADC_STATE_BUSY_INTERNAL,
|
||||
HAL_ADC_STATE_ERROR_INTERNAL);
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hadc);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Restore ADC DMA transfer request after calibration */
|
||||
SET_BIT(hadc->Instance->CFGR1, backup_setting_adc_dma_transfer);
|
||||
|
||||
/* Set ADC state */
|
||||
ADC_STATE_CLR_SET(hadc->State,
|
||||
HAL_ADC_STATE_BUSY_INTERNAL,
|
||||
HAL_ADC_STATE_READY);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
||||
|
||||
tmp_hal_status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hadc);
|
||||
|
||||
/* Return function status */
|
||||
return tmp_hal_status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_ADC_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
2432
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c
Normal file
2432
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c
Normal file
File diff suppressed because it is too large
Load Diff
997
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cec.c
Normal file
997
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cec.c
Normal file
@@ -0,0 +1,997 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_cec.c
|
||||
* @author MCD Application Team
|
||||
* @brief CEC HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the High Definition Multimedia Interface
|
||||
* Consumer Electronics Control Peripheral (CEC).
|
||||
* + Initialization and de-initialization function
|
||||
* + IO operation function
|
||||
* + Peripheral Control function
|
||||
*
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### How to use this driver #####
|
||||
===============================================================================
|
||||
[..]
|
||||
The CEC HAL driver can be used as follow:
|
||||
|
||||
(#) Declare a CEC_HandleTypeDef handle structure.
|
||||
(#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
|
||||
(##) Enable the CEC interface clock.
|
||||
(##) CEC pins configuration:
|
||||
(+++) Enable the clock for the CEC GPIOs.
|
||||
(+++) Configure these CEC pins as alternate function pull-up.
|
||||
(##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
|
||||
and HAL_CEC_Receive_IT() APIs):
|
||||
(+++) Configure the CEC interrupt priority.
|
||||
(+++) Enable the NVIC CEC IRQ handle.
|
||||
(+++) The specific CEC interrupts (Transmission complete interrupt,
|
||||
RXNE interrupt and Error Interrupts) will be managed using the macros
|
||||
__HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
|
||||
and receive process.
|
||||
|
||||
(#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in
|
||||
in case of Bit Rising Error, Error-Bit generation conditions, device logical
|
||||
address and Listen mode in the hcec Init structure.
|
||||
|
||||
(#) Initialize the CEC registers by calling the HAL_CEC_Init() API.
|
||||
|
||||
[..]
|
||||
(@) This API (HAL_CEC_Init()) configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
|
||||
by calling the customed HAL_CEC_MspInit() API.
|
||||
*** Callback registration ***
|
||||
=============================================
|
||||
|
||||
The compilation define USE_HAL_CEC_REGISTER_CALLBACKS when set to 1
|
||||
allows the user to configure dynamically the driver callbacks.
|
||||
Use Functions HAL_CEC_RegisterCallback() or HAL_CEC_RegisterXXXCallback()
|
||||
to register an interrupt callback.
|
||||
|
||||
Function HAL_CEC_RegisterCallback() allows to register following callbacks:
|
||||
(+) TxCpltCallback : Tx Transfer completed callback.
|
||||
(+) ErrorCallback : callback for error detection.
|
||||
(+) MspInitCallback : CEC MspInit.
|
||||
(+) MspDeInitCallback : CEC MspDeInit.
|
||||
This function takes as parameters the HAL peripheral handle, the Callback ID
|
||||
and a pointer to the user callback function.
|
||||
|
||||
For specific callback HAL_CEC_RxCpltCallback use dedicated register callbacks
|
||||
HAL_CEC_RegisterRxCpltCallback().
|
||||
|
||||
Use function HAL_CEC_UnRegisterCallback() to reset a callback to the default
|
||||
weak function.
|
||||
HAL_CEC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
|
||||
and the Callback ID.
|
||||
This function allows to reset following callbacks:
|
||||
(+) TxCpltCallback : Tx Transfer completed callback.
|
||||
(+) ErrorCallback : callback for error detection.
|
||||
(+) MspInitCallback : CEC MspInit.
|
||||
(+) MspDeInitCallback : CEC MspDeInit.
|
||||
|
||||
For callback HAL_CEC_RxCpltCallback use dedicated unregister callback :
|
||||
HAL_CEC_UnRegisterRxCpltCallback().
|
||||
|
||||
By default, after the HAL_CEC_Init() and when the state is HAL_CEC_STATE_RESET
|
||||
all callbacks are set to the corresponding weak functions :
|
||||
examples HAL_CEC_TxCpltCallback() , HAL_CEC_RxCpltCallback().
|
||||
Exception done for MspInit and MspDeInit functions that are
|
||||
reset to the legacy weak function in the HAL_CEC_Init()/ HAL_CEC_DeInit() only when
|
||||
these callbacks are null (not registered beforehand).
|
||||
if not, MspInit or MspDeInit are not null, the HAL_CEC_Init() / HAL_CEC_DeInit()
|
||||
keep and use the user MspInit/MspDeInit functions (registered beforehand)
|
||||
|
||||
Callbacks can be registered/unregistered in HAL_CEC_STATE_READY state only.
|
||||
Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
|
||||
in HAL_CEC_STATE_READY or HAL_CEC_STATE_RESET state,
|
||||
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
|
||||
In that case first register the MspInit/MspDeInit user callbacks
|
||||
using HAL_CEC_RegisterCallback() before calling HAL_CEC_DeInit()
|
||||
or HAL_CEC_Init() function.
|
||||
|
||||
When the compilation define USE_HAL_CEC_REGISTER_CALLBACKS is set to 0 or
|
||||
not defined, the callback registration feature is not available and all callbacks
|
||||
are set to the corresponding weak functions.
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CEC CEC
|
||||
* @brief HAL CEC module driver
|
||||
* @{
|
||||
*/
|
||||
#ifdef HAL_CEC_MODULE_ENABLED
|
||||
#if defined (CEC)
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @defgroup CEC_Private_Constants CEC Private Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup CEC_Private_Functions CEC Private Functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CEC_Exported_Functions CEC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Configuration functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to initialize the CEC
|
||||
(+) The following parameters need to be configured:
|
||||
(++) SignalFreeTime
|
||||
(++) Tolerance
|
||||
(++) BRERxStop (RX stopped or not upon Bit Rising Error)
|
||||
(++) BREErrorBitGen (Error-Bit generation in case of Bit Rising Error)
|
||||
(++) LBPEErrorBitGen (Error-Bit generation in case of Long Bit Period Error)
|
||||
(++) BroadcastMsgNoErrorBitGen (Error-bit generation in case of broadcast message error)
|
||||
(++) SignalFreeTimeOption (SFT Timer start definition)
|
||||
(++) OwnAddress (CEC device address)
|
||||
(++) ListenMode
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the CEC mode according to the specified
|
||||
* parameters in the CEC_InitTypeDef and creates the associated handle .
|
||||
* @param hcec CEC handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
|
||||
{
|
||||
/* Check the CEC handle allocation */
|
||||
if ((hcec == NULL) || (hcec->Init.RxBuffer == NULL))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
|
||||
assert_param(IS_CEC_SIGNALFREETIME(hcec->Init.SignalFreeTime));
|
||||
assert_param(IS_CEC_TOLERANCE(hcec->Init.Tolerance));
|
||||
assert_param(IS_CEC_BRERXSTOP(hcec->Init.BRERxStop));
|
||||
assert_param(IS_CEC_BREERRORBITGEN(hcec->Init.BREErrorBitGen));
|
||||
assert_param(IS_CEC_LBPEERRORBITGEN(hcec->Init.LBPEErrorBitGen));
|
||||
assert_param(IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(hcec->Init.BroadcastMsgNoErrorBitGen));
|
||||
assert_param(IS_CEC_SFTOP(hcec->Init.SignalFreeTimeOption));
|
||||
assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode));
|
||||
assert_param(IS_CEC_OWN_ADDRESS(hcec->Init.OwnAddress));
|
||||
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
if (hcec->gState == HAL_CEC_STATE_RESET)
|
||||
{
|
||||
/* Allocate lock resource and initialize it */
|
||||
hcec->Lock = HAL_UNLOCKED;
|
||||
|
||||
hcec->TxCpltCallback = HAL_CEC_TxCpltCallback; /* Legacy weak TxCpltCallback */
|
||||
hcec->RxCpltCallback = HAL_CEC_RxCpltCallback; /* Legacy weak RxCpltCallback */
|
||||
hcec->ErrorCallback = HAL_CEC_ErrorCallback; /* Legacy weak ErrorCallback */
|
||||
|
||||
if (hcec->MspInitCallback == NULL)
|
||||
{
|
||||
hcec->MspInitCallback = HAL_CEC_MspInit; /* Legacy weak MspInit */
|
||||
}
|
||||
|
||||
/* Init the low level hardware */
|
||||
hcec->MspInitCallback(hcec);
|
||||
}
|
||||
#else
|
||||
if (hcec->gState == HAL_CEC_STATE_RESET)
|
||||
{
|
||||
/* Allocate lock resource and initialize it */
|
||||
hcec->Lock = HAL_UNLOCKED;
|
||||
/* Init the low level hardware : GPIO, CLOCK */
|
||||
HAL_CEC_MspInit(hcec);
|
||||
}
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
|
||||
hcec->gState = HAL_CEC_STATE_BUSY;
|
||||
|
||||
/* Disable the Peripheral */
|
||||
__HAL_CEC_DISABLE(hcec);
|
||||
|
||||
/* Write to CEC Control Register */
|
||||
hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop | \
|
||||
hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | \
|
||||
hcec->Init.BroadcastMsgNoErrorBitGen | \
|
||||
hcec->Init.SignalFreeTimeOption | ((uint32_t)(hcec->Init.OwnAddress) << 16U) | \
|
||||
hcec->Init.ListenMode;
|
||||
|
||||
/* Enable the following CEC Transmission/Reception interrupts as
|
||||
* well as the following CEC Transmission/Reception Errors interrupts
|
||||
* Rx Byte Received IT
|
||||
* End of Reception IT
|
||||
* Rx overrun
|
||||
* Rx bit rising error
|
||||
* Rx short bit period error
|
||||
* Rx long bit period error
|
||||
* Rx missing acknowledge
|
||||
* Tx Byte Request IT
|
||||
* End of Transmission IT
|
||||
* Tx Missing Acknowledge IT
|
||||
* Tx-Error IT
|
||||
* Tx-Buffer Underrun IT
|
||||
* Tx arbitration lost */
|
||||
__HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR | CEC_IT_RXEND | CEC_IER_RX_ALL_ERR | CEC_IT_TXBR | CEC_IT_TXEND |
|
||||
CEC_IER_TX_ALL_ERR);
|
||||
|
||||
/* Enable the CEC Peripheral */
|
||||
__HAL_CEC_ENABLE(hcec);
|
||||
|
||||
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
|
||||
hcec->gState = HAL_CEC_STATE_READY;
|
||||
hcec->RxState = HAL_CEC_STATE_READY;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the CEC peripheral
|
||||
* @param hcec CEC handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
|
||||
{
|
||||
/* Check the CEC handle allocation */
|
||||
if (hcec == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
|
||||
|
||||
hcec->gState = HAL_CEC_STATE_BUSY;
|
||||
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
if (hcec->MspDeInitCallback == NULL)
|
||||
{
|
||||
hcec->MspDeInitCallback = HAL_CEC_MspDeInit; /* Legacy weak MspDeInit */
|
||||
}
|
||||
|
||||
/* DeInit the low level hardware */
|
||||
hcec->MspDeInitCallback(hcec);
|
||||
|
||||
#else
|
||||
/* DeInit the low level hardware */
|
||||
HAL_CEC_MspDeInit(hcec);
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
|
||||
/* Disable the Peripheral */
|
||||
__HAL_CEC_DISABLE(hcec);
|
||||
|
||||
/* Clear Flags */
|
||||
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND | CEC_FLAG_TXBR | CEC_FLAG_RXBR | CEC_FLAG_RXEND | CEC_ISR_ALL_ERROR);
|
||||
|
||||
/* Disable the following CEC Transmission/Reception interrupts as
|
||||
* well as the following CEC Transmission/Reception Errors interrupts
|
||||
* Rx Byte Received IT
|
||||
* End of Reception IT
|
||||
* Rx overrun
|
||||
* Rx bit rising error
|
||||
* Rx short bit period error
|
||||
* Rx long bit period error
|
||||
* Rx missing acknowledge
|
||||
* Tx Byte Request IT
|
||||
* End of Transmission IT
|
||||
* Tx Missing Acknowledge IT
|
||||
* Tx-Error IT
|
||||
* Tx-Buffer Underrun IT
|
||||
* Tx arbitration lost */
|
||||
__HAL_CEC_DISABLE_IT(hcec, CEC_IT_RXBR | CEC_IT_RXEND | CEC_IER_RX_ALL_ERR | CEC_IT_TXBR | CEC_IT_TXEND |
|
||||
CEC_IER_TX_ALL_ERR);
|
||||
|
||||
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
|
||||
hcec->gState = HAL_CEC_STATE_RESET;
|
||||
hcec->RxState = HAL_CEC_STATE_RESET;
|
||||
|
||||
/* Process Unlock */
|
||||
__HAL_UNLOCK(hcec);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the Own Address of the CEC device
|
||||
* @param hcec CEC handle
|
||||
* @param CEC_OwnAddress The CEC own address.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CEC_OWN_ADDRESS(CEC_OwnAddress));
|
||||
|
||||
if ((hcec->gState == HAL_CEC_STATE_READY) && (hcec->RxState == HAL_CEC_STATE_READY))
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hcec);
|
||||
|
||||
hcec->gState = HAL_CEC_STATE_BUSY;
|
||||
|
||||
/* Disable the Peripheral */
|
||||
__HAL_CEC_DISABLE(hcec);
|
||||
|
||||
if (CEC_OwnAddress != CEC_OWN_ADDRESS_NONE)
|
||||
{
|
||||
hcec->Instance->CFGR |= ((uint32_t)CEC_OwnAddress << 16);
|
||||
}
|
||||
else
|
||||
{
|
||||
hcec->Instance->CFGR &= ~(CEC_CFGR_OAR);
|
||||
}
|
||||
|
||||
hcec->gState = HAL_CEC_STATE_READY;
|
||||
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hcec);
|
||||
|
||||
/* Enable the Peripheral */
|
||||
__HAL_CEC_ENABLE(hcec);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief CEC MSP Init
|
||||
* @param hcec CEC handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcec);
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_CEC_MspInit can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief CEC MSP DeInit
|
||||
* @param hcec CEC handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcec);
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_CEC_MspDeInit can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief Register a User CEC Callback
|
||||
* To be used instead of the weak predefined callback
|
||||
* @param hcec CEC handle
|
||||
* @param CallbackID ID of the callback to be registered
|
||||
* This parameter can be one of the following values:
|
||||
* @arg HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
|
||||
* @arg HAL_CEC_ERROR_CB_ID Error callback ID
|
||||
* @arg HAL_CEC_MSPINIT_CB_ID MspInit callback ID
|
||||
* @arg HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
|
||||
* @param pCallback pointer to the Callback function
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID,
|
||||
pCEC_CallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
if (pCallback == NULL)
|
||||
{
|
||||
/* Update the error code */
|
||||
hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hcec);
|
||||
|
||||
if (hcec->gState == HAL_CEC_STATE_READY)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_CEC_TX_CPLT_CB_ID :
|
||||
hcec->TxCpltCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_CEC_ERROR_CB_ID :
|
||||
hcec->ErrorCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_CEC_MSPINIT_CB_ID :
|
||||
hcec->MspInitCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_CEC_MSPDEINIT_CB_ID :
|
||||
hcec->MspDeInitCallback = pCallback;
|
||||
break;
|
||||
|
||||
default :
|
||||
/* Update the error code */
|
||||
hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else if (hcec->gState == HAL_CEC_STATE_RESET)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_CEC_MSPINIT_CB_ID :
|
||||
hcec->MspInitCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_CEC_MSPDEINIT_CB_ID :
|
||||
hcec->MspDeInitCallback = pCallback;
|
||||
break;
|
||||
|
||||
default :
|
||||
/* Update the error code */
|
||||
hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update the error code */
|
||||
hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hcec);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unregister an CEC Callback
|
||||
* CEC callback is redirected to the weak predefined callback
|
||||
* @param hcec uart handle
|
||||
* @param CallbackID ID of the callback to be unregistered
|
||||
* This parameter can be one of the following values:
|
||||
* @arg HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
|
||||
* @arg HAL_CEC_ERROR_CB_ID Error callback ID
|
||||
* @arg HAL_CEC_MSPINIT_CB_ID MspInit callback ID
|
||||
* @arg HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
|
||||
* @retval status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hcec);
|
||||
|
||||
if (hcec->gState == HAL_CEC_STATE_READY)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_CEC_TX_CPLT_CB_ID :
|
||||
hcec->TxCpltCallback = HAL_CEC_TxCpltCallback; /* Legacy weak TxCpltCallback */
|
||||
break;
|
||||
|
||||
case HAL_CEC_ERROR_CB_ID :
|
||||
hcec->ErrorCallback = HAL_CEC_ErrorCallback; /* Legacy weak ErrorCallback */
|
||||
break;
|
||||
|
||||
case HAL_CEC_MSPINIT_CB_ID :
|
||||
hcec->MspInitCallback = HAL_CEC_MspInit;
|
||||
break;
|
||||
|
||||
case HAL_CEC_MSPDEINIT_CB_ID :
|
||||
hcec->MspDeInitCallback = HAL_CEC_MspDeInit;
|
||||
break;
|
||||
|
||||
default :
|
||||
/* Update the error code */
|
||||
hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else if (hcec->gState == HAL_CEC_STATE_RESET)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_CEC_MSPINIT_CB_ID :
|
||||
hcec->MspInitCallback = HAL_CEC_MspInit;
|
||||
break;
|
||||
|
||||
case HAL_CEC_MSPDEINIT_CB_ID :
|
||||
hcec->MspDeInitCallback = HAL_CEC_MspDeInit;
|
||||
break;
|
||||
|
||||
default :
|
||||
/* Update the error code */
|
||||
hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update the error code */
|
||||
hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hcec);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Register CEC RX complete Callback
|
||||
* To be used instead of the weak HAL_CEC_RxCpltCallback() predefined callback
|
||||
* @param hcec CEC handle
|
||||
* @param pCallback pointer to the Rx transfer compelete Callback function
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback(CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
if (pCallback == NULL)
|
||||
{
|
||||
/* Update the error code */
|
||||
hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hcec);
|
||||
|
||||
if (HAL_CEC_STATE_READY == hcec->RxState)
|
||||
{
|
||||
hcec->RxCpltCallback = pCallback;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update the error code */
|
||||
hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hcec);
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief UnRegister CEC RX complete Callback
|
||||
* CEC RX complete Callback is redirected to the weak HAL_CEC_RxCpltCallback() predefined callback
|
||||
* @param hcec CEC handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hcec);
|
||||
|
||||
if (HAL_CEC_STATE_READY == hcec->RxState)
|
||||
{
|
||||
hcec->RxCpltCallback = HAL_CEC_RxCpltCallback; /* Legacy weak CEC RxCpltCallback */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update the error code */
|
||||
hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hcec);
|
||||
return status;
|
||||
}
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @brief CEC Transmit/Receive functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
This subsection provides a set of functions allowing to manage the CEC data transfers.
|
||||
|
||||
(#) The CEC handle must contain the initiator (TX side) and the destination (RX side)
|
||||
logical addresses (4-bit long addresses, 0xF for broadcast messages destination)
|
||||
|
||||
(#) The communication is performed using Interrupts.
|
||||
These API's return the HAL status.
|
||||
The end of the data processing will be indicated through the
|
||||
dedicated CEC IRQ when using Interrupt mode.
|
||||
The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks
|
||||
will be executed respectively at the end of the transmit or Receive process
|
||||
The HAL_CEC_ErrorCallback() user callback will be executed when a communication
|
||||
error is detected
|
||||
|
||||
(#) API's with Interrupt are :
|
||||
(+) HAL_CEC_Transmit_IT()
|
||||
(+) HAL_CEC_IRQHandler()
|
||||
|
||||
(#) A set of User Callbacks are provided:
|
||||
(+) HAL_CEC_TxCpltCallback()
|
||||
(+) HAL_CEC_RxCpltCallback()
|
||||
(+) HAL_CEC_ErrorCallback()
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Send data in interrupt mode
|
||||
* @param hcec CEC handle
|
||||
* @param InitiatorAddress Initiator address
|
||||
* @param DestinationAddress destination logical address
|
||||
* @param pData pointer to input byte data buffer
|
||||
* @param Size amount of data to be sent in bytes (without counting the header).
|
||||
* 0 means only the header is sent (ping operation).
|
||||
* Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress,
|
||||
const uint8_t *pData, uint32_t Size)
|
||||
{
|
||||
/* if the peripheral isn't already busy and if there is no previous transmission
|
||||
already pending due to arbitration lost */
|
||||
if (hcec->gState == HAL_CEC_STATE_READY)
|
||||
{
|
||||
if ((pData == NULL) && (Size > 0U))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
assert_param(IS_CEC_ADDRESS(DestinationAddress));
|
||||
assert_param(IS_CEC_ADDRESS(InitiatorAddress));
|
||||
assert_param(IS_CEC_MSGSIZE(Size));
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hcec);
|
||||
hcec->pTxBuffPtr = pData;
|
||||
hcec->gState = HAL_CEC_STATE_BUSY_TX;
|
||||
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
|
||||
|
||||
/* initialize the number of bytes to send,
|
||||
* 0 means only one header is sent (ping operation) */
|
||||
hcec->TxXferCount = (uint16_t)Size;
|
||||
|
||||
/* in case of no payload (Size = 0), sender is only pinging the system;
|
||||
Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
|
||||
if (Size == 0U)
|
||||
{
|
||||
__HAL_CEC_LAST_BYTE_TX_SET(hcec);
|
||||
}
|
||||
|
||||
/* send header block */
|
||||
hcec->Instance->TXDR = (uint32_t)(((uint32_t)InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress);
|
||||
|
||||
/* Set TX Start of Message (TXSOM) bit */
|
||||
__HAL_CEC_FIRST_BYTE_TX_SET(hcec);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hcec);
|
||||
|
||||
return HAL_OK;
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get size of the received frame.
|
||||
* @param hcec CEC handle
|
||||
* @retval Frame size
|
||||
*/
|
||||
uint32_t HAL_CEC_GetLastReceivedFrameSize(const CEC_HandleTypeDef *hcec)
|
||||
{
|
||||
return hcec->RxXferSize;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Change Rx Buffer.
|
||||
* @param hcec CEC handle
|
||||
* @param Rxbuffer Rx Buffer
|
||||
* @note This function can be called only inside the HAL_CEC_RxCpltCallback()
|
||||
* @retval Frame size
|
||||
*/
|
||||
void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer)
|
||||
{
|
||||
hcec->Init.RxBuffer = Rxbuffer;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles CEC interrupt requests.
|
||||
* @param hcec CEC handle
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
|
||||
{
|
||||
|
||||
/* save interrupts register for further error or interrupts handling purposes */
|
||||
uint32_t itflag;
|
||||
itflag = hcec->Instance->ISR;
|
||||
|
||||
|
||||
/* ----------------------------Arbitration Lost Management----------------------------------*/
|
||||
/* CEC TX arbitration error interrupt occurred --------------------------------------*/
|
||||
if (HAL_IS_BIT_SET(itflag, CEC_FLAG_ARBLST))
|
||||
{
|
||||
hcec->ErrorCode = HAL_CEC_ERROR_ARBLST;
|
||||
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST);
|
||||
}
|
||||
|
||||
/* ----------------------------Rx Management----------------------------------*/
|
||||
/* CEC RX byte received interrupt ---------------------------------------------------*/
|
||||
if (HAL_IS_BIT_SET(itflag, CEC_FLAG_RXBR))
|
||||
{
|
||||
/* reception is starting */
|
||||
hcec->RxState = HAL_CEC_STATE_BUSY_RX;
|
||||
hcec->RxXferSize++;
|
||||
/* read received byte */
|
||||
*hcec->Init.RxBuffer = (uint8_t) hcec->Instance->RXDR;
|
||||
hcec->Init.RxBuffer++;
|
||||
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR);
|
||||
}
|
||||
|
||||
/* CEC RX end received interrupt ---------------------------------------------------*/
|
||||
if (HAL_IS_BIT_SET(itflag, CEC_FLAG_RXEND))
|
||||
{
|
||||
/* clear IT */
|
||||
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND);
|
||||
|
||||
/* Rx process is completed, restore hcec->RxState to Ready */
|
||||
hcec->RxState = HAL_CEC_STATE_READY;
|
||||
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
|
||||
hcec->Init.RxBuffer -= hcec->RxXferSize;
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1U)
|
||||
hcec->RxCpltCallback(hcec, hcec->RxXferSize);
|
||||
#else
|
||||
HAL_CEC_RxCpltCallback(hcec, hcec->RxXferSize);
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
hcec->RxXferSize = 0U;
|
||||
}
|
||||
|
||||
/* ----------------------------Tx Management----------------------------------*/
|
||||
/* CEC TX byte request interrupt ------------------------------------------------*/
|
||||
if (HAL_IS_BIT_SET(itflag, CEC_FLAG_TXBR))
|
||||
{
|
||||
--hcec->TxXferCount;
|
||||
if (hcec->TxXferCount == 0U)
|
||||
{
|
||||
/* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
|
||||
__HAL_CEC_LAST_BYTE_TX_SET(hcec);
|
||||
}
|
||||
/* In all cases transmit the byte */
|
||||
hcec->Instance->TXDR = (uint8_t) * hcec->pTxBuffPtr;
|
||||
hcec->pTxBuffPtr++;
|
||||
/* clear Tx-Byte request flag */
|
||||
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR);
|
||||
}
|
||||
|
||||
/* CEC TX end interrupt ------------------------------------------------*/
|
||||
if (HAL_IS_BIT_SET(itflag, CEC_FLAG_TXEND))
|
||||
{
|
||||
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND);
|
||||
|
||||
/* Tx process is ended, restore hcec->gState to Ready */
|
||||
hcec->gState = HAL_CEC_STATE_READY;
|
||||
/* Call the Process Unlocked before calling the Tx call back API to give the possibility to
|
||||
start again the Transmission under the Tx call back API */
|
||||
__HAL_UNLOCK(hcec);
|
||||
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1U)
|
||||
hcec->TxCpltCallback(hcec);
|
||||
#else
|
||||
HAL_CEC_TxCpltCallback(hcec);
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
}
|
||||
|
||||
/* ----------------------------Rx/Tx Error Management----------------------------------*/
|
||||
if ((itflag & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE | CEC_ISR_TXUDR |
|
||||
CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U)
|
||||
{
|
||||
hcec->ErrorCode = itflag;
|
||||
__HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR | HAL_CEC_ERROR_BRE | CEC_FLAG_LBPE | CEC_FLAG_SBPE |
|
||||
HAL_CEC_ERROR_RXACKE | HAL_CEC_ERROR_TXUDR | HAL_CEC_ERROR_TXERR | HAL_CEC_ERROR_TXACKE);
|
||||
|
||||
|
||||
if ((itflag & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE)) != 0U)
|
||||
{
|
||||
hcec->Init.RxBuffer -= hcec->RxXferSize;
|
||||
hcec->RxXferSize = 0U;
|
||||
hcec->RxState = HAL_CEC_STATE_READY;
|
||||
}
|
||||
else if (((itflag & CEC_ISR_ARBLST) == 0U) && ((itflag & (CEC_ISR_TXUDR | CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U))
|
||||
{
|
||||
/* Set the CEC state ready to be able to start again the process */
|
||||
hcec->gState = HAL_CEC_STATE_READY;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Nothing todo*/
|
||||
}
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1U)
|
||||
hcec->ErrorCallback(hcec);
|
||||
#else
|
||||
/* Error Call Back */
|
||||
HAL_CEC_ErrorCallback(hcec);
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Nothing todo*/
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Tx Transfer completed callback
|
||||
* @param hcec CEC handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcec);
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_CEC_TxCpltCallback can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Rx Transfer completed callback
|
||||
* @param hcec CEC handle
|
||||
* @param RxFrameSize Size of frame
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcec);
|
||||
UNUSED(RxFrameSize);
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_CEC_RxCpltCallback can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief CEC error callbacks
|
||||
* @param hcec CEC handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcec);
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_CEC_ErrorCallback can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control function
|
||||
* @brief CEC control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control function #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the CEC.
|
||||
(+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral.
|
||||
(+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral.
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief return the CEC state
|
||||
* @param hcec pointer to a CEC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified CEC module.
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_CEC_StateTypeDef HAL_CEC_GetState(const CEC_HandleTypeDef *hcec)
|
||||
{
|
||||
uint32_t temp1;
|
||||
uint32_t temp2;
|
||||
temp1 = hcec->gState;
|
||||
temp2 = hcec->RxState;
|
||||
|
||||
return (HAL_CEC_StateTypeDef)(temp1 | temp2);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the CEC error code
|
||||
* @param hcec pointer to a CEC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified CEC.
|
||||
* @retval CEC Error Code
|
||||
*/
|
||||
uint32_t HAL_CEC_GetError(const CEC_HandleTypeDef *hcec)
|
||||
{
|
||||
return hcec->ErrorCode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* CEC */
|
||||
#endif /* HAL_CEC_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
983
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_comp.c
Normal file
983
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_comp.c
Normal file
@@ -0,0 +1,983 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_comp.c
|
||||
* @author MCD Application Team
|
||||
* @brief COMP HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the COMP peripheral:
|
||||
* + Initialization/de-initialization functions
|
||||
* + Peripheral Control functions
|
||||
* + Peripheral State functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
================================================================================
|
||||
##### COMP Peripheral features #####
|
||||
================================================================================
|
||||
|
||||
[..]
|
||||
The STM32F0xx device family integrates up to 2 analog comparators COMP1 and COMP2:
|
||||
(+) The non inverting input and inverting input can be set to GPIO pins.
|
||||
|
||||
(+) The COMP output is available using HAL_COMP_GetOutputLevel()
|
||||
and can be set on GPIO pins.
|
||||
|
||||
(+) The COMP output can be redirected to embedded timers (TIM1, TIM2 and TIM3).
|
||||
|
||||
(+) The comparators COMP1 and COMP2 can be combined in window mode.
|
||||
|
||||
(+) The comparators have interrupt capability with wake-up
|
||||
from Sleep and Stop modes (through the EXTI controller):
|
||||
(++) COMP1 is internally connected to EXTI Line 21
|
||||
(++) COMP2 is internally connected to EXTI Line 22
|
||||
|
||||
(+) From the corresponding IRQ handler, the right interrupt source can be retrieved with the
|
||||
macros __HAL_COMP_COMP1_EXTI_GET_FLAG() and __HAL_COMP_COMP2_EXTI_GET_FLAG().
|
||||
|
||||
|
||||
##### How to use this driver #####
|
||||
================================================================================
|
||||
[..]
|
||||
This driver provides functions to configure and program the Comparators of STM32F05x, STM32F07x and STM32F09x devices.
|
||||
|
||||
To use the comparator, perform the following steps:
|
||||
|
||||
(#) Fill in the HAL_COMP_MspInit() to
|
||||
(++) Configure the comparator input in analog mode using HAL_GPIO_Init()
|
||||
(++) Configure the comparator output in alternate function mode using HAL_GPIO_Init() to map the comparator
|
||||
output to the GPIO pin
|
||||
(++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and
|
||||
selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator
|
||||
interrupt vector using HAL_NVIC_EnableIRQ() function.
|
||||
|
||||
(#) Configure the comparator using HAL_COMP_Init() function:
|
||||
(++) Select the inverting input (input minus)
|
||||
(++) Select the non inverting input (input plus)
|
||||
(++) Select the output polarity
|
||||
(++) Select the output redirection
|
||||
(++) Select the hysteresis level
|
||||
(++) Select the power mode
|
||||
(++) Select the event/interrupt mode
|
||||
(++) Select the window mode
|
||||
|
||||
-@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE() in order
|
||||
to access the comparator(s) registers.
|
||||
|
||||
(#) Enable the comparator using HAL_COMP_Start() function or HAL_COMP_Start_IT() function for interrupt mode.
|
||||
|
||||
(#) Use HAL_COMP_TriggerCallback() and/or HAL_COMP_GetOutputLevel() functions
|
||||
to manage comparator outputs (event/interrupt triggered and output level).
|
||||
|
||||
(#) Disable the comparator using HAL_COMP_Stop() or HAL_COMP_Stop_IT()
|
||||
function.
|
||||
|
||||
(#) De-initialize the comparator using HAL_COMP_DeInit() function.
|
||||
|
||||
(#) For safety purposes comparator(s) can be locked using HAL_COMP_Lock() function.
|
||||
Only a MCU reset can reset that protection.
|
||||
|
||||
*** Callback registration ***
|
||||
=============================================
|
||||
[..]
|
||||
|
||||
The compilation flag USE_HAL_COMP_REGISTER_CALLBACKS, when set to 1,
|
||||
allows the user to configure dynamically the driver callbacks.
|
||||
Use Functions HAL_COMP_RegisterCallback()
|
||||
to register an interrupt callback.
|
||||
[..]
|
||||
|
||||
Function HAL_COMP_RegisterCallback() allows to register following callbacks:
|
||||
(+) OperationCpltCallback : callback for End of operation.
|
||||
(+) ErrorCallback : callback for error detection.
|
||||
(+) MspInitCallback : callback for Msp Init.
|
||||
(+) MspDeInitCallback : callback for Msp DeInit.
|
||||
This function takes as parameters the HAL peripheral handle, the Callback ID
|
||||
and a pointer to the user callback function.
|
||||
[..]
|
||||
|
||||
Use function HAL_COMP_UnRegisterCallback to reset a callback to the default
|
||||
weak function.
|
||||
[..]
|
||||
|
||||
HAL_COMP_UnRegisterCallback takes as parameters the HAL peripheral handle,
|
||||
and the Callback ID.
|
||||
This function allows to reset following callbacks:
|
||||
(+) OperationCpltCallback : callback for End of operation.
|
||||
(+) ErrorCallback : callback for error detection.
|
||||
(+) MspInitCallback : callback for Msp Init.
|
||||
(+) MspDeInitCallback : callback for Msp DeInit.
|
||||
[..]
|
||||
|
||||
By default, after the HAL_COMP_Init() and when the state is HAL_COMP_STATE_RESET
|
||||
all callbacks are set to the corresponding weak functions:
|
||||
examples HAL_COMP_OperationCpltCallback(), HAL_COMP_ErrorCallback().
|
||||
Exception done for MspInit and MspDeInit functions that are
|
||||
reset to the legacy weak functions in the HAL_COMP_Init()/ HAL_COMP_DeInit() only when
|
||||
these callbacks are null (not registered beforehand).
|
||||
[..]
|
||||
|
||||
If MspInit or MspDeInit are not null, the HAL_COMP_Init()/ HAL_COMP_DeInit()
|
||||
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
|
||||
[..]
|
||||
|
||||
Callbacks can be registered/unregistered in HAL_COMP_STATE_READY state only.
|
||||
Exception done MspInit/MspDeInit functions that can be registered/unregistered
|
||||
in HAL_COMP_STATE_READY or HAL_COMP_STATE_RESET state,
|
||||
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
|
||||
[..]
|
||||
|
||||
Then, the user first registers the MspInit/MspDeInit user callbacks
|
||||
using HAL_COMP_RegisterCallback() before calling HAL_COMP_DeInit()
|
||||
or HAL_COMP_Init() function.
|
||||
[..]
|
||||
|
||||
When the compilation flag USE_HAL_COMP_REGISTER_CALLBACKS is set to 0 or
|
||||
not defined, the callback registration feature is not available and all callbacks
|
||||
are set to the corresponding weak functions.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/*
|
||||
Additional Tables:
|
||||
|
||||
Table 1. COMP Inputs for the STM32F05x, STM32F07x and STM32F09x devices
|
||||
+--------------------------------------------------+
|
||||
| | | COMP1 | COMP2 |
|
||||
|-----------------|----------------|---------------|
|
||||
| | 1/4 VREFINT | OK | OK |
|
||||
| | 1/2 VREFINT | OK | OK |
|
||||
| | 3/4 VREFINT | OK | OK |
|
||||
| Inverting Input | VREFINT | OK | OK |
|
||||
| | DAC1 OUT (PA4) | OK | OK |
|
||||
| | DAC2 OUT (PA5) | OK | OK |
|
||||
| | IO1 | PA0 | PA2 |
|
||||
|-----------------|----------------|-------|-------|
|
||||
| Non Inverting | | PA1 | PA3 |
|
||||
| Input | | | |
|
||||
+--------------------------------------------------+
|
||||
|
||||
Table 2. COMP Outputs for the STM32F05x, STM32F07x and STM32F09x devices
|
||||
+---------------+
|
||||
| COMP1 | COMP2 |
|
||||
|-------|-------|
|
||||
| PA0 | PA2 |
|
||||
| PA6 | PA7 |
|
||||
| PA11 | PA12 |
|
||||
+---------------+
|
||||
|
||||
Table 3. COMP Outputs redirection to embedded timers for the STM32F05x, STM32F07x and STM32F09x devices
|
||||
+---------------------------------+
|
||||
| COMP1 | COMP2 |
|
||||
|----------------|----------------|
|
||||
| TIM1 BKIN | TIM1 BKIN |
|
||||
| | |
|
||||
| TIM1 OCREFCLR | TIM1 OCREFCLR |
|
||||
| | |
|
||||
| TIM1 IC1 | TIM1 IC1 |
|
||||
| | |
|
||||
| TIM2 IC4 | TIM2 IC4 |
|
||||
| | |
|
||||
| TIM2 OCREFCLR | TIM2 OCREFCLR |
|
||||
| | |
|
||||
| TIM3 IC1 | TIM3 IC1 |
|
||||
| | |
|
||||
| TIM3 OCREFCLR | TIM3 OCREFCLR |
|
||||
+---------------------------------+
|
||||
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
#ifdef HAL_COMP_MODULE_ENABLED
|
||||
|
||||
#if defined (COMP1) || defined (COMP2)
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP COMP
|
||||
* @brief COMP HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup COMP_Private_Constants COMP Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Delay for COMP startup time. */
|
||||
/* Note: Delay required to reach propagation delay specification. */
|
||||
/* Literal set to maximum value (refer to device datasheet, */
|
||||
/* parameter "tSTART"). */
|
||||
/* Unit: us */
|
||||
#define COMP_DELAY_STARTUP_US (60U) /*!< Delay for COMP startup time */
|
||||
|
||||
/* CSR register reset value */
|
||||
#define COMP_CSR_RESET_VALUE (0x00000000U)
|
||||
/* CSR register masks */
|
||||
#define COMP_CSR_RESET_PARAMETERS_MASK (0x00003FFFU)
|
||||
#define COMP_CSR_UPDATE_PARAMETERS_MASK (0x00003FFEU)
|
||||
/* CSR COMPx non inverting input mask */
|
||||
#define COMP_CSR_COMPxNONINSEL_MASK ((uint16_t)COMP_CSR_COMP1SW1)
|
||||
/* CSR COMP2 shift */
|
||||
#define COMP_CSR_COMP1_SHIFT 0U
|
||||
#define COMP_CSR_COMP2_SHIFT 16U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup COMP_Exported_Functions COMP Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Configuration functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions to initialize and de-initialize comparators
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the COMP according to the specified
|
||||
* parameters in the COMP_InitTypeDef and create the associated handle.
|
||||
* @note If the selected comparator is locked, initialization can't be performed.
|
||||
* To unlock the configuration, perform a system reset.
|
||||
* @param hcomp COMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint32_t regshift = COMP_CSR_COMP1_SHIFT;
|
||||
|
||||
/* Check the COMP handle allocation and lock status */
|
||||
if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
assert_param(IS_COMP_INVERTINGINPUT(hcomp->Init.InvertingInput));
|
||||
assert_param(IS_COMP_NONINVERTINGINPUT(hcomp->Init.NonInvertingInput));
|
||||
assert_param(IS_COMP_OUTPUT(hcomp->Init.Output));
|
||||
assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol));
|
||||
assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis));
|
||||
assert_param(IS_COMP_MODE(hcomp->Init.Mode));
|
||||
|
||||
if(hcomp->Init.NonInvertingInput == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED)
|
||||
{
|
||||
assert_param(IS_COMP_DAC1SWITCH_INSTANCE(hcomp->Instance));
|
||||
}
|
||||
|
||||
if(hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLE)
|
||||
{
|
||||
assert_param(IS_COMP_WINDOWMODE_INSTANCE(hcomp->Instance));
|
||||
}
|
||||
|
||||
/* Init SYSCFG and the low level hardware to access comparators */
|
||||
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||||
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
||||
/* Init the COMP Callback settings */
|
||||
hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */
|
||||
|
||||
if (hcomp->MspInitCallback == NULL)
|
||||
{
|
||||
hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */
|
||||
}
|
||||
|
||||
/* Init the low level hardware */
|
||||
hcomp->MspInitCallback(hcomp);
|
||||
#else
|
||||
/* Init the low level hardware : SYSCFG to access comparators */
|
||||
HAL_COMP_MspInit(hcomp);
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
|
||||
if(hcomp->State == HAL_COMP_STATE_RESET)
|
||||
{
|
||||
/* Allocate lock resource and initialize it */
|
||||
hcomp->Lock = HAL_UNLOCKED;
|
||||
}
|
||||
|
||||
/* Change COMP peripheral state */
|
||||
hcomp->State = HAL_COMP_STATE_BUSY;
|
||||
|
||||
/* Set COMP parameters */
|
||||
/* Set COMPxINSEL bits according to hcomp->Init.InvertingInput value */
|
||||
/* Set COMPxOUTSEL bits according to hcomp->Init.Output value */
|
||||
/* Set COMPxPOL bit according to hcomp->Init.OutputPol value */
|
||||
/* Set COMPxHYST bits according to hcomp->Init.Hysteresis value */
|
||||
/* Set COMPxMODE bits according to hcomp->Init.Mode value */
|
||||
if(hcomp->Instance == COMP2)
|
||||
{
|
||||
regshift = COMP_CSR_COMP2_SHIFT;
|
||||
}
|
||||
MODIFY_REG(COMP->CSR,
|
||||
(COMP_CSR_COMPxINSEL | COMP_CSR_COMPxNONINSEL_MASK | \
|
||||
COMP_CSR_COMPxOUTSEL | COMP_CSR_COMPxPOL | \
|
||||
COMP_CSR_COMPxHYST | COMP_CSR_COMPxMODE) << regshift,
|
||||
(hcomp->Init.InvertingInput | \
|
||||
hcomp->Init.NonInvertingInput | \
|
||||
hcomp->Init.Output | \
|
||||
hcomp->Init.OutputPol | \
|
||||
hcomp->Init.Hysteresis | \
|
||||
hcomp->Init.Mode) << regshift);
|
||||
|
||||
if(hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLE)
|
||||
{
|
||||
COMP->CSR |= COMP_CSR_WNDWEN;
|
||||
}
|
||||
|
||||
/* Initialize the COMP state*/
|
||||
hcomp->State = HAL_COMP_STATE_READY;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the COMP peripheral
|
||||
* @note Deinitialization can't be performed if the COMP configuration is locked.
|
||||
* To unlock the configuration, perform a system reset.
|
||||
* @param hcomp COMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint32_t regshift = COMP_CSR_COMP1_SHIFT;
|
||||
|
||||
/* Check the COMP handle allocation and lock status */
|
||||
if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
|
||||
/* Set COMP_CSR register to reset value for the corresponding COMP instance */
|
||||
if(hcomp->Instance == COMP2)
|
||||
{
|
||||
regshift = COMP_CSR_COMP2_SHIFT;
|
||||
}
|
||||
MODIFY_REG(COMP->CSR,
|
||||
COMP_CSR_RESET_PARAMETERS_MASK << regshift,
|
||||
COMP_CSR_RESET_VALUE << regshift);
|
||||
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
||||
if (hcomp->MspDeInitCallback == NULL)
|
||||
{
|
||||
hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */
|
||||
}
|
||||
|
||||
/* DeInit the low level hardware: SYSCFG, GPIO, CLOCK and NVIC */
|
||||
hcomp->MspDeInitCallback(hcomp);
|
||||
#else
|
||||
/* DeInit the low level hardware: SYSCFG, GPIO, CLOCK and NVIC */
|
||||
HAL_COMP_MspDeInit(hcomp);
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
|
||||
hcomp->State = HAL_COMP_STATE_RESET;
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hcomp);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the COMP MSP.
|
||||
* @param hcomp COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcomp);
|
||||
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_COMP_MspInit could be implenetd in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes COMP MSP.
|
||||
* @param hcomp COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcomp);
|
||||
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_COMP_MspDeInit could be implenetd in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief Register a User COMP Callback
|
||||
* To be used instead of the weak predefined callback
|
||||
* @param hcomp Pointer to a COMP_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified COMP.
|
||||
* @param CallbackID ID of the callback to be registered
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref HAL_COMP_TRIGGER_CB_ID Trigger callback ID
|
||||
* @arg @ref HAL_COMP_MSPINIT_CB_ID MspInit callback ID
|
||||
* @arg @ref HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID
|
||||
* @param pCallback pointer to the Callback function
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
if (pCallback == NULL)
|
||||
{
|
||||
/* Update the error code */
|
||||
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if (HAL_COMP_STATE_READY == hcomp->State)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_COMP_TRIGGER_CB_ID :
|
||||
hcomp->TriggerCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_COMP_MSPINIT_CB_ID :
|
||||
hcomp->MspInitCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_COMP_MSPDEINIT_CB_ID :
|
||||
hcomp->MspDeInitCallback = pCallback;
|
||||
break;
|
||||
|
||||
default :
|
||||
/* Update the error code */
|
||||
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
|
||||
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else if (HAL_COMP_STATE_RESET == hcomp->State)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_COMP_MSPINIT_CB_ID :
|
||||
hcomp->MspInitCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_COMP_MSPDEINIT_CB_ID :
|
||||
hcomp->MspDeInitCallback = pCallback;
|
||||
break;
|
||||
|
||||
default :
|
||||
/* Update the error code */
|
||||
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
|
||||
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update the error code */
|
||||
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
|
||||
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unregister a COMP Callback
|
||||
* COMP callback is redirected to the weak predefined callback
|
||||
* @param hcomp Pointer to a COMP_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified COMP.
|
||||
* @param CallbackID ID of the callback to be unregistered
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref HAL_COMP_TRIGGER_CB_ID Trigger callback ID
|
||||
* @arg @ref HAL_COMP_MSPINIT_CB_ID MspInit callback ID
|
||||
* @arg @ref HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
if (HAL_COMP_STATE_READY == hcomp->State)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_COMP_TRIGGER_CB_ID :
|
||||
hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */
|
||||
break;
|
||||
|
||||
case HAL_COMP_MSPINIT_CB_ID :
|
||||
hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */
|
||||
break;
|
||||
|
||||
case HAL_COMP_MSPDEINIT_CB_ID :
|
||||
hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */
|
||||
break;
|
||||
|
||||
default :
|
||||
/* Update the error code */
|
||||
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
|
||||
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else if (HAL_COMP_STATE_RESET == hcomp->State)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_COMP_MSPINIT_CB_ID :
|
||||
hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */
|
||||
break;
|
||||
|
||||
case HAL_COMP_MSPDEINIT_CB_ID :
|
||||
hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */
|
||||
break;
|
||||
|
||||
default :
|
||||
/* Update the error code */
|
||||
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
|
||||
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update the error code */
|
||||
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
|
||||
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Exported_Functions_Group2 I/O operation functions
|
||||
* @brief Data transfers functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to manage the COMP data
|
||||
transfers.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Start the comparator
|
||||
* @param hcomp COMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
uint32_t wait_loop_index = 0U;
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint32_t regshift = COMP_CSR_COMP1_SHIFT;
|
||||
|
||||
/* Check the COMP handle allocation and lock status */
|
||||
if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
|
||||
if(hcomp->State == HAL_COMP_STATE_READY)
|
||||
{
|
||||
/* Enable the selected comparator */
|
||||
if(hcomp->Instance == COMP2)
|
||||
{
|
||||
regshift = COMP_CSR_COMP2_SHIFT;
|
||||
}
|
||||
SET_BIT(COMP->CSR, COMP_CSR_COMPxEN << regshift);
|
||||
|
||||
/* Set HAL COMP handle state */
|
||||
hcomp->State = HAL_COMP_STATE_BUSY;
|
||||
|
||||
/* Delay for COMP startup time */
|
||||
wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / 1000000U));
|
||||
while(wait_loop_index != 0U)
|
||||
{
|
||||
wait_loop_index--;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stop the comparator
|
||||
* @param hcomp COMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint32_t regshift = COMP_CSR_COMP1_SHIFT;
|
||||
|
||||
/* Check the COMP handle allocation and lock status */
|
||||
if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
|
||||
if(hcomp->State == HAL_COMP_STATE_BUSY)
|
||||
{
|
||||
/* Disable the selected comparator */
|
||||
if(hcomp->Instance == COMP2)
|
||||
{
|
||||
regshift = COMP_CSR_COMP2_SHIFT;
|
||||
}
|
||||
CLEAR_BIT(COMP->CSR, COMP_CSR_COMPxEN << regshift);
|
||||
|
||||
hcomp->State = HAL_COMP_STATE_READY;
|
||||
}
|
||||
else
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the interrupt and starts the comparator
|
||||
* @param hcomp COMP handle
|
||||
* @retval HAL status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint32_t extiline = 0U;
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode));
|
||||
|
||||
status = HAL_COMP_Start(hcomp);
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Check the Exti Line output configuration */
|
||||
extiline = COMP_GET_EXTI_LINE(hcomp->Instance);
|
||||
/* Configure the rising edge */
|
||||
if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_RISING) != RESET)
|
||||
{
|
||||
SET_BIT(EXTI->RTSR, extiline);
|
||||
}
|
||||
else
|
||||
{
|
||||
CLEAR_BIT(EXTI->RTSR, extiline);
|
||||
}
|
||||
/* Configure the falling edge */
|
||||
if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_FALLING) != RESET)
|
||||
{
|
||||
SET_BIT(EXTI->FTSR, extiline);
|
||||
}
|
||||
else
|
||||
{
|
||||
CLEAR_BIT(EXTI->FTSR, extiline);
|
||||
}
|
||||
|
||||
/* Clear COMP EXTI pending bit */
|
||||
WRITE_REG(EXTI->PR, extiline);
|
||||
|
||||
/* Enable Exti interrupt mode */
|
||||
SET_BIT(EXTI->IMR, extiline);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the interrupt and Stop the comparator
|
||||
* @param hcomp COMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Disable the Exti Line interrupt mode */
|
||||
CLEAR_BIT(EXTI->IMR, COMP_GET_EXTI_LINE(hcomp->Instance));
|
||||
|
||||
status = HAL_COMP_Stop(hcomp);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Comparator IRQ Handler
|
||||
* @param hcomp COMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
uint32_t extiline = COMP_GET_EXTI_LINE(hcomp->Instance);
|
||||
|
||||
/* Check COMP Exti flag */
|
||||
if(READ_BIT(EXTI->PR, extiline) != RESET)
|
||||
{
|
||||
/* Clear COMP Exti pending bit */
|
||||
WRITE_REG(EXTI->PR, extiline);
|
||||
|
||||
/* COMP trigger callback */
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
||||
hcomp->TriggerCallback(hcomp);
|
||||
#else
|
||||
HAL_COMP_TriggerCallback(hcomp);
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @brief management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the COMP data
|
||||
transfers.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Lock the selected comparator configuration.
|
||||
* @param hcomp COMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint32_t regshift = COMP_CSR_COMP1_SHIFT;
|
||||
|
||||
/* Check the COMP handle allocation and lock status */
|
||||
if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
|
||||
/* Set lock flag */
|
||||
hcomp->State |= COMP_STATE_BIT_LOCK;
|
||||
|
||||
/* Set the lock bit corresponding to selected comparator */
|
||||
if(hcomp->Instance == COMP2)
|
||||
{
|
||||
regshift = COMP_CSR_COMP2_SHIFT;
|
||||
}
|
||||
SET_BIT(COMP->CSR, COMP_CSR_COMPxLOCK << regshift);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the output level (high or low) of the selected comparator.
|
||||
* The output level depends on the selected polarity.
|
||||
* If the polarity is not inverted:
|
||||
* - Comparator output is low when the non-inverting input is at a lower
|
||||
* voltage than the inverting input
|
||||
* - Comparator output is high when the non-inverting input is at a higher
|
||||
* voltage than the inverting input
|
||||
* If the polarity is inverted:
|
||||
* - Comparator output is high when the non-inverting input is at a lower
|
||||
* voltage than the inverting input
|
||||
* - Comparator output is low when the non-inverting input is at a higher
|
||||
* voltage than the inverting input
|
||||
* @param hcomp COMP handle
|
||||
* @retval Returns the selected comparator output level: COMP_OUTPUTLEVEL_LOW or COMP_OUTPUTLEVEL_HIGH.
|
||||
*
|
||||
*/
|
||||
uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
uint32_t level=0;
|
||||
uint32_t regshift = COMP_CSR_COMP1_SHIFT;
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
|
||||
if(hcomp->Instance == COMP2)
|
||||
{
|
||||
regshift = COMP_CSR_COMP2_SHIFT;
|
||||
}
|
||||
level = READ_BIT(COMP->CSR, COMP_CSR_COMPxOUT << regshift);
|
||||
|
||||
if(level != 0U)
|
||||
{
|
||||
return(COMP_OUTPUTLEVEL_HIGH);
|
||||
}
|
||||
return(COMP_OUTPUTLEVEL_LOW);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Comparator trigger callback.
|
||||
* @param hcomp COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcomp);
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_COMP_TriggerCallback should be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral State functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection permit to get in run-time the status of the peripheral
|
||||
and the data flow.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Return the COMP state
|
||||
* @param hcomp COMP handle
|
||||
* @retval HAL state
|
||||
*/
|
||||
uint32_t HAL_COMP_GetState(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
/* Check the COMP handle allocation */
|
||||
if(hcomp == NULL)
|
||||
{
|
||||
return HAL_COMP_STATE_RESET;
|
||||
}
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
|
||||
return hcomp->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the COMP error code.
|
||||
* @param hcomp COMP handle
|
||||
* @retval COMP error code
|
||||
*/
|
||||
uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
|
||||
return hcomp->ErrorCode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* COMP1 || COMP2 */
|
||||
|
||||
#endif /* HAL_COMP_MODULE_ENABLED */
|
||||
|
||||
|
||||
342
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c
Normal file
342
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c
Normal file
@@ -0,0 +1,342 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_cortex.c
|
||||
* @author MCD Application Team
|
||||
* @brief CORTEX HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the CORTEX:
|
||||
* + Initialization and de-initialization functions
|
||||
* + Peripheral Control functions
|
||||
*
|
||||
* @verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
|
||||
[..]
|
||||
*** How to configure Interrupts using CORTEX HAL driver ***
|
||||
===========================================================
|
||||
[..]
|
||||
This section provides functions allowing to configure the NVIC interrupts (IRQ).
|
||||
The Cortex-M0 exceptions are managed by CMSIS functions.
|
||||
(#) Enable and Configure the priority of the selected IRQ Channels.
|
||||
The priority can be 0..3.
|
||||
|
||||
-@- Lower priority values gives higher priority.
|
||||
-@- Priority Order:
|
||||
(#@) Lowest priority.
|
||||
(#@) Lowest hardware priority (IRQn position).
|
||||
|
||||
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
|
||||
|
||||
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
|
||||
|
||||
-@- Negative value of IRQn_Type are not allowed.
|
||||
|
||||
|
||||
[..]
|
||||
*** How to configure Systick using CORTEX HAL driver ***
|
||||
========================================================
|
||||
[..]
|
||||
Setup SysTick Timer for time base.
|
||||
|
||||
(+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
|
||||
is a CMSIS function that:
|
||||
(++) Configures the SysTick Reload register with value passed as function parameter.
|
||||
(++) Configures the SysTick IRQ priority to the lowest value (0x03).
|
||||
(++) Resets the SysTick Counter register.
|
||||
(++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
|
||||
(++) Enables the SysTick Interrupt.
|
||||
(++) Starts the SysTick Counter.
|
||||
|
||||
(+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
|
||||
HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
|
||||
HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() macro is defined
|
||||
inside the stm32f0xx_hal_cortex.h file.
|
||||
|
||||
(+) You can change the SysTick IRQ priority by calling the
|
||||
HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
|
||||
call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
|
||||
|
||||
(+) To adjust the SysTick time base, use the following formula:
|
||||
|
||||
Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
|
||||
(++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
|
||||
(++) Reload Value should not exceed 0xFFFFFF
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX CORTEX
|
||||
* @brief CORTEX CORTEX HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This section provides the CORTEX HAL driver functions allowing to configure Interrupts
|
||||
Systick functionalities
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Sets the priority of an interrupt.
|
||||
* @param IRQn External interrupt number .
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32f0xx.h file)
|
||||
* @param PreemptPriority The preemption priority for the IRQn channel.
|
||||
* This parameter can be a value between 0 and 3.
|
||||
* A lower priority value indicates a higher priority
|
||||
* @param SubPriority the subpriority level for the IRQ channel.
|
||||
* with stm32f0xx devices, this parameter is a dummy value and it is ignored, because
|
||||
* no subpriority supported in Cortex M0 based products.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
||||
NVIC_SetPriority(IRQn,PreemptPriority);
|
||||
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(SubPriority);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables a device specific interrupt in the NVIC interrupt controller.
|
||||
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
|
||||
* function should be called before.
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Enable interrupt */
|
||||
NVIC_EnableIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables a device specific interrupt in the NVIC interrupt controller.
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Disable interrupt */
|
||||
NVIC_DisableIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initiates a system reset request to reset the MCU.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SystemReset(void)
|
||||
{
|
||||
/* System Reset */
|
||||
NVIC_SystemReset();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
* Counter is in free running mode to generate periodic interrupts.
|
||||
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
|
||||
* @retval status: - 0 Function succeeded.
|
||||
* - 1 Function failed.
|
||||
*/
|
||||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
||||
{
|
||||
return SysTick_Config(TicksNumb);
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief Cortex control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the CORTEX
|
||||
(NVIC, SYSTICK) functionalities.
|
||||
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Gets the priority of an interrupt.
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn)
|
||||
{
|
||||
/* Get priority for Cortex-M system or device specific interrupts */
|
||||
return NVIC_GetPriority(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets Pending bit of an external interrupt.
|
||||
* @param IRQn External interrupt number
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Set interrupt pending */
|
||||
NVIC_SetPendingIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets Pending Interrupt (reads the pending register in the NVIC
|
||||
* and returns the pending bit for the specified interrupt).
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
|
||||
* @retval status: - 0 Interrupt status is not pending.
|
||||
* - 1 Interrupt status is pending.
|
||||
*/
|
||||
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Return 1 if pending else 0 */
|
||||
return NVIC_GetPendingIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the pending bit of an external interrupt.
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Clear pending interrupt */
|
||||
NVIC_ClearPendingIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the SysTick clock source.
|
||||
* @param CLKSource specifies the SysTick clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
|
||||
* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
|
||||
if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
|
||||
{
|
||||
SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
|
||||
}
|
||||
else
|
||||
{
|
||||
SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles SYSTICK interrupt request.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SYSTICK_IRQHandler(void)
|
||||
{
|
||||
HAL_SYSTICK_Callback();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SYSTICK callback.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_SYSTICK_Callback(void)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_SYSTICK_Callback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
518
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_crc.c
Normal file
518
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_crc.c
Normal file
@@ -0,0 +1,518 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_crc.c
|
||||
* @author MCD Application Team
|
||||
* @brief CRC HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Cyclic Redundancy Check (CRC) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + Peripheral Control functions
|
||||
* + Peripheral State functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### How to use this driver #####
|
||||
===============================================================================
|
||||
[..]
|
||||
(+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
|
||||
(+) Initialize CRC calculator
|
||||
(++) specify generating polynomial (peripheral default or non-default one)
|
||||
(++) specify initialization value (peripheral default or non-default one)
|
||||
(++) specify input data format
|
||||
(++) specify input or output data inversion mode if any
|
||||
(+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
|
||||
input data buffer starting with the previously computed CRC as
|
||||
initialization value
|
||||
(+) Use HAL_CRC_Calculate() function to compute the CRC value of the
|
||||
input data buffer starting with the defined initialization value
|
||||
(default or non-default) to initiate CRC calculation
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC CRC
|
||||
* @brief CRC HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_CRC_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup CRC_Private_Functions CRC Private Functions
|
||||
* @{
|
||||
*/
|
||||
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
|
||||
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRC_Exported_Functions CRC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Initialize the CRC according to the specified parameters
|
||||
in the CRC_InitTypeDef and create the associated handle
|
||||
(+) DeInitialize the CRC peripheral
|
||||
(+) Initialize the CRC MSP (MCU Specific Package)
|
||||
(+) DeInitialize the CRC MSP
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initialize the CRC according to the specified
|
||||
* parameters in the CRC_InitTypeDef and create the associated handle.
|
||||
* @param hcrc CRC handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
/* Check the CRC handle allocation */
|
||||
if (hcrc == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
|
||||
|
||||
if (hcrc->State == HAL_CRC_STATE_RESET)
|
||||
{
|
||||
/* Allocate lock resource and initialize it */
|
||||
hcrc->Lock = HAL_UNLOCKED;
|
||||
/* Init the low level hardware */
|
||||
HAL_CRC_MspInit(hcrc);
|
||||
}
|
||||
|
||||
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||
|
||||
#if defined(CRC_POL_POL)
|
||||
/* check whether or not non-default generating polynomial has been
|
||||
* picked up by user */
|
||||
assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
|
||||
if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
|
||||
{
|
||||
/* initialize peripheral with default generating polynomial */
|
||||
WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
|
||||
MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* initialize CRC peripheral with generating polynomial defined by user */
|
||||
if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
#endif /* CRC_POL_POL */
|
||||
|
||||
/* check whether or not non-default CRC initial value has been
|
||||
* picked up by user */
|
||||
assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
|
||||
if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
|
||||
{
|
||||
WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
|
||||
}
|
||||
else
|
||||
{
|
||||
WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
|
||||
}
|
||||
|
||||
|
||||
/* set input data inversion mode */
|
||||
assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
|
||||
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
|
||||
|
||||
/* set output data inversion mode */
|
||||
assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
|
||||
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
|
||||
|
||||
/* makes sure the input data format (bytes, halfwords or words stream)
|
||||
* is properly specified by user */
|
||||
assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_READY;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitialize the CRC peripheral.
|
||||
* @param hcrc CRC handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
/* Check the CRC handle allocation */
|
||||
if (hcrc == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
|
||||
|
||||
/* Check the CRC peripheral state */
|
||||
if (hcrc->State == HAL_CRC_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||
|
||||
/* Reset CRC calculation unit */
|
||||
__HAL_CRC_DR_RESET(hcrc);
|
||||
|
||||
/* Reset IDR register content */
|
||||
__HAL_CRC_SET_IDR(hcrc, 0);
|
||||
|
||||
/* DeInit the low level hardware */
|
||||
HAL_CRC_MspDeInit(hcrc);
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_RESET;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hcrc);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the CRC MSP.
|
||||
* @param hcrc CRC handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcrc);
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_CRC_MspInit can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitialize the CRC MSP.
|
||||
* @param hcrc CRC handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcrc);
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_CRC_MspDeInit can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief management functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
|
||||
using combination of the previous CRC value and the new one.
|
||||
|
||||
[..] or
|
||||
|
||||
(+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
|
||||
independently of the previous CRC value.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
|
||||
* starting with the previously computed CRC as initialization value.
|
||||
* @param hcrc CRC handle
|
||||
* @param pBuffer pointer to the input data buffer, exact input data format is
|
||||
* provided by hcrc->InputDataFormat.
|
||||
* @param BufferLength input data buffer length (number of bytes if pBuffer
|
||||
* type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
|
||||
* number of words if pBuffer type is * uint32_t).
|
||||
* @note By default, the API expects a uint32_t pointer as input buffer parameter.
|
||||
* Input buffer pointers with other types simply need to be cast in uint32_t
|
||||
* and the API will internally adjust its input data processing based on the
|
||||
* handle field hcrc->InputDataFormat.
|
||||
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
|
||||
*/
|
||||
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
|
||||
{
|
||||
uint32_t index; /* CRC input data buffer index */
|
||||
uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||
|
||||
switch (hcrc->InputDataFormat)
|
||||
{
|
||||
case CRC_INPUTDATA_FORMAT_WORDS:
|
||||
/* Enter Data to the CRC calculator */
|
||||
for (index = 0U; index < BufferLength; index++)
|
||||
{
|
||||
hcrc->Instance->DR = pBuffer[index];
|
||||
}
|
||||
temp = hcrc->Instance->DR;
|
||||
break;
|
||||
|
||||
case CRC_INPUTDATA_FORMAT_BYTES:
|
||||
temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
|
||||
break;
|
||||
|
||||
case CRC_INPUTDATA_FORMAT_HALFWORDS:
|
||||
temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_READY;
|
||||
|
||||
/* Return the CRC computed value */
|
||||
return temp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
|
||||
* starting with hcrc->Instance->INIT as initialization value.
|
||||
* @param hcrc CRC handle
|
||||
* @param pBuffer pointer to the input data buffer, exact input data format is
|
||||
* provided by hcrc->InputDataFormat.
|
||||
* @param BufferLength input data buffer length (number of bytes if pBuffer
|
||||
* type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
|
||||
* number of words if pBuffer type is * uint32_t).
|
||||
* @note By default, the API expects a uint32_t pointer as input buffer parameter.
|
||||
* Input buffer pointers with other types simply need to be cast in uint32_t
|
||||
* and the API will internally adjust its input data processing based on the
|
||||
* handle field hcrc->InputDataFormat.
|
||||
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
|
||||
*/
|
||||
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
|
||||
{
|
||||
uint32_t index; /* CRC input data buffer index */
|
||||
uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||
|
||||
/* Reset CRC Calculation Unit (hcrc->Instance->INIT is
|
||||
* written in hcrc->Instance->DR) */
|
||||
__HAL_CRC_DR_RESET(hcrc);
|
||||
|
||||
switch (hcrc->InputDataFormat)
|
||||
{
|
||||
case CRC_INPUTDATA_FORMAT_WORDS:
|
||||
/* Enter 32-bit input data to the CRC calculator */
|
||||
for (index = 0U; index < BufferLength; index++)
|
||||
{
|
||||
hcrc->Instance->DR = pBuffer[index];
|
||||
}
|
||||
temp = hcrc->Instance->DR;
|
||||
break;
|
||||
|
||||
case CRC_INPUTDATA_FORMAT_BYTES:
|
||||
/* Specific 8-bit input data handling */
|
||||
temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
|
||||
break;
|
||||
|
||||
case CRC_INPUTDATA_FORMAT_HALFWORDS:
|
||||
/* Specific 16-bit input data handling */
|
||||
temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_READY;
|
||||
|
||||
/* Return the CRC computed value */
|
||||
return temp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
|
||||
* @brief Peripheral State functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral State functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection permits to get in run-time the status of the peripheral.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Return the CRC handle state.
|
||||
* @param hcrc CRC handle
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
/* Return CRC handle state */
|
||||
return hcrc->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enter 8-bit input data to the CRC calculator.
|
||||
* Specific data handling to optimize processing time.
|
||||
* @param hcrc CRC handle
|
||||
* @param pBuffer pointer to the input data buffer
|
||||
* @param BufferLength input data buffer length
|
||||
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
|
||||
*/
|
||||
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
|
||||
{
|
||||
uint32_t i; /* input data buffer index */
|
||||
uint16_t data;
|
||||
__IO uint16_t *pReg;
|
||||
|
||||
/* Processing time optimization: 4 bytes are entered in a row with a single word write,
|
||||
* last bytes must be carefully fed to the CRC calculator to ensure a correct type
|
||||
* handling by the peripheral */
|
||||
for (i = 0U; i < (BufferLength / 4U); i++)
|
||||
{
|
||||
hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \
|
||||
((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \
|
||||
((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \
|
||||
(uint32_t)pBuffer[(4U * i) + 3U];
|
||||
}
|
||||
/* last bytes specific handling */
|
||||
if ((BufferLength % 4U) != 0U)
|
||||
{
|
||||
if ((BufferLength % 4U) == 1U)
|
||||
{
|
||||
*(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */
|
||||
}
|
||||
if ((BufferLength % 4U) == 2U)
|
||||
{
|
||||
data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
|
||||
pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
|
||||
*pReg = data;
|
||||
}
|
||||
if ((BufferLength % 4U) == 3U)
|
||||
{
|
||||
data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
|
||||
pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
|
||||
*pReg = data;
|
||||
|
||||
*(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */
|
||||
}
|
||||
}
|
||||
|
||||
/* Return the CRC computed value */
|
||||
return hcrc->Instance->DR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enter 16-bit input data to the CRC calculator.
|
||||
* Specific data handling to optimize processing time.
|
||||
* @param hcrc CRC handle
|
||||
* @param pBuffer pointer to the input data buffer
|
||||
* @param BufferLength input data buffer length
|
||||
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
|
||||
*/
|
||||
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
|
||||
{
|
||||
uint32_t i; /* input data buffer index */
|
||||
__IO uint16_t *pReg;
|
||||
|
||||
/* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
|
||||
* in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
|
||||
* a correct type handling by the peripheral */
|
||||
for (i = 0U; i < (BufferLength / 2U); i++)
|
||||
{
|
||||
hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U];
|
||||
}
|
||||
if ((BufferLength % 2U) != 0U)
|
||||
{
|
||||
pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
|
||||
*pReg = pBuffer[2U * i];
|
||||
}
|
||||
|
||||
/* Return the CRC computed value */
|
||||
return hcrc->Instance->DR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
232
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_crc_ex.c
Normal file
232
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_crc_ex.c
Normal file
@@ -0,0 +1,232 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_crc_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief Extended CRC HAL module driver.
|
||||
* This file provides firmware functions to manage the extended
|
||||
* functionalities of the CRC peripheral.
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
================================================================================
|
||||
##### How to use this driver #####
|
||||
================================================================================
|
||||
[..]
|
||||
(+) Set user-defined generating polynomial through HAL_CRCEx_Polynomial_Set()
|
||||
(+) Configure Input or Output data inversion
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRCEx CRCEx
|
||||
* @brief CRC Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_CRC_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions
|
||||
* @brief Extended Initialization and Configuration functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extended configuration functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure the generating polynomial
|
||||
(+) Configure the input data inversion
|
||||
(+) Configure the output data inversion
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
#if defined(CRC_POL_POL)
|
||||
/**
|
||||
* @brief Initialize the CRC polynomial if different from default one.
|
||||
* @param hcrc CRC handle
|
||||
* @param Pol CRC generating polynomial (7, 8, 16 or 32-bit long).
|
||||
* This parameter is written in normal representation, e.g.
|
||||
* @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
|
||||
* @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
|
||||
* @param PolyLength CRC polynomial length.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CRC_POLYLENGTH_7B 7-bit long CRC (generating polynomial of degree 7)
|
||||
* @arg @ref CRC_POLYLENGTH_8B 8-bit long CRC (generating polynomial of degree 8)
|
||||
* @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16)
|
||||
* @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32)
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CRC_POL_LENGTH(PolyLength));
|
||||
|
||||
/* Ensure that the generating polynomial is odd */
|
||||
if ((Pol & (uint32_t)(0x1U)) == 0U)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* check polynomial definition vs polynomial size:
|
||||
* polynomial length must be aligned with polynomial
|
||||
* definition. HAL_ERROR is reported if Pol degree is
|
||||
* larger than that indicated by PolyLength.
|
||||
* Look for MSB position: msb will contain the degree of
|
||||
* the second to the largest polynomial member. E.g., for
|
||||
* X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
|
||||
while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
|
||||
{
|
||||
}
|
||||
|
||||
switch (PolyLength)
|
||||
{
|
||||
|
||||
case CRC_POLYLENGTH_7B:
|
||||
if (msb >= HAL_CRC_LENGTH_7B)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
break;
|
||||
case CRC_POLYLENGTH_8B:
|
||||
if (msb >= HAL_CRC_LENGTH_8B)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
break;
|
||||
case CRC_POLYLENGTH_16B:
|
||||
if (msb >= HAL_CRC_LENGTH_16B)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
break;
|
||||
|
||||
case CRC_POLYLENGTH_32B:
|
||||
/* no polynomial definition vs. polynomial length issue possible */
|
||||
break;
|
||||
default:
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (status == HAL_OK)
|
||||
{
|
||||
/* set generating polynomial */
|
||||
WRITE_REG(hcrc->Instance->POL, Pol);
|
||||
|
||||
/* set generating polynomial size */
|
||||
MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
|
||||
}
|
||||
/* Return function status */
|
||||
return status;
|
||||
}
|
||||
#endif /* CRC_POL_POL */
|
||||
|
||||
/**
|
||||
* @brief Set the Reverse Input data mode.
|
||||
* @param hcrc CRC handle
|
||||
* @param InputReverseMode Input Data inversion mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CRC_INPUTDATA_INVERSION_NONE no change in bit order (default value)
|
||||
* @arg @ref CRC_INPUTDATA_INVERSION_BYTE Byte-wise bit reversal
|
||||
* @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD HalfWord-wise bit reversal
|
||||
* @arg @ref CRC_INPUTDATA_INVERSION_WORD Word-wise bit reversal
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode));
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||
|
||||
/* set input data inversion mode */
|
||||
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode);
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_READY;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Reverse Output data mode.
|
||||
* @param hcrc CRC handle
|
||||
* @param OutputReverseMode Output Data inversion mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion (default value)
|
||||
* @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD)
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode));
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||
|
||||
/* set output data inversion mode */
|
||||
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode);
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_READY;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
1088
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dac.c
Normal file
1088
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dac.c
Normal file
File diff suppressed because it is too large
Load Diff
1182
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dac_ex.c
Normal file
1182
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dac_ex.c
Normal file
File diff suppressed because it is too large
Load Diff
899
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c
Normal file
899
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c
Normal file
@@ -0,0 +1,899 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_dma.c
|
||||
* @author MCD Application Team
|
||||
* @brief DMA HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Direct Memory Access (DMA) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + IO operation functions
|
||||
* + Peripheral State and errors functions
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) Enable and configure the peripheral to be connected to the DMA Channel
|
||||
(except for internal SRAM / FLASH memories: no initialization is
|
||||
necessary). Please refer to Reference manual for connection between peripherals
|
||||
and DMA requests .
|
||||
|
||||
(#) For a given Channel, program the required configuration through the following parameters:
|
||||
Transfer Direction, Source and Destination data formats,
|
||||
Circular or Normal mode, Channel Priority level, Source and Destination Increment mode,
|
||||
using HAL_DMA_Init() function.
|
||||
|
||||
(#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
|
||||
detection.
|
||||
|
||||
(#) Use HAL_DMA_Abort() function to abort the current transfer
|
||||
|
||||
-@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
|
||||
*** Polling mode IO operation ***
|
||||
=================================
|
||||
[..]
|
||||
(+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
|
||||
address and destination address and the Length of data to be transferred
|
||||
(+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
|
||||
case a fixed Timeout can be configured by User depending from his application.
|
||||
|
||||
*** Interrupt mode IO operation ***
|
||||
===================================
|
||||
[..]
|
||||
(+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
|
||||
(+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
|
||||
(+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
|
||||
Source address and destination address and the Length of data to be transferred.
|
||||
In this case the DMA interrupt is configured
|
||||
(+) Use HAL_DMA_Channel_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
|
||||
(+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
|
||||
add his own function by customization of function pointer XferCpltCallback and
|
||||
XferErrorCallback (i.e a member of DMA handle structure).
|
||||
|
||||
*** DMA HAL driver macros list ***
|
||||
=============================================
|
||||
[..]
|
||||
Below the list of most used macros in DMA HAL driver.
|
||||
|
||||
[..]
|
||||
(@) You can refer to the DMA HAL driver header file for more useful macros
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA DMA
|
||||
* @brief DMA HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup DMA_Private_Functions DMA Private Functions
|
||||
* @{
|
||||
*/
|
||||
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||||
static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions DMA Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and de-initialization functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This section provides functions allowing to initialize the DMA Channel source
|
||||
and destination addresses, incrementation and data sizes, transfer direction,
|
||||
circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
|
||||
[..]
|
||||
The HAL_DMA_Init() function follows the DMA configuration procedures as described in
|
||||
reference manual.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initialize the DMA according to the specified
|
||||
* parameters in the DMA_InitTypeDef and initialize the associated handle.
|
||||
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
/* Check the DMA handle allocation */
|
||||
if (NULL == hdma)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
|
||||
assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
|
||||
assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
|
||||
assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
|
||||
assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
|
||||
assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
|
||||
assert_param(IS_DMA_MODE(hdma->Init.Mode));
|
||||
assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
|
||||
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
|
||||
/* Get the CR register value */
|
||||
tmp = hdma->Instance->CCR;
|
||||
|
||||
/* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
|
||||
tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
|
||||
DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
|
||||
DMA_CCR_DIR));
|
||||
|
||||
/* Prepare the DMA Channel configuration */
|
||||
tmp |= hdma->Init.Direction |
|
||||
hdma->Init.PeriphInc | hdma->Init.MemInc |
|
||||
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
|
||||
hdma->Init.Mode | hdma->Init.Priority;
|
||||
|
||||
/* Write to DMA Channel CR register */
|
||||
hdma->Instance->CCR = tmp;
|
||||
|
||||
/* Initialize DmaBaseAddress and ChannelIndex parameters used
|
||||
by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
|
||||
DMA_CalcBaseAndBitshift(hdma);
|
||||
|
||||
/* Initialise the error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
||||
|
||||
/* Initialize the DMA state*/
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Allocate lock resource and initialize it */
|
||||
hdma->Lock = HAL_UNLOCKED;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitialize the DMA peripheral
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
/* Check the DMA handle allocation */
|
||||
if (NULL == hdma)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
|
||||
|
||||
/* Disable the selected DMA Channelx */
|
||||
hdma->Instance->CCR &= ~DMA_CCR_EN;
|
||||
|
||||
/* Reset DMA Channel control register */
|
||||
hdma->Instance->CCR = 0U;
|
||||
|
||||
/* Reset DMA Channel Number of Data to Transfer register */
|
||||
hdma->Instance->CNDTR = 0U;
|
||||
|
||||
/* Reset DMA Channel peripheral address register */
|
||||
hdma->Instance->CPAR = 0U;
|
||||
|
||||
/* Reset DMA Channel memory address register */
|
||||
hdma->Instance->CMAR = 0U;
|
||||
|
||||
/* Get DMA Base Address */
|
||||
DMA_CalcBaseAndBitshift(hdma);
|
||||
|
||||
/* Clear all flags */
|
||||
hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
|
||||
|
||||
/* Clean callbacks */
|
||||
hdma->XferCpltCallback = NULL;
|
||||
hdma->XferHalfCpltCallback = NULL;
|
||||
hdma->XferErrorCallback = NULL;
|
||||
hdma->XferAbortCallback = NULL;
|
||||
|
||||
/* Reset the error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
||||
|
||||
/* Reset the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_RESET;
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @brief I/O operation functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure the source, destination address and data length and Start DMA transfer
|
||||
(+) Configure the source, destination address and data length and
|
||||
Start DMA transfer with interrupt
|
||||
(+) Abort DMA transfer
|
||||
(+) Poll for transfer complete
|
||||
(+) Handle DMA interrupt request
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Start the DMA Transfer.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @param SrcAddress The source memory Buffer address
|
||||
* @param DstAddress The destination memory Buffer address
|
||||
* @param DataLength The length of data to be transferred from source to destination
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
if (HAL_DMA_STATE_READY == hdma->State)
|
||||
{
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
||||
|
||||
/* Disable the peripheral */
|
||||
hdma->Instance->CCR &= ~DMA_CCR_EN;
|
||||
|
||||
/* Configure the source, destination address and the data length */
|
||||
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
|
||||
|
||||
/* Enable the Peripheral */
|
||||
hdma->Instance->CCR |= DMA_CCR_EN;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
/* Remain BUSY */
|
||||
status = HAL_BUSY;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Start the DMA Transfer with interrupt enabled.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @param SrcAddress The source memory Buffer address
|
||||
* @param DstAddress The destination memory Buffer address
|
||||
* @param DataLength The length of data to be transferred from source to destination
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
if (HAL_DMA_STATE_READY == hdma->State)
|
||||
{
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
||||
|
||||
/* Disable the peripheral */
|
||||
hdma->Instance->CCR &= ~DMA_CCR_EN;
|
||||
|
||||
/* Configure the source, destination address and the data length */
|
||||
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
|
||||
|
||||
/* Enable the transfer complete, & transfer error interrupts */
|
||||
/* Half transfer interrupt is optional: enable it only if associated callback is available */
|
||||
if (NULL != hdma->XferHalfCpltCallback)
|
||||
{
|
||||
hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
|
||||
}
|
||||
else
|
||||
{
|
||||
hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE);
|
||||
hdma->Instance->CCR &= ~DMA_IT_HT;
|
||||
}
|
||||
|
||||
/* Enable the Peripheral */
|
||||
hdma->Instance->CCR |= DMA_CCR_EN;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
/* Remain BUSY */
|
||||
status = HAL_BUSY;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Abort the DMA Transfer.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
if (hdma->State != HAL_DMA_STATE_BUSY)
|
||||
{
|
||||
/* no transfer ongoing */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable DMA IT */
|
||||
hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
|
||||
|
||||
/* Disable the channel */
|
||||
hdma->Instance->CCR &= ~DMA_CCR_EN;
|
||||
|
||||
/* Clear all flags */
|
||||
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex);
|
||||
}
|
||||
/* Change the DMA state*/
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Abort the DMA Transfer in Interrupt mode.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
if (HAL_DMA_STATE_BUSY != hdma->State)
|
||||
{
|
||||
/* no transfer ongoing */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
||||
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
||||
/* Disable DMA IT */
|
||||
hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
|
||||
|
||||
/* Disable the channel */
|
||||
hdma->Instance->CCR &= ~DMA_CCR_EN;
|
||||
|
||||
/* Clear all flags */
|
||||
hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
/* Call User Abort callback */
|
||||
if (hdma->XferAbortCallback != NULL)
|
||||
{
|
||||
hdma->XferAbortCallback(hdma);
|
||||
}
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Polling for transfer complete.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @param CompleteLevel Specifies the DMA level complete.
|
||||
* @param Timeout Timeout duration.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
|
||||
{
|
||||
uint32_t temp;
|
||||
uint32_t tickstart = 0U;
|
||||
|
||||
if (HAL_DMA_STATE_BUSY != hdma->State)
|
||||
{
|
||||
/* no transfer ongoing */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
||||
__HAL_UNLOCK(hdma);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Polling mode not supported in circular mode */
|
||||
if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC))
|
||||
{
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Get the level transfer complete flag */
|
||||
if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
|
||||
{
|
||||
/* Transfer Complete flag */
|
||||
temp = DMA_FLAG_TC1 << hdma->ChannelIndex;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Half Transfer Complete flag */
|
||||
temp = DMA_FLAG_HT1 << hdma->ChannelIndex;
|
||||
}
|
||||
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
while (RESET == (hdma->DmaBaseAddress->ISR & temp))
|
||||
{
|
||||
if (RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex)))
|
||||
{
|
||||
/* When a DMA transfer error occurs */
|
||||
/* A hardware clear of its EN bits is performed */
|
||||
/* Clear all flags */
|
||||
hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
|
||||
|
||||
/* Update error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_TE;
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Check for the Timeout */
|
||||
if (Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
|
||||
{
|
||||
/* Update error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
|
||||
{
|
||||
/* Clear the transfer complete flag */
|
||||
hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
|
||||
|
||||
/* The selected Channelx EN bit is cleared (DMA is disabled and
|
||||
all transfers are complete) */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear the half transfer complete flag */
|
||||
hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
|
||||
}
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handle DMA interrupt request.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
uint32_t flag_it = hdma->DmaBaseAddress->ISR;
|
||||
uint32_t source_it = hdma->Instance->CCR;
|
||||
|
||||
/* Half Transfer Complete Interrupt management ******************************/
|
||||
if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT)))
|
||||
{
|
||||
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
|
||||
if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
|
||||
{
|
||||
/* Disable the half transfer interrupt */
|
||||
hdma->Instance->CCR &= ~DMA_IT_HT;
|
||||
}
|
||||
|
||||
/* Clear the half transfer complete flag */
|
||||
hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
|
||||
|
||||
/* DMA peripheral state is not updated in Half Transfer */
|
||||
/* State is updated only in Transfer Complete case */
|
||||
|
||||
if (hdma->XferHalfCpltCallback != NULL)
|
||||
{
|
||||
/* Half transfer callback */
|
||||
hdma->XferHalfCpltCallback(hdma);
|
||||
}
|
||||
}
|
||||
|
||||
/* Transfer Complete Interrupt management ***********************************/
|
||||
else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC)))
|
||||
{
|
||||
if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
|
||||
{
|
||||
/* Disable the transfer complete & transfer error interrupts */
|
||||
/* if the DMA mode is not CIRCULAR */
|
||||
hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE);
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
}
|
||||
|
||||
/* Clear the transfer complete flag */
|
||||
hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
if (hdma->XferCpltCallback != NULL)
|
||||
{
|
||||
/* Transfer complete callback */
|
||||
hdma->XferCpltCallback(hdma);
|
||||
}
|
||||
}
|
||||
|
||||
/* Transfer Error Interrupt management ***************************************/
|
||||
else if ((RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
|
||||
{
|
||||
/* When a DMA transfer error occurs */
|
||||
/* A hardware clear of its EN bits is performed */
|
||||
/* Then, disable all DMA interrupts */
|
||||
hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
|
||||
|
||||
/* Clear all flags */
|
||||
hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
|
||||
|
||||
/* Update error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_TE;
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
if (hdma->XferErrorCallback != NULL)
|
||||
{
|
||||
/* Transfer error callback */
|
||||
hdma->XferErrorCallback(hdma);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Register callbacks
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @param CallbackID User Callback identifier
|
||||
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
|
||||
* @param pCallback pointer to private callback function which has pointer to
|
||||
* a DMA_HandleTypeDef structure as parameter.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
if (HAL_DMA_STATE_READY == hdma->State)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_DMA_XFER_CPLT_CB_ID:
|
||||
hdma->XferCpltCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_HALFCPLT_CB_ID:
|
||||
hdma->XferHalfCpltCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_ERROR_CB_ID:
|
||||
hdma->XferErrorCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_ABORT_CB_ID:
|
||||
hdma->XferAbortCallback = pCallback;
|
||||
break;
|
||||
|
||||
default:
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief UnRegister callbacks
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @param CallbackID User Callback identifier
|
||||
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
if (HAL_DMA_STATE_READY == hdma->State)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_DMA_XFER_CPLT_CB_ID:
|
||||
hdma->XferCpltCallback = NULL;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_HALFCPLT_CB_ID:
|
||||
hdma->XferHalfCpltCallback = NULL;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_ERROR_CB_ID:
|
||||
hdma->XferErrorCallback = NULL;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_ABORT_CB_ID:
|
||||
hdma->XferAbortCallback = NULL;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_ALL_CB_ID:
|
||||
hdma->XferCpltCallback = NULL;
|
||||
hdma->XferHalfCpltCallback = NULL;
|
||||
hdma->XferErrorCallback = NULL;
|
||||
hdma->XferAbortCallback = NULL;
|
||||
break;
|
||||
|
||||
default:
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### State and Errors functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides functions allowing to
|
||||
(+) Check the DMA state
|
||||
(+) Get error code
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Returns the DMA state.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
return hdma->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the DMA error code
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval DMA Error Code
|
||||
*/
|
||||
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
return hdma->ErrorCode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set the DMA Transfer parameters.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @param SrcAddress The source memory Buffer address
|
||||
* @param DstAddress The destination memory Buffer address
|
||||
* @param DataLength The length of data to be transferred from source to destination
|
||||
* @retval HAL status
|
||||
*/
|
||||
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
||||
{
|
||||
/* Clear all flags */
|
||||
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex);
|
||||
|
||||
/* Configure DMA Channel data length */
|
||||
hdma->Instance->CNDTR = DataLength;
|
||||
|
||||
/* Memory to Peripheral */
|
||||
if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
|
||||
{
|
||||
/* Configure DMA Channel destination address */
|
||||
hdma->Instance->CPAR = DstAddress;
|
||||
|
||||
/* Configure DMA Channel source address */
|
||||
hdma->Instance->CMAR = SrcAddress;
|
||||
}
|
||||
/* Peripheral to Memory */
|
||||
else
|
||||
{
|
||||
/* Configure DMA Channel source address */
|
||||
hdma->Instance->CPAR = SrcAddress;
|
||||
|
||||
/* Configure DMA Channel destination address */
|
||||
hdma->Instance->CMAR = DstAddress;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set the DMA base address and channel index depending on DMA instance
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @retval None
|
||||
*/
|
||||
static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
#if defined (DMA2)
|
||||
/* calculation of the channel index */
|
||||
if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
|
||||
{
|
||||
/* DMA1 */
|
||||
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
|
||||
hdma->DmaBaseAddress = DMA1;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DMA2 */
|
||||
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
|
||||
hdma->DmaBaseAddress = DMA2;
|
||||
}
|
||||
#else
|
||||
/* calculation of the channel index */
|
||||
/* DMA1 */
|
||||
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
|
||||
hdma->DmaBaseAddress = DMA1;
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
547
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c
Normal file
547
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c
Normal file
@@ -0,0 +1,547 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_exti.c
|
||||
* @author MCD Application Team
|
||||
* @brief EXTI HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Extended Interrupts and events controller (EXTI) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + IO operation functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### EXTI Peripheral features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(+) Each Exti line can be configured within this driver.
|
||||
|
||||
(+) Exti line can be configured in 3 different modes
|
||||
(++) Interrupt
|
||||
(++) Event
|
||||
(++) Both of them
|
||||
|
||||
(+) Configurable Exti lines can be configured with 3 different triggers
|
||||
(++) Rising
|
||||
(++) Falling
|
||||
(++) Both of them
|
||||
|
||||
(+) When set in interrupt mode, configurable Exti lines have two different
|
||||
interrupts pending registers which allow to distinguish which transition
|
||||
occurs:
|
||||
(++) Rising edge pending interrupt
|
||||
(++) Falling
|
||||
|
||||
(+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
|
||||
be selected through multiplexer.
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
|
||||
(#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
|
||||
(++) Choose the interrupt line number by setting "Line" member from
|
||||
EXTI_ConfigTypeDef structure.
|
||||
(++) Configure the interrupt and/or event mode using "Mode" member from
|
||||
EXTI_ConfigTypeDef structure.
|
||||
(++) For configurable lines, configure rising and/or falling trigger
|
||||
"Trigger" member from EXTI_ConfigTypeDef structure.
|
||||
(++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
|
||||
member from GPIO_InitTypeDef structure.
|
||||
|
||||
(#) Get current Exti configuration of a dedicated line using
|
||||
HAL_EXTI_GetConfigLine().
|
||||
(++) Provide exiting handle as parameter.
|
||||
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
|
||||
|
||||
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine().
|
||||
(++) Provide exiting handle as parameter.
|
||||
|
||||
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
|
||||
(++) Provide exiting handle as first parameter.
|
||||
(++) Provide which callback will be registered using one value from
|
||||
EXTI_CallbackIDTypeDef.
|
||||
(++) Provide callback function pointer.
|
||||
|
||||
(#) Get interrupt pending bit using HAL_EXTI_GetPending().
|
||||
|
||||
(#) Clear interrupt pending bit using HAL_EXTI_ClearPending().
|
||||
|
||||
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
|
||||
|
||||
@endverbatim
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI
|
||||
* @{
|
||||
*/
|
||||
/** MISRA C:2012 deviation rule has been granted for following rule:
|
||||
* Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
|
||||
* of bounds [0,3] in following API :
|
||||
* HAL_EXTI_SetConfigLine
|
||||
* HAL_EXTI_GetConfigLine
|
||||
* HAL_EXTI_ClearConfigLine
|
||||
*/
|
||||
|
||||
#ifdef HAL_EXTI_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Private_Constants EXTI Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup EXTI_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI_Exported_Functions_Group1
|
||||
* @brief Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Configuration functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set configuration of a dedicated Exti line.
|
||||
* @param hexti Exti handle.
|
||||
* @param pExtiConfig Pointer on EXTI configuration to be set.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t linepos;
|
||||
uint32_t maskline;
|
||||
|
||||
/* Check null pointer */
|
||||
if ((hexti == NULL) || (pExtiConfig == NULL))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_EXTI_LINE(pExtiConfig->Line));
|
||||
assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
|
||||
|
||||
/* Assign line number to handle */
|
||||
hexti->Line = pExtiConfig->Line;
|
||||
|
||||
/* Compute line mask */
|
||||
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
|
||||
maskline = (1uL << linepos);
|
||||
|
||||
/* Configure triggers for configurable lines */
|
||||
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
|
||||
{
|
||||
assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
|
||||
|
||||
/* Configure rising trigger */
|
||||
/* Mask or set line */
|
||||
if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
|
||||
{
|
||||
EXTI->RTSR |= maskline;
|
||||
}
|
||||
else
|
||||
{
|
||||
EXTI->RTSR &= ~maskline;
|
||||
}
|
||||
|
||||
/* Configure falling trigger */
|
||||
/* Mask or set line */
|
||||
if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
|
||||
{
|
||||
EXTI->FTSR |= maskline;
|
||||
}
|
||||
else
|
||||
{
|
||||
EXTI->FTSR &= ~maskline;
|
||||
}
|
||||
|
||||
|
||||
/* Configure gpio port selection in case of gpio exti line */
|
||||
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
|
||||
{
|
||||
assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
|
||||
assert_param(IS_EXTI_GPIO_PIN(linepos));
|
||||
|
||||
regval = SYSCFG->EXTICR[linepos >> 2u];
|
||||
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
|
||||
regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
|
||||
SYSCFG->EXTICR[linepos >> 2u] = regval;
|
||||
}
|
||||
}
|
||||
|
||||
/* Configure interrupt mode : read current mode */
|
||||
/* Mask or set line */
|
||||
if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
|
||||
{
|
||||
EXTI->IMR |= maskline;
|
||||
}
|
||||
else
|
||||
{
|
||||
EXTI->IMR &= ~maskline;
|
||||
}
|
||||
|
||||
/* Configure event mode : read current mode */
|
||||
/* Mask or set line */
|
||||
if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
|
||||
{
|
||||
EXTI->EMR |= maskline;
|
||||
}
|
||||
else
|
||||
{
|
||||
EXTI->EMR &= ~maskline;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get configuration of a dedicated Exti line.
|
||||
* @param hexti Exti handle.
|
||||
* @param pExtiConfig Pointer on structure to store Exti configuration.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t linepos;
|
||||
uint32_t maskline;
|
||||
|
||||
/* Check null pointer */
|
||||
if ((hexti == NULL) || (pExtiConfig == NULL))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
|
||||
/* Store handle line number to configuration structure */
|
||||
pExtiConfig->Line = hexti->Line;
|
||||
|
||||
/* Compute line mask */
|
||||
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
|
||||
maskline = (1uL << linepos);
|
||||
|
||||
/* 1] Get core mode : interrupt */
|
||||
|
||||
/* Check if selected line is enable */
|
||||
if ((EXTI->IMR & maskline) != 0x00u)
|
||||
{
|
||||
pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
|
||||
}
|
||||
else
|
||||
{
|
||||
pExtiConfig->Mode = EXTI_MODE_NONE;
|
||||
}
|
||||
|
||||
/* Get event mode */
|
||||
/* Check if selected line is enable */
|
||||
if ((EXTI->EMR & maskline) != 0x00u)
|
||||
{
|
||||
pExtiConfig->Mode |= EXTI_MODE_EVENT;
|
||||
}
|
||||
|
||||
/* Get default Trigger and GPIOSel configuration */
|
||||
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
|
||||
pExtiConfig->GPIOSel = 0x00u;
|
||||
|
||||
/* 2] Get trigger for configurable lines : rising */
|
||||
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
|
||||
{
|
||||
/* Check if configuration of selected line is enable */
|
||||
if ((EXTI->RTSR & maskline) != 0x00u)
|
||||
{
|
||||
pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
|
||||
}
|
||||
|
||||
/* Get falling configuration */
|
||||
/* Check if configuration of selected line is enable */
|
||||
if ((EXTI->FTSR & maskline) != 0x00u)
|
||||
{
|
||||
pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
|
||||
}
|
||||
|
||||
/* Get Gpio port selection for gpio lines */
|
||||
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
|
||||
{
|
||||
assert_param(IS_EXTI_GPIO_PIN(linepos));
|
||||
|
||||
regval = SYSCFG->EXTICR[linepos >> 2u];
|
||||
pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EXTICR1_EXTI0;
|
||||
}
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear whole configuration of a dedicated Exti line.
|
||||
* @param hexti Exti handle.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t linepos;
|
||||
uint32_t maskline;
|
||||
|
||||
/* Check null pointer */
|
||||
if (hexti == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
|
||||
/* compute line mask */
|
||||
linepos = (hexti->Line & EXTI_PIN_MASK);
|
||||
maskline = (1uL << linepos);
|
||||
|
||||
/* 1] Clear interrupt mode */
|
||||
EXTI->IMR = (EXTI->IMR & ~maskline);
|
||||
|
||||
/* 2] Clear event mode */
|
||||
EXTI->EMR = (EXTI->EMR & ~maskline);
|
||||
|
||||
/* 3] Clear triggers in case of configurable lines */
|
||||
if ((hexti->Line & EXTI_CONFIG) != 0x00u)
|
||||
{
|
||||
EXTI->RTSR = (EXTI->RTSR & ~maskline);
|
||||
EXTI->FTSR = (EXTI->FTSR & ~maskline);
|
||||
|
||||
/* Get Gpio port selection for gpio lines */
|
||||
if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
|
||||
{
|
||||
assert_param(IS_EXTI_GPIO_PIN(linepos));
|
||||
|
||||
regval = SYSCFG->EXTICR[linepos >> 2u];
|
||||
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
|
||||
SYSCFG->EXTICR[linepos >> 2u] = regval;
|
||||
}
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Register callback for a dedicated Exti line.
|
||||
* @param hexti Exti handle.
|
||||
* @param CallbackID User callback identifier.
|
||||
* This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
|
||||
* @param pPendingCbfn function pointer to be stored as callback.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_EXTI_COMMON_CB_ID:
|
||||
hexti->PendingCallback = pPendingCbfn;
|
||||
break;
|
||||
|
||||
default:
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Store line number as handle private field.
|
||||
* @param hexti Exti handle.
|
||||
* @param ExtiLine Exti line number.
|
||||
* This parameter can be from 0 to @ref EXTI_LINE_NB.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_LINE(ExtiLine));
|
||||
|
||||
/* Check null pointer */
|
||||
if (hexti == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Store line number as handle private field */
|
||||
hexti->Line = ExtiLine;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI_Exported_Functions_Group2
|
||||
* @brief EXTI IO functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Handle EXTI interrupt request.
|
||||
* @param hexti Exti handle.
|
||||
* @retval none.
|
||||
*/
|
||||
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t maskline;
|
||||
|
||||
/* Compute line mask */
|
||||
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
|
||||
|
||||
/* Get pending bit */
|
||||
regval = (EXTI->PR & maskline);
|
||||
if (regval != 0x00u)
|
||||
{
|
||||
/* Clear pending bit */
|
||||
EXTI->PR = maskline;
|
||||
|
||||
/* Call callback */
|
||||
if (hexti->PendingCallback != NULL)
|
||||
{
|
||||
hexti->PendingCallback();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get interrupt pending bit of a dedicated line.
|
||||
* @param hexti Exti handle.
|
||||
* @param Edge Specify which pending edge as to be checked.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref EXTI_TRIGGER_RISING_FALLING
|
||||
* This parameter is kept for compatibility with other series.
|
||||
* @retval 1 if interrupt is pending else 0.
|
||||
*/
|
||||
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t linepos;
|
||||
uint32_t maskline;
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_PENDING_EDGE(Edge));
|
||||
|
||||
/* Compute line mask */
|
||||
linepos = (hexti->Line & EXTI_PIN_MASK);
|
||||
maskline = (1uL << linepos);
|
||||
|
||||
/* return 1 if bit is set else 0 */
|
||||
regval = ((EXTI->PR & maskline) >> linepos);
|
||||
return regval;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear interrupt pending bit of a dedicated line.
|
||||
* @param hexti Exti handle.
|
||||
* @param Edge Specify which pending edge as to be clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref EXTI_TRIGGER_RISING_FALLING
|
||||
* This parameter is kept for compatibility with other series.
|
||||
* @retval None.
|
||||
*/
|
||||
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
|
||||
{
|
||||
uint32_t maskline;
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_PENDING_EDGE(Edge));
|
||||
|
||||
/* Compute line mask */
|
||||
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
|
||||
|
||||
/* Clear Pending bit */
|
||||
EXTI->PR = maskline;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Generate a software interrupt for a dedicated line.
|
||||
* @param hexti Exti handle.
|
||||
* @retval None.
|
||||
*/
|
||||
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
|
||||
{
|
||||
uint32_t maskline;
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
|
||||
|
||||
/* Compute line mask */
|
||||
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
|
||||
|
||||
/* Generate Software interrupt */
|
||||
EXTI->SWIER = maskline;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_EXTI_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
691
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c
Normal file
691
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c
Normal file
@@ -0,0 +1,691 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_flash.c
|
||||
* @author MCD Application Team
|
||||
* @brief FLASH HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the internal FLASH memory:
|
||||
* + Program operations functions
|
||||
* + Memory Control functions
|
||||
* + Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### FLASH peripheral features #####
|
||||
==============================================================================
|
||||
[..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
|
||||
to the Flash memory. It implements the erase and program Flash memory operations
|
||||
and the read and write protection mechanisms.
|
||||
|
||||
[..] The Flash memory interface accelerates code execution with a system of instruction
|
||||
prefetch.
|
||||
|
||||
[..] The FLASH main features are:
|
||||
(+) Flash memory read operations
|
||||
(+) Flash memory program/erase operations
|
||||
(+) Read / write protections
|
||||
(+) Prefetch on I-Code
|
||||
(+) Option Bytes programming
|
||||
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This driver provides functions and macros to configure and program the FLASH
|
||||
memory of all STM32F0xx devices.
|
||||
|
||||
(#) FLASH Memory I/O Programming functions: this group includes all needed
|
||||
functions to erase and program the main memory:
|
||||
(++) Lock and Unlock the FLASH interface
|
||||
(++) Erase function: Erase page, erase all pages
|
||||
(++) Program functions: half word, word and doubleword
|
||||
(#) FLASH Option Bytes Programming functions: this group includes all needed
|
||||
functions to manage the Option Bytes:
|
||||
(++) Lock and Unlock the Option Bytes
|
||||
(++) Set/Reset the write protection
|
||||
(++) Set the Read protection Level
|
||||
(++) Program the user Option Bytes
|
||||
(++) Launch the Option Bytes loader
|
||||
(++) Erase Option Bytes
|
||||
(++) Program the data Option Bytes
|
||||
(++) Get the Write protection.
|
||||
(++) Get the user option bytes.
|
||||
|
||||
(#) Interrupts and flags management functions : this group
|
||||
includes all needed functions to:
|
||||
(++) Handle FLASH interrupts
|
||||
(++) Wait for last FLASH operation according to its status
|
||||
(++) Get error flag status
|
||||
|
||||
[..] In addition to these function, this driver includes a set of macros allowing
|
||||
to handle the following operations:
|
||||
|
||||
(+) Set/Get the latency
|
||||
(+) Enable/Disable the prefetch buffer
|
||||
(+) Enable/Disable the FLASH interrupts
|
||||
(+) Monitor the FLASH flags status
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
|
||||
/** @defgroup FLASH FLASH
|
||||
* @brief FLASH HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Constants FLASH Private Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro ---------------------------- ---------------------------------*/
|
||||
/** @defgroup FLASH_Private_Macros FLASH Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Variables FLASH Private Variables
|
||||
* @{
|
||||
*/
|
||||
/* Variables used for Erase pages under interruption*/
|
||||
FLASH_ProcessTypeDef pFlash;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Functions FLASH Private Functions
|
||||
* @{
|
||||
*/
|
||||
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
|
||||
static void FLASH_SetErrorCode(void);
|
||||
extern void FLASH_PageErase(uint32_t PageAddress);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ---------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
|
||||
* @brief Programming operation functions
|
||||
*
|
||||
@verbatim
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Program halfword, word or double word at a specified address
|
||||
* @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
|
||||
* The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
|
||||
*
|
||||
* @note If an erase and a program operations are requested simultaneously,
|
||||
* the erase operation is performed before the program one.
|
||||
*
|
||||
* @note FLASH should be previously erased before new programming (only exception to this
|
||||
* is when 0x0000 is programmed)
|
||||
*
|
||||
* @param TypeProgram Indicate the way to program at a specified address.
|
||||
* This parameter can be a value of @ref FLASH_Type_Program
|
||||
* @param Address Specifie the address to be programmed.
|
||||
* @param Data Specifie the data to be programmed
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_ERROR;
|
||||
uint8_t index = 0U;
|
||||
uint8_t nbiterations = 0U;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
|
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
|
||||
{
|
||||
/* Program halfword (16-bit) at a specified address. */
|
||||
nbiterations = 1U;
|
||||
}
|
||||
else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
|
||||
{
|
||||
/* Program word (32-bit = 2*16-bit) at a specified address. */
|
||||
nbiterations = 2U;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Program double word (64-bit = 4*16-bit) at a specified address. */
|
||||
nbiterations = 4U;
|
||||
}
|
||||
|
||||
for (index = 0U; index < nbiterations; index++)
|
||||
{
|
||||
FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index)));
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* If the program operation is completed, disable the PG Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
|
||||
/* In case of error, stop programming procedure */
|
||||
if (status != HAL_OK)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Program halfword, word or double word at a specified address with interrupt enabled.
|
||||
* @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
|
||||
* The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
|
||||
*
|
||||
* @note If an erase and a program operations are requested simultaneously,
|
||||
* the erase operation is performed before the program one.
|
||||
*
|
||||
* @param TypeProgram Indicate the way to program at a specified address.
|
||||
* This parameter can be a value of @ref FLASH_Type_Program
|
||||
* @param Address Specifie the address to be programmed.
|
||||
* @param Data Specifie the data to be programmed
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
|
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
|
||||
|
||||
/* Enable End of FLASH Operation and Error source interrupts */
|
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
|
||||
|
||||
pFlash.Address = Address;
|
||||
pFlash.Data = Data;
|
||||
|
||||
if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
|
||||
{
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD;
|
||||
/* Program halfword (16-bit) at a specified address. */
|
||||
pFlash.DataRemaining = 1U;
|
||||
}
|
||||
else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
|
||||
{
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD;
|
||||
/* Program word (32-bit : 2*16-bit) at a specified address. */
|
||||
pFlash.DataRemaining = 2U;
|
||||
}
|
||||
else
|
||||
{
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD;
|
||||
/* Program double word (64-bit : 4*16-bit) at a specified address. */
|
||||
pFlash.DataRemaining = 4U;
|
||||
}
|
||||
|
||||
/* Program halfword (16-bit) at a specified address. */
|
||||
FLASH_Program_HalfWord(Address, (uint16_t)Data);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles FLASH interrupt request.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASH_IRQHandler(void)
|
||||
{
|
||||
uint32_t addresstmp = 0U;
|
||||
|
||||
/* Check FLASH operation error flags */
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
|
||||
{
|
||||
/* Return the faulty address */
|
||||
addresstmp = pFlash.Address;
|
||||
/* Reset address */
|
||||
pFlash.Address = 0xFFFFFFFFU;
|
||||
|
||||
/* Save the Error code */
|
||||
FLASH_SetErrorCode();
|
||||
|
||||
/* FLASH error interrupt user callback */
|
||||
HAL_FLASH_OperationErrorCallback(addresstmp);
|
||||
|
||||
/* Stop the procedure ongoing */
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
|
||||
}
|
||||
|
||||
/* Check FLASH End of Operation flag */
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
|
||||
{
|
||||
/* Clear FLASH End of Operation pending bit */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
|
||||
|
||||
/* Process can continue only if no error detected */
|
||||
if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
|
||||
{
|
||||
if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
|
||||
{
|
||||
/* Nb of pages to erased can be decreased */
|
||||
pFlash.DataRemaining--;
|
||||
|
||||
/* Check if there are still pages to erase */
|
||||
if(pFlash.DataRemaining != 0U)
|
||||
{
|
||||
addresstmp = pFlash.Address;
|
||||
/*Indicate user which sector has been erased */
|
||||
HAL_FLASH_EndOfOperationCallback(addresstmp);
|
||||
|
||||
/*Increment sector number*/
|
||||
addresstmp = pFlash.Address + FLASH_PAGE_SIZE;
|
||||
pFlash.Address = addresstmp;
|
||||
|
||||
/* If the erase operation is completed, disable the PER Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
|
||||
|
||||
FLASH_PageErase(addresstmp);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* No more pages to Erase, user callback can be called. */
|
||||
/* Reset Sector and stop Erase pages procedure */
|
||||
pFlash.Address = addresstmp = 0xFFFFFFFFU;
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
|
||||
/* FLASH EOP interrupt user callback */
|
||||
HAL_FLASH_EndOfOperationCallback(addresstmp);
|
||||
}
|
||||
}
|
||||
else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
|
||||
{
|
||||
/* Operation is completed, disable the MER Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
|
||||
|
||||
/* MassErase ended. Return the selected bank */
|
||||
/* FLASH EOP interrupt user callback */
|
||||
HAL_FLASH_EndOfOperationCallback(0);
|
||||
|
||||
/* Stop Mass Erase procedure*/
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Nb of 16-bit data to program can be decreased */
|
||||
pFlash.DataRemaining--;
|
||||
|
||||
/* Check if there are still 16-bit data to program */
|
||||
if(pFlash.DataRemaining != 0U)
|
||||
{
|
||||
/* Increment address to 16-bit */
|
||||
pFlash.Address += 2;
|
||||
addresstmp = pFlash.Address;
|
||||
|
||||
/* Shift to have next 16-bit data */
|
||||
pFlash.Data = (pFlash.Data >> 16U);
|
||||
|
||||
/* Operation is completed, disable the PG Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
|
||||
|
||||
/*Program halfword (16-bit) at a specified address.*/
|
||||
FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Program ended. Return the selected address */
|
||||
/* FLASH EOP interrupt user callback */
|
||||
if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD)
|
||||
{
|
||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address);
|
||||
}
|
||||
else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD)
|
||||
{
|
||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U);
|
||||
}
|
||||
else
|
||||
{
|
||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U);
|
||||
}
|
||||
|
||||
/* Reset Address and stop Program procedure */
|
||||
pFlash.Address = 0xFFFFFFFFU;
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
|
||||
{
|
||||
/* Operation is completed, disable the PG, PER and MER Bits */
|
||||
CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER));
|
||||
|
||||
/* Disable End of FLASH Operation and Error source interrupts */
|
||||
__HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief FLASH end of operation interrupt callback
|
||||
* @param ReturnValue The value saved in this parameter depends on the ongoing procedure
|
||||
* - Mass Erase: No return value expected
|
||||
* - Pages Erase: Address of the page which has been erased
|
||||
* (if 0xFFFFFFFF, it means that all the selected pages have been erased)
|
||||
* - Program: Address which was selected for data program
|
||||
* @retval none
|
||||
*/
|
||||
__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(ReturnValue);
|
||||
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief FLASH operation error interrupt callback
|
||||
* @param ReturnValue The value saved in this parameter depends on the ongoing procedure
|
||||
* - Mass Erase: No return value expected
|
||||
* - Pages Erase: Address of the page which returned an error
|
||||
* - Program: Address which was selected for data program
|
||||
* @retval none
|
||||
*/
|
||||
__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(ReturnValue);
|
||||
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_FLASH_OperationErrorCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the FLASH
|
||||
memory operations.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Unlock the FLASH control register access
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
|
||||
{
|
||||
/* Authorize the FLASH Registers access */
|
||||
WRITE_REG(FLASH->KEYR, FLASH_KEY1);
|
||||
WRITE_REG(FLASH->KEYR, FLASH_KEY2);
|
||||
|
||||
/* Verify Flash is unlocked */
|
||||
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Locks the FLASH control register access
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Lock(void)
|
||||
{
|
||||
/* Set the LOCK Bit to lock the FLASH Registers access */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_LOCK);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unlock the FLASH Option Control Registers access.
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
|
||||
{
|
||||
if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE))
|
||||
{
|
||||
/* Authorizes the Option Byte register programming */
|
||||
WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
|
||||
WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Lock the FLASH Option Control Registers access.
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
|
||||
{
|
||||
/* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Launch the option byte loading.
|
||||
* @note This function will reset automatically the MCU.
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
|
||||
{
|
||||
/* Set the OBL_Launch bit to launch the option byte loading */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
return(FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions
|
||||
* @brief Peripheral errors functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Errors functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection permit to get in run-time errors of the FLASH peripheral.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get the specific FLASH error flag.
|
||||
* @retval FLASH_ErrorCode The returned value can be:
|
||||
* @ref FLASH_Error_Codes
|
||||
*/
|
||||
uint32_t HAL_FLASH_GetError(void)
|
||||
{
|
||||
return pFlash.ErrorCode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Program a half-word (16-bit) at a specified address.
|
||||
* @param Address specify the address to be programmed.
|
||||
* @param Data specify the data to be programmed.
|
||||
* @retval None
|
||||
*/
|
||||
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
|
||||
{
|
||||
/* Clean the error context */
|
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
|
||||
/* Proceed to program the new data */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_PG);
|
||||
|
||||
/* Write data in the address */
|
||||
*(__IO uint16_t*)Address = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Wait for a FLASH operation to complete.
|
||||
* @param Timeout maximum flash operation timeout
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
|
||||
{
|
||||
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
|
||||
Even if the FLASH operation fails, the BUSY flag will be reset and an error
|
||||
flag will be set */
|
||||
|
||||
uint32_t tickstart = HAL_GetTick();
|
||||
|
||||
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
|
||||
{
|
||||
if (Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Check FLASH End of Operation flag */
|
||||
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
|
||||
{
|
||||
/* Clear FLASH End of Operation pending bit */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
|
||||
}
|
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
|
||||
{
|
||||
/*Save the error code*/
|
||||
FLASH_SetErrorCode();
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* There is no error flag set */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Set the specific FLASH error flag.
|
||||
* @retval None
|
||||
*/
|
||||
static void FLASH_SetErrorCode(void)
|
||||
{
|
||||
uint32_t flags = 0U;
|
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
|
||||
flags |= FLASH_FLAG_WRPERR;
|
||||
}
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;
|
||||
flags |= FLASH_FLAG_PGERR;
|
||||
}
|
||||
/* Clear FLASH error pending bits */
|
||||
__HAL_FLASH_CLEAR_FLAG(flags);
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
981
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c
Normal file
981
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c
Normal file
@@ -0,0 +1,981 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_flash_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief Extended FLASH HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the FLASH peripheral:
|
||||
* + Extended Initialization/de-initialization functions
|
||||
* + Extended I/O operation functions
|
||||
* + Extended Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Flash peripheral extended features #####
|
||||
==============================================================================
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..] This driver provides functions to configure and program the FLASH memory
|
||||
of all STM32F0xxx devices. It includes
|
||||
|
||||
(++) Set/Reset the write protection
|
||||
(++) Program the user Option Bytes
|
||||
(++) Get the Read protection Level
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
/** @addtogroup FLASH_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/* Variables used for Erase pages under interruption*/
|
||||
extern FLASH_ProcessTypeDef pFlash;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx FLASHEx
|
||||
* @brief FLASH HAL Extension module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_POSITION_IWDGSW_BIT 8U
|
||||
#define FLASH_POSITION_OB_USERDATA0_BIT 16U
|
||||
#define FLASH_POSITION_OB_USERDATA1_BIT 24U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
|
||||
* @{
|
||||
*/
|
||||
/* Erase operations */
|
||||
static void FLASH_MassErase(void);
|
||||
void FLASH_PageErase(uint32_t PageAddress);
|
||||
|
||||
/* Option bytes control */
|
||||
static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage);
|
||||
static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage);
|
||||
static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel);
|
||||
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig);
|
||||
static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data);
|
||||
static uint32_t FLASH_OB_GetWRP(void);
|
||||
static uint32_t FLASH_OB_GetRDP(void);
|
||||
static uint8_t FLASH_OB_GetUser(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ---------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions
|
||||
* @brief FLASH Memory Erasing functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### FLASH Erasing Programming functions #####
|
||||
==============================================================================
|
||||
|
||||
[..] The FLASH Memory Erasing functions, includes the following functions:
|
||||
(+) HAL_FLASHEx_Erase: return only when erase has been done
|
||||
(+) HAL_FLASHEx_Erase_IT: end of erase is done when HAL_FLASH_EndOfOperationCallback
|
||||
is called with parameter 0xFFFFFFFF
|
||||
|
||||
[..] Any operation of erase should follow these steps:
|
||||
(#) Call the HAL_FLASH_Unlock() function to enable the flash control register and
|
||||
program memory access.
|
||||
(#) Call the desired function to erase page.
|
||||
(#) Call the HAL_FLASH_Lock() to disable the flash program memory access
|
||||
(recommended to protect the FLASH memory against possible unwanted operation).
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Perform a mass erase or erase the specified FLASH memory pages
|
||||
* @note To correctly run this function, the @ref HAL_FLASH_Unlock() function
|
||||
* must be called before.
|
||||
* Call the @ref HAL_FLASH_Lock() to disable the flash memory access
|
||||
* (recommended to protect the FLASH memory against possible unwanted operation)
|
||||
* @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
|
||||
* contains the configuration information for the erasing.
|
||||
*
|
||||
* @param[out] PageError pointer to variable that
|
||||
* contains the configuration information on faulty page in case of error
|
||||
* (0xFFFFFFFF means that all the pages have been correctly erased)
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_ERROR;
|
||||
uint32_t address = 0U;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
|
||||
|
||||
if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
|
||||
{
|
||||
/* Mass Erase requested for Bank1 */
|
||||
/* Wait for last operation to be completed */
|
||||
if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
|
||||
{
|
||||
/*Mass erase to be done*/
|
||||
FLASH_MassErase();
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* If the erase operation is completed, disable the MER Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Page Erase is requested */
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
|
||||
assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));
|
||||
|
||||
/* Page Erase requested on address located on bank1 */
|
||||
/* Wait for last operation to be completed */
|
||||
if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
|
||||
{
|
||||
/*Initialization of PageError variable*/
|
||||
*PageError = 0xFFFFFFFFU;
|
||||
|
||||
/* Erase page by page to be done*/
|
||||
for(address = pEraseInit->PageAddress;
|
||||
address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);
|
||||
address += FLASH_PAGE_SIZE)
|
||||
{
|
||||
FLASH_PageErase(address);
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* If the erase operation is completed, disable the PER Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
|
||||
|
||||
if (status != HAL_OK)
|
||||
{
|
||||
/* In case of error, stop erase procedure and return the faulty address */
|
||||
*PageError = address;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled
|
||||
* @note To correctly run this function, the @ref HAL_FLASH_Unlock() function
|
||||
* must be called before.
|
||||
* Call the @ref HAL_FLASH_Lock() to disable the flash memory access
|
||||
* (recommended to protect the FLASH memory against possible unwanted operation)
|
||||
* @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
|
||||
* contains the configuration information for the erasing.
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* If procedure already ongoing, reject the next one */
|
||||
if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
|
||||
|
||||
/* Enable End of FLASH Operation and Error source interrupts */
|
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
|
||||
|
||||
if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
|
||||
{
|
||||
/*Mass erase to be done*/
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
|
||||
FLASH_MassErase();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Erase by page to be done*/
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
|
||||
assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));
|
||||
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE;
|
||||
pFlash.DataRemaining = pEraseInit->NbPages;
|
||||
pFlash.Address = pEraseInit->PageAddress;
|
||||
|
||||
/*Erase 1st page and wait for IT*/
|
||||
FLASH_PageErase(pEraseInit->PageAddress);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions
|
||||
* @brief Option Bytes Programming functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Option Bytes Programming functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the FLASH
|
||||
option bytes operations.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Erases the FLASH option bytes.
|
||||
* @note This functions erases all option bytes except the Read protection (RDP).
|
||||
* The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
|
||||
* The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
|
||||
* The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
|
||||
* (system reset will occur)
|
||||
* @retval HAL status
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OBErase(void)
|
||||
{
|
||||
uint8_t rdptmp = OB_RDP_LEVEL_0;
|
||||
HAL_StatusTypeDef status = HAL_ERROR;
|
||||
|
||||
/* Get the actual read protection Option Byte value */
|
||||
rdptmp = FLASH_OB_GetRDP();
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Clean the error context */
|
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
|
||||
/* If the previous operation is completed, proceed to erase the option bytes */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OPTER);
|
||||
SET_BIT(FLASH->CR, FLASH_CR_STRT);
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* If the erase operation is completed, disable the OPTER Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Restore the last read protection Option Byte value */
|
||||
status = FLASH_OB_RDP_LevelConfig(rdptmp);
|
||||
}
|
||||
}
|
||||
|
||||
/* Return the erase status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Program option bytes
|
||||
* @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
|
||||
* The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
|
||||
* The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
|
||||
* (system reset will occur)
|
||||
*
|
||||
* @param pOBInit pointer to an FLASH_OBInitStruct structure that
|
||||
* contains the configuration information for the programming.
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_ERROR;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
|
||||
|
||||
/* Write protection configuration */
|
||||
if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
|
||||
{
|
||||
assert_param(IS_WRPSTATE(pOBInit->WRPState));
|
||||
if (pOBInit->WRPState == OB_WRPSTATE_ENABLE)
|
||||
{
|
||||
/* Enable of Write protection on the selected page */
|
||||
status = FLASH_OB_EnableWRP(pOBInit->WRPPage);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable of Write protection on the selected page */
|
||||
status = FLASH_OB_DisableWRP(pOBInit->WRPPage);
|
||||
}
|
||||
if (status != HAL_OK)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
return status;
|
||||
}
|
||||
}
|
||||
|
||||
/* Read protection configuration */
|
||||
if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
|
||||
{
|
||||
status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);
|
||||
if (status != HAL_OK)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
return status;
|
||||
}
|
||||
}
|
||||
|
||||
/* USER configuration */
|
||||
if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
|
||||
{
|
||||
status = FLASH_OB_UserConfig(pOBInit->USERConfig);
|
||||
if (status != HAL_OK)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
return status;
|
||||
}
|
||||
}
|
||||
|
||||
/* DATA configuration*/
|
||||
if((pOBInit->OptionType & OPTIONBYTE_DATA) == OPTIONBYTE_DATA)
|
||||
{
|
||||
status = FLASH_OB_ProgramData(pOBInit->DATAAddress, pOBInit->DATAData);
|
||||
if (status != HAL_OK)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
return status;
|
||||
}
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the Option byte configuration
|
||||
* @param pOBInit pointer to an FLASH_OBInitStruct structure that
|
||||
* contains the configuration information for the programming.
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
|
||||
{
|
||||
pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER;
|
||||
|
||||
/*Get WRP*/
|
||||
pOBInit->WRPPage = FLASH_OB_GetWRP();
|
||||
|
||||
/*Get RDP Level*/
|
||||
pOBInit->RDPLevel = FLASH_OB_GetRDP();
|
||||
|
||||
/*Get USER*/
|
||||
pOBInit->USERConfig = FLASH_OB_GetUser();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the Option byte user data
|
||||
* @param DATAAdress Address of the option byte DATA
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref OB_DATA_ADDRESS_DATA0
|
||||
* @arg @ref OB_DATA_ADDRESS_DATA1
|
||||
* @retval Value programmed in USER data
|
||||
*/
|
||||
uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress)
|
||||
{
|
||||
uint32_t value = 0U;
|
||||
|
||||
if (DATAAdress == OB_DATA_ADDRESS_DATA0)
|
||||
{
|
||||
/* Get value programmed in OB USER Data0 */
|
||||
value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA0) >> FLASH_POSITION_OB_USERDATA0_BIT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Get value programmed in OB USER Data1 */
|
||||
value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA1) >> FLASH_POSITION_OB_USERDATA1_BIT;
|
||||
}
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Full erase of FLASH memory Bank
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
static void FLASH_MassErase(void)
|
||||
{
|
||||
/* Clean the error context */
|
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
|
||||
/* Only bank1 will be erased*/
|
||||
SET_BIT(FLASH->CR, FLASH_CR_MER);
|
||||
SET_BIT(FLASH->CR, FLASH_CR_STRT);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the write protection of the desired pages
|
||||
* @note An option byte erase is done automatically in this function.
|
||||
* @note When the memory read protection level is selected (RDP level = 1),
|
||||
* it is not possible to program or erase the flash page i if
|
||||
* debug features are connected or boot code is executed in RAM, even if nWRPi = 1
|
||||
*
|
||||
* @param WriteProtectPage specifies the page(s) to be write protected.
|
||||
* The value of this parameter depend on device used within the same series
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint16_t WRP0_Data = 0xFFFFU;
|
||||
#if defined(OB_WRP1_WRP1)
|
||||
uint16_t WRP1_Data = 0xFFFFU;
|
||||
#endif /* OB_WRP1_WRP1 */
|
||||
#if defined(OB_WRP2_WRP2)
|
||||
uint16_t WRP2_Data = 0xFFFFU;
|
||||
#endif /* OB_WRP2_WRP2 */
|
||||
#if defined(OB_WRP3_WRP3)
|
||||
uint16_t WRP3_Data = 0xFFFFU;
|
||||
#endif /* OB_WRP3_WRP3 */
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_WRP(WriteProtectPage));
|
||||
|
||||
/* Get current write protected pages and the new pages to be protected ******/
|
||||
WriteProtectPage = (uint32_t)(~((~FLASH_OB_GetWRP()) | WriteProtectPage));
|
||||
|
||||
#if defined(OB_WRP_PAGES0TO15MASK)
|
||||
WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
|
||||
#elif defined(OB_WRP_PAGES0TO31MASK)
|
||||
WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK);
|
||||
#endif /* OB_WRP_PAGES0TO31MASK */
|
||||
|
||||
#if defined(OB_WRP_PAGES16TO31MASK)
|
||||
WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U);
|
||||
#elif defined(OB_WRP_PAGES32TO63MASK)
|
||||
WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U);
|
||||
#endif /* OB_WRP_PAGES32TO63MASK */
|
||||
|
||||
#if defined(OB_WRP_PAGES32TO47MASK)
|
||||
WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U);
|
||||
#endif /* OB_WRP_PAGES32TO47MASK */
|
||||
|
||||
#if defined(OB_WRP_PAGES48TO63MASK)
|
||||
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO63MASK) >> 24U);
|
||||
#elif defined(OB_WRP_PAGES48TO127MASK)
|
||||
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U);
|
||||
#endif /* OB_WRP_PAGES48TO63MASK */
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Clean the error context */
|
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
|
||||
/* To be able to write again option byte, need to perform a option byte erase */
|
||||
status = HAL_FLASHEx_OBErase();
|
||||
if (status == HAL_OK)
|
||||
{
|
||||
/* Enable write protection */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
|
||||
#if defined(OB_WRP0_WRP0)
|
||||
if(WRP0_Data != 0xFFU)
|
||||
{
|
||||
OB->WRP0 &= WRP0_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
#endif /* OB_WRP0_WRP0 */
|
||||
|
||||
#if defined(OB_WRP1_WRP1)
|
||||
if((status == HAL_OK) && (WRP1_Data != 0xFFU))
|
||||
{
|
||||
OB->WRP1 &= WRP1_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
#endif /* OB_WRP1_WRP1 */
|
||||
|
||||
#if defined(OB_WRP2_WRP2)
|
||||
if((status == HAL_OK) && (WRP2_Data != 0xFFU))
|
||||
{
|
||||
OB->WRP2 &= WRP2_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
#endif /* OB_WRP2_WRP2 */
|
||||
|
||||
#if defined(OB_WRP3_WRP3)
|
||||
if((status == HAL_OK) && (WRP3_Data != 0xFFU))
|
||||
{
|
||||
OB->WRP3 &= WRP3_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
#endif /* OB_WRP3_WRP3 */
|
||||
|
||||
/* if the program operation is completed, disable the OPTPG Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the write protection of the desired pages
|
||||
* @note An option byte erase is done automatically in this function.
|
||||
* @note When the memory read protection level is selected (RDP level = 1),
|
||||
* it is not possible to program or erase the flash page i if
|
||||
* debug features are connected or boot code is executed in RAM, even if nWRPi = 1
|
||||
*
|
||||
* @param WriteProtectPage specifies the page(s) to be write unprotected.
|
||||
* The value of this parameter depend on device used within the same series
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint16_t WRP0_Data = 0xFFFFU;
|
||||
#if defined(OB_WRP1_WRP1)
|
||||
uint16_t WRP1_Data = 0xFFFFU;
|
||||
#endif /* OB_WRP1_WRP1 */
|
||||
#if defined(OB_WRP2_WRP2)
|
||||
uint16_t WRP2_Data = 0xFFFFU;
|
||||
#endif /* OB_WRP2_WRP2 */
|
||||
#if defined(OB_WRP3_WRP3)
|
||||
uint16_t WRP3_Data = 0xFFFFU;
|
||||
#endif /* OB_WRP3_WRP3 */
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_WRP(WriteProtectPage));
|
||||
|
||||
/* Get current write protected pages and the new pages to be unprotected ******/
|
||||
WriteProtectPage = (FLASH_OB_GetWRP() | WriteProtectPage);
|
||||
|
||||
#if defined(OB_WRP_PAGES0TO15MASK)
|
||||
WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
|
||||
#elif defined(OB_WRP_PAGES0TO31MASK)
|
||||
WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK);
|
||||
#endif /* OB_WRP_PAGES0TO31MASK */
|
||||
|
||||
#if defined(OB_WRP_PAGES16TO31MASK)
|
||||
WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U);
|
||||
#elif defined(OB_WRP_PAGES32TO63MASK)
|
||||
WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U);
|
||||
#endif /* OB_WRP_PAGES32TO63MASK */
|
||||
|
||||
#if defined(OB_WRP_PAGES32TO47MASK)
|
||||
WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U);
|
||||
#endif /* OB_WRP_PAGES32TO47MASK */
|
||||
|
||||
#if defined(OB_WRP_PAGES48TO63MASK)
|
||||
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO63MASK) >> 24U);
|
||||
#elif defined(OB_WRP_PAGES48TO127MASK)
|
||||
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U);
|
||||
#endif /* OB_WRP_PAGES48TO63MASK */
|
||||
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Clean the error context */
|
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
|
||||
/* To be able to write again option byte, need to perform a option byte erase */
|
||||
status = HAL_FLASHEx_OBErase();
|
||||
if (status == HAL_OK)
|
||||
{
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
|
||||
#if defined(OB_WRP0_WRP0)
|
||||
if(WRP0_Data != 0xFFU)
|
||||
{
|
||||
OB->WRP0 &= WRP0_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
#endif /* OB_WRP0_WRP0 */
|
||||
|
||||
#if defined(OB_WRP1_WRP1)
|
||||
if((status == HAL_OK) && (WRP1_Data != 0xFFU))
|
||||
{
|
||||
OB->WRP1 &= WRP1_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
#endif /* OB_WRP1_WRP1 */
|
||||
|
||||
#if defined(OB_WRP2_WRP2)
|
||||
if((status == HAL_OK) && (WRP2_Data != 0xFFU))
|
||||
{
|
||||
OB->WRP2 &= WRP2_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
#endif /* OB_WRP2_WRP2 */
|
||||
|
||||
#if defined(OB_WRP3_WRP3)
|
||||
if((status == HAL_OK) && (WRP3_Data != 0xFFU))
|
||||
{
|
||||
OB->WRP3 &= WRP3_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
#endif /* OB_WRP3_WRP3 */
|
||||
|
||||
/* if the program operation is completed, disable the OPTPG Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
}
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the read protection level.
|
||||
* @param ReadProtectLevel specifies the read protection level.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref OB_RDP_LEVEL_0 No protection
|
||||
* @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
|
||||
* @arg @ref OB_RDP_LEVEL_2 Full chip protection
|
||||
* @note Warning: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel));
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Clean the error context */
|
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
|
||||
/* If the previous operation is completed, proceed to erase the option bytes */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OPTER);
|
||||
SET_BIT(FLASH->CR, FLASH_CR_STRT);
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* If the erase operation is completed, disable the OPTER Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Enable the Option Bytes Programming operation */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
|
||||
WRITE_REG(OB->RDP, ReadProtectLevel);
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* if the program operation is completed, disable the OPTPG Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Program the FLASH User Option Byte.
|
||||
* @note Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
|
||||
* @param UserConfig The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nBOOT1(Bit4),
|
||||
* VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6).
|
||||
* For few devices, following option bytes are available: nBOOT0(Bit3) & BOOT_SEL(Bit7).
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_IWDG_SOURCE((UserConfig&OB_IWDG_SW)));
|
||||
assert_param(IS_OB_STOP_SOURCE((UserConfig&OB_STOP_NO_RST)));
|
||||
assert_param(IS_OB_STDBY_SOURCE((UserConfig&OB_STDBY_NO_RST)));
|
||||
assert_param(IS_OB_BOOT1((UserConfig&OB_BOOT1_SET)));
|
||||
assert_param(IS_OB_VDDA_ANALOG((UserConfig&OB_VDDA_ANALOG_ON)));
|
||||
assert_param(IS_OB_SRAM_PARITY((UserConfig&OB_SRAM_PARITY_RESET)));
|
||||
#if defined(FLASH_OBR_BOOT_SEL)
|
||||
assert_param(IS_OB_BOOT_SEL((UserConfig&OB_BOOT_SEL_SET)));
|
||||
assert_param(IS_OB_BOOT0((UserConfig&OB_BOOT0_SET)));
|
||||
#endif /* FLASH_OBR_BOOT_SEL */
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Clean the error context */
|
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
|
||||
/* Enable the Option Bytes Programming operation */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
|
||||
#if defined(FLASH_OBR_BOOT_SEL)
|
||||
OB->USER = UserConfig;
|
||||
#else
|
||||
OB->USER = (UserConfig | 0x88U);
|
||||
#endif
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* if the program operation is completed, disable the OPTPG Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Programs a half word at a specified Option Byte Data address.
|
||||
* @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
|
||||
* The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
|
||||
* The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
|
||||
* (system reset will occur)
|
||||
* Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
|
||||
* @param Address specifies the address to be programmed.
|
||||
* This parameter can be 0x1FFFF804 or 0x1FFFF806.
|
||||
* @param Data specifies the data to be programmed.
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_ERROR;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_DATA_ADDRESS(Address));
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Clean the error context */
|
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
|
||||
/* Enables the Option Bytes Programming operation */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
*(__IO uint16_t*)Address = Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* If the program operation is completed, disable the OPTPG Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
}
|
||||
/* Return the Option Byte Data Program Status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the FLASH Write Protection Option Bytes value.
|
||||
* @retval The FLASH Write Protection Option Bytes value
|
||||
*/
|
||||
static uint32_t FLASH_OB_GetWRP(void)
|
||||
{
|
||||
/* Return the FLASH write protection Register value */
|
||||
return (uint32_t)(READ_REG(FLASH->WRPR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the FLASH Read Protection level.
|
||||
* @retval FLASH RDP level
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref OB_RDP_LEVEL_0 No protection
|
||||
* @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
|
||||
* @arg @ref OB_RDP_LEVEL_2 Full chip protection
|
||||
*/
|
||||
static uint32_t FLASH_OB_GetRDP(void)
|
||||
{
|
||||
uint32_t tmp_reg;
|
||||
|
||||
/* Read RDP level bits */
|
||||
tmp_reg = READ_BIT(FLASH->OBR, (FLASH_OBR_RDPRT1 | FLASH_OBR_RDPRT2));
|
||||
|
||||
if (tmp_reg == 0U)
|
||||
{
|
||||
return OB_RDP_LEVEL_0;
|
||||
}
|
||||
else if ((tmp_reg & FLASH_OBR_RDPRT2) == FLASH_OBR_RDPRT2)
|
||||
{
|
||||
return OB_RDP_LEVEL_2;
|
||||
}
|
||||
else
|
||||
{
|
||||
return OB_RDP_LEVEL_1;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the FLASH User Option Byte value.
|
||||
* @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nBOOT1(Bit4),
|
||||
* VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6).
|
||||
* For few devices, following option bytes are available: nBOOT0(Bit3) & BOOT_SEL(Bit7).
|
||||
*/
|
||||
static uint8_t FLASH_OB_GetUser(void)
|
||||
{
|
||||
/* Return the User Option Byte */
|
||||
return (uint8_t)((READ_REG(FLASH->OBR) & FLASH_OBR_USER) >> FLASH_POSITION_IWDGSW_BIT);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Erase the specified FLASH memory page
|
||||
* @param PageAddress FLASH page to erase
|
||||
* The value of this parameter depend on device used within the same series
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FLASH_PageErase(uint32_t PageAddress)
|
||||
{
|
||||
/* Clean the error context */
|
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
|
||||
/* Proceed to erase the page */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_PER);
|
||||
WRITE_REG(FLASH->AR, PageAddress);
|
||||
SET_BIT(FLASH->CR, FLASH_CR_STRT);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
539
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c
Normal file
539
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c
Normal file
@@ -0,0 +1,539 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_gpio.c
|
||||
* @author MCD Application Team
|
||||
* @brief GPIO HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + IO operation functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### GPIO Peripheral features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
|
||||
configured by software in several modes:
|
||||
(++) Input mode
|
||||
(++) Analog mode
|
||||
(++) Output mode
|
||||
(++) Alternate function mode
|
||||
(++) External interrupt/event lines
|
||||
|
||||
(+) During and just after reset, the alternate functions and external interrupt
|
||||
lines are not active and the I/O ports are configured in input floating mode.
|
||||
|
||||
(+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
|
||||
activated or not.
|
||||
|
||||
(+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
|
||||
type and the IO speed can be selected depending on the VDD value.
|
||||
|
||||
(+) The microcontroller IO pins are connected to onboard peripherals/modules through a
|
||||
multiplexer that allows only one peripheral alternate function (AF) connected
|
||||
to an IO pin at a time. In this way, there can be no conflict between peripherals
|
||||
sharing the same IO pin.
|
||||
|
||||
(+) All ports have external interrupt/event capability. To use external interrupt
|
||||
lines, the port must be configured in input mode. All available GPIO pins are
|
||||
connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
|
||||
|
||||
(+) The external interrupt/event controller consists of up to 28 edge detectors
|
||||
(16 lines are connected to GPIO) for generating event/interrupt requests (each
|
||||
input line can be independently configured to select the type (interrupt or event)
|
||||
and the corresponding trigger event (rising or falling or both). Each line can
|
||||
also be masked independently.
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) Enable the GPIO AHB clock using the following function : __HAL_RCC_GPIOx_CLK_ENABLE().
|
||||
|
||||
(#) Configure the GPIO pin(s) using HAL_GPIO_Init().
|
||||
(++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
|
||||
(++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
|
||||
structure.
|
||||
(++) In case of Output or alternate function mode selection: the speed is
|
||||
configured through "Speed" member from GPIO_InitTypeDef structure.
|
||||
(++) In alternate mode is selection, the alternate function connected to the IO
|
||||
is configured through "Alternate" member from GPIO_InitTypeDef structure.
|
||||
(++) Analog mode is required when a pin is to be used as ADC channel
|
||||
or DAC output.
|
||||
(++) In case of external interrupt/event selection the "Mode" member from
|
||||
GPIO_InitTypeDef structure select the type (interrupt or event) and
|
||||
the corresponding trigger event (rising or falling or both).
|
||||
|
||||
(#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
|
||||
mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
|
||||
HAL_NVIC_EnableIRQ().
|
||||
|
||||
(#) HAL_GPIO_DeInit allows to set register values to their reset value. It's also
|
||||
recommended to use it to unconfigure pin which was used as an external interrupt
|
||||
or in event mode. That's the only way to reset corresponding bit in EXTI & SYSCFG
|
||||
registers.
|
||||
|
||||
(#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
|
||||
|
||||
(#) To set/reset the level of a pin configured in output mode use
|
||||
HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
|
||||
|
||||
(#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
|
||||
|
||||
(#) During and just after reset, the alternate functions are not
|
||||
active and the GPIO pins are configured in input floating mode (except JTAG
|
||||
pins).
|
||||
|
||||
(#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
|
||||
(PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
|
||||
priority over the GPIO function.
|
||||
|
||||
(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
|
||||
general purpose PF0 and PF1, respectively, when the HSE oscillator is off.
|
||||
The HSE has priority over the GPIO function.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO GPIO
|
||||
* @brief GPIO HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** MISRA C:2012 deviation rule has been granted for following rules:
|
||||
* Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..]
|
||||
* which may be out of array bounds [..,UNKNOWN] in following APIs:
|
||||
* HAL_GPIO_Init
|
||||
* HAL_GPIO_DeInit
|
||||
*/
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/** @addtogroup GPIO_Private_Constants GPIO Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_NUMBER 16U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
|
||||
* @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family
|
||||
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
|
||||
* the configuration information for the specified GPIO peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
||||
{
|
||||
uint32_t position = 0x00u;
|
||||
uint32_t iocurrent;
|
||||
uint32_t temp;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
||||
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
||||
|
||||
/* Configure the port pins */
|
||||
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
||||
{
|
||||
/* Get current io position */
|
||||
iocurrent = (GPIO_Init->Pin) & (1uL << position);
|
||||
|
||||
if (iocurrent != 0x00u)
|
||||
{
|
||||
/*--------------------- GPIO Mode Configuration ------------------------*/
|
||||
/* In case of Output or Alternate function mode selection */
|
||||
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
|
||||
((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
|
||||
{
|
||||
/* Check the Speed parameter */
|
||||
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
||||
/* Configure the IO Speed */
|
||||
temp = GPIOx->OSPEEDR;
|
||||
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u));
|
||||
temp |= (GPIO_Init->Speed << (position * 2u));
|
||||
GPIOx->OSPEEDR = temp;
|
||||
|
||||
/* Configure the IO Output Type */
|
||||
temp = GPIOx->OTYPER;
|
||||
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
|
||||
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
|
||||
GPIOx->OTYPER = temp;
|
||||
}
|
||||
|
||||
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
|
||||
{
|
||||
/* Check the Pull parameter */
|
||||
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
||||
|
||||
/* Activate the Pull-up or Pull down resistor for the current IO */
|
||||
temp = GPIOx->PUPDR;
|
||||
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u));
|
||||
temp |= ((GPIO_Init->Pull) << (position * 2u));
|
||||
GPIOx->PUPDR = temp;
|
||||
}
|
||||
|
||||
/* In case of Alternate function mode selection */
|
||||
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
||||
{
|
||||
/* Check the Alternate function parameters */
|
||||
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
|
||||
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
||||
|
||||
/* Configure Alternate function mapped with the current IO */
|
||||
temp = GPIOx->AFR[position >> 3u];
|
||||
temp &= ~(0xFu << ((position & 0x07u) * 4u));
|
||||
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
|
||||
GPIOx->AFR[position >> 3u] = temp;
|
||||
}
|
||||
|
||||
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
||||
temp = GPIOx->MODER;
|
||||
temp &= ~(GPIO_MODER_MODER0 << (position * 2u));
|
||||
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
|
||||
GPIOx->MODER = temp;
|
||||
|
||||
/*--------------------- EXTI Mode Configuration ------------------------*/
|
||||
/* Configure the External Interrupt or event for the current IO */
|
||||
if((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
|
||||
{
|
||||
/* Enable SYSCFG Clock */
|
||||
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||||
|
||||
temp = SYSCFG->EXTICR[position >> 2u];
|
||||
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
|
||||
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
|
||||
SYSCFG->EXTICR[position >> 2u] = temp;
|
||||
|
||||
/* Clear Rising Falling edge configuration */
|
||||
temp = EXTI->RTSR;
|
||||
temp &= ~(iocurrent);
|
||||
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->RTSR = temp;
|
||||
|
||||
temp = EXTI->FTSR;
|
||||
temp &= ~(iocurrent);
|
||||
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->FTSR = temp;
|
||||
|
||||
/* Clear EXTI line configuration */
|
||||
temp = EXTI->EMR;
|
||||
temp &= ~(iocurrent);
|
||||
if((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->EMR = temp;
|
||||
|
||||
temp = EXTI->IMR;
|
||||
temp &= ~(iocurrent);
|
||||
if((GPIO_Init->Mode & EXTI_IT) != 0x00u)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->IMR = temp;
|
||||
}
|
||||
}
|
||||
|
||||
position++;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief De-initialize the GPIOx peripheral registers to their default reset values.
|
||||
* @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family
|
||||
* @param GPIO_Pin specifies the port bit to be written.
|
||||
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
|
||||
{
|
||||
uint32_t position = 0x00u;
|
||||
uint32_t iocurrent;
|
||||
uint32_t tmp;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
/* Configure the port pins */
|
||||
while ((GPIO_Pin >> position) != 0x00u)
|
||||
{
|
||||
/* Get current io position */
|
||||
iocurrent = (GPIO_Pin) & (1uL << position);
|
||||
|
||||
if (iocurrent != 0x00u)
|
||||
{
|
||||
/*------------------------- EXTI Mode Configuration --------------------*/
|
||||
/* Clear the External Interrupt or Event for the current IO */
|
||||
|
||||
tmp = SYSCFG->EXTICR[position >> 2u];
|
||||
tmp &= (0x0FuL << (4u * (position & 0x03u)));
|
||||
if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))))
|
||||
{
|
||||
/* Clear EXTI line configuration */
|
||||
EXTI->IMR &= ~((uint32_t)iocurrent);
|
||||
EXTI->EMR &= ~((uint32_t)iocurrent);
|
||||
|
||||
/* Clear Rising Falling edge configuration */
|
||||
EXTI->FTSR &= ~((uint32_t)iocurrent);
|
||||
EXTI->RTSR &= ~((uint32_t)iocurrent);
|
||||
|
||||
/* Configure the External Interrupt or event for the current IO */
|
||||
tmp = 0x0FuL << (4u * (position & 0x03u));
|
||||
SYSCFG->EXTICR[position >> 2u] &= ~tmp;
|
||||
}
|
||||
|
||||
/*------------------------- GPIO Mode Configuration --------------------*/
|
||||
/* Configure IO Direction in Input Floating Mode */
|
||||
GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2u));
|
||||
|
||||
/* Configure the default Alternate Function in current IO */
|
||||
GPIOx->AFR[position >> 3u] &= ~(0xFu << ((uint32_t)(position & 0x07u) * 4u)) ;
|
||||
|
||||
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
|
||||
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u));
|
||||
|
||||
/* Configure the default value IO Output Type */
|
||||
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
|
||||
|
||||
/* Configure the default value for IO Speed */
|
||||
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u));
|
||||
|
||||
}
|
||||
|
||||
position++;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
|
||||
* @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Read the specified input port pin.
|
||||
* @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family
|
||||
* @param GPIO_Pin specifies the port bit to read.
|
||||
* This parameter can be GPIO_PIN_x where x can be (0..15).
|
||||
* @retval The input port pin value.
|
||||
*/
|
||||
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
GPIO_PinState bitstatus;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
|
||||
{
|
||||
bitstatus = GPIO_PIN_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = GPIO_PIN_RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set or clear the selected data port bit.
|
||||
* @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify
|
||||
* accesses. In this way, there is no risk of an IRQ occurring between
|
||||
* the read and the modify access.
|
||||
*
|
||||
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32F0 family
|
||||
* @param GPIO_Pin specifies the port bit to be written.
|
||||
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
|
||||
* @param PinState specifies the value to be written to the selected bit.
|
||||
* This parameter can be one of the GPIO_PinState enum values:
|
||||
* @arg GPIO_PIN_RESET: to clear the port pin
|
||||
* @arg GPIO_PIN_SET: to set the port pin
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
||||
|
||||
if (PinState != GPIO_PIN_RESET)
|
||||
{
|
||||
GPIOx->BSRR = (uint32_t)GPIO_Pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Toggle the specified GPIO pin.
|
||||
* @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family
|
||||
* @param GPIO_Pin specifies the pin to be toggled.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint32_t odr;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
/* get current Output Data Register value */
|
||||
odr = GPIOx->ODR;
|
||||
|
||||
/* Set selected pins that were at low level, and reset ones that were high */
|
||||
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Locks GPIO Pins configuration registers.
|
||||
* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
|
||||
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
|
||||
* @note The configuration of the locked GPIO pins can no longer be modified
|
||||
* until the next reset.
|
||||
* @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family
|
||||
* @param GPIO_Pin specifies the port bits to be locked.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
__IO uint32_t tmp = GPIO_LCKR_LCKK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
/* Apply lock key write sequence */
|
||||
SET_BIT(tmp, GPIO_Pin);
|
||||
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
|
||||
GPIOx->LCKR = GPIO_Pin;
|
||||
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Read LCKK register. This read is mandatory to complete key lock sequence */
|
||||
tmp = GPIOx->LCKR;
|
||||
|
||||
/* read again in order to confirm lock is active */
|
||||
if((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u)
|
||||
{
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handle EXTI interrupt request.
|
||||
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
|
||||
{
|
||||
/* EXTI line interrupt detected */
|
||||
if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
|
||||
{
|
||||
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
|
||||
HAL_GPIO_EXTI_Callback(GPIO_Pin);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EXTI line detection callback.
|
||||
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(GPIO_Pin);
|
||||
|
||||
/* NOTE: This function should not be modified, when the callback is needed,
|
||||
the HAL_GPIO_EXTI_Callback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
7548
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c
Normal file
7548
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c
Normal file
File diff suppressed because it is too large
Load Diff
362
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c
Normal file
362
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c
Normal file
@@ -0,0 +1,362 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_i2c_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief I2C Extended HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of I2C Extended peripheral:
|
||||
* + Filter Mode Functions
|
||||
* + WakeUp Mode Functions
|
||||
* + FastModePlus Functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### I2C peripheral Extended features #####
|
||||
==============================================================================
|
||||
|
||||
[..] Comparing to other previous devices, the I2C interface for STM32F0xx
|
||||
devices contains the following additional features
|
||||
|
||||
(+) Possibility to disable or enable Analog Noise Filter
|
||||
(+) Use of a configured Digital Noise Filter
|
||||
(+) Disable or enable wakeup from Stop mode(s)
|
||||
(+) Disable or enable Fast Mode Plus
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..] This driver provides functions to configure Noise Filter and Wake Up Feature
|
||||
(#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
|
||||
(#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
|
||||
(#) Configure the enable or disable of I2C Wake Up Mode using the functions :
|
||||
(++) HAL_I2CEx_EnableWakeUp()
|
||||
(++) HAL_I2CEx_DisableWakeUp()
|
||||
(#) Configure the enable or disable of fast mode plus driving capability using the functions :
|
||||
(++) HAL_I2CEx_EnableFastModePlus()
|
||||
(++) HAL_I2CEx_DisableFastModePlus()
|
||||
@endverbatim
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx I2CEx
|
||||
* @brief I2C Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
|
||||
* @brief Filter Mode Functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Filter Mode Functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure Noise Filters
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configure I2C Analog noise filter.
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2Cx peripheral.
|
||||
* @param AnalogFilter New state of the Analog filter.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
||||
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_READY)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_BUSY;
|
||||
|
||||
/* Disable the selected I2C peripheral */
|
||||
__HAL_I2C_DISABLE(hi2c);
|
||||
|
||||
/* Reset I2Cx ANOFF bit */
|
||||
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
|
||||
|
||||
/* Set analog filter bit*/
|
||||
hi2c->Instance->CR1 |= AnalogFilter;
|
||||
|
||||
__HAL_I2C_ENABLE(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure I2C Digital noise filter.
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2Cx peripheral.
|
||||
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
|
||||
{
|
||||
uint32_t tmpreg;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
||||
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_READY)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_BUSY;
|
||||
|
||||
/* Disable the selected I2C peripheral */
|
||||
__HAL_I2C_DISABLE(hi2c);
|
||||
|
||||
/* Get the old register value */
|
||||
tmpreg = hi2c->Instance->CR1;
|
||||
|
||||
/* Reset I2Cx DNF bits [11:8] */
|
||||
tmpreg &= ~(I2C_CR1_DNF);
|
||||
|
||||
/* Set I2Cx DNF coefficient */
|
||||
tmpreg |= DigitalFilter << 8U;
|
||||
|
||||
/* Store the new register value */
|
||||
hi2c->Instance->CR1 = tmpreg;
|
||||
|
||||
__HAL_I2C_ENABLE(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#if defined(I2C_CR1_WUPEN)
|
||||
|
||||
/** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
|
||||
* @brief WakeUp Mode Functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### WakeUp Mode Functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure Wake Up Feature
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable I2C wakeup from Stop mode(s).
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2Cx peripheral.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_READY)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_BUSY;
|
||||
|
||||
/* Disable the selected I2C peripheral */
|
||||
__HAL_I2C_DISABLE(hi2c);
|
||||
|
||||
/* Enable wakeup from stop mode */
|
||||
hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
|
||||
|
||||
__HAL_I2C_ENABLE(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable I2C wakeup from Stop mode(s).
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2Cx peripheral.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_READY)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_BUSY;
|
||||
|
||||
/* Disable the selected I2C peripheral */
|
||||
__HAL_I2C_DISABLE(hi2c);
|
||||
|
||||
/* Enable wakeup from stop mode */
|
||||
hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
|
||||
|
||||
__HAL_I2C_ENABLE(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* I2C_CR1_WUPEN */
|
||||
|
||||
/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
|
||||
* @brief Fast Mode Plus Functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Fast Mode Plus Functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure Fast Mode Plus
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the I2C fast mode plus driving capability.
|
||||
* @param ConfigFastModePlus Selects the pin.
|
||||
* This parameter can be one of the @ref I2CEx_FastModePlus values
|
||||
* @note For I2C1, fast mode plus driving capability can be enabled on all selected
|
||||
* I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
|
||||
* on each one of the following pins PB6, PB7, PB8 and PB9.
|
||||
* @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
|
||||
* can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
|
||||
* @note For all I2C2 pins fast mode plus driving capability can be enabled
|
||||
* only by using I2C_FASTMODEPLUS_I2C2 parameter.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
|
||||
|
||||
/* Enable SYSCFG clock */
|
||||
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||||
|
||||
/* Enable fast mode plus driving capability for selected pin */
|
||||
SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the I2C fast mode plus driving capability.
|
||||
* @param ConfigFastModePlus Selects the pin.
|
||||
* This parameter can be one of the @ref I2CEx_FastModePlus values
|
||||
* @note For I2C1, fast mode plus driving capability can be disabled on all selected
|
||||
* I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
|
||||
* on each one of the following pins PB6, PB7, PB8 and PB9.
|
||||
* @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
|
||||
* can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
|
||||
* @note For all I2C2 pins fast mode plus driving capability can be disabled
|
||||
* only by using I2C_FASTMODEPLUS_I2C2 parameter.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
|
||||
|
||||
/* Enable SYSCFG clock */
|
||||
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||||
|
||||
/* Disable fast mode plus driving capability for selected pin */
|
||||
CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
1854
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2s.c
Normal file
1854
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2s.c
Normal file
File diff suppressed because it is too large
Load Diff
3011
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_irda.c
Normal file
3011
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_irda.c
Normal file
File diff suppressed because it is too large
Load Diff
282
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_iwdg.c
Normal file
282
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_iwdg.c
Normal file
@@ -0,0 +1,282 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_iwdg.c
|
||||
* @author MCD Application Team
|
||||
* @brief IWDG HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Independent Watchdog (IWDG) peripheral:
|
||||
* + Initialization and Start functions
|
||||
* + IO operation functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### IWDG Generic features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(+) The IWDG can be started by either software or hardware (configurable
|
||||
through option byte).
|
||||
|
||||
(+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays
|
||||
active even if the main clock fails.
|
||||
|
||||
(+) Once the IWDG is started, the LSI is forced ON and both cannot be
|
||||
disabled. The counter starts counting down from the reset value (0xFFF).
|
||||
When it reaches the end of count value (0x000) a reset signal is
|
||||
generated (IWDG reset).
|
||||
|
||||
(+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
|
||||
the IWDG_RLR value is reloaded into the counter and the watchdog reset
|
||||
is prevented.
|
||||
|
||||
(+) The IWDG is implemented in the VDD voltage domain that is still functional
|
||||
in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY).
|
||||
IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
|
||||
reset occurs.
|
||||
|
||||
(+) Debug mode: When the microcontroller enters debug mode (core halted),
|
||||
the IWDG counter either continues to work normally or stops, depending
|
||||
on DBG_IWDG_STOP configuration bit in DBG module, accessible through
|
||||
__HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros.
|
||||
|
||||
[..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
|
||||
The IWDG timeout may vary due to LSI clock frequency dispersion.
|
||||
STM32F0xx devices provide the capability to measure the LSI clock
|
||||
frequency (LSI clock is internally connected to TIM16 CH1 input capture).
|
||||
The measured value can be used to have an IWDG timeout with an
|
||||
acceptable accuracy.
|
||||
|
||||
[..] Default timeout value (necessary for IWDG_SR status register update):
|
||||
Constant LSI_VALUE is defined based on the nominal LSI clock frequency.
|
||||
This frequency being subject to variations as mentioned above, the
|
||||
default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT
|
||||
below) may become too short or too long.
|
||||
In such cases, this default timeout value can be tuned by redefining
|
||||
the constant LSI_VALUE at user-application level (based, for instance,
|
||||
on the measured LSI clock frequency as explained above).
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) Use IWDG using HAL_IWDG_Init() function to :
|
||||
(++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
|
||||
clock is forced ON and IWDG counter starts counting down.
|
||||
(++) Enable write access to configuration registers:
|
||||
IWDG_PR, IWDG_RLR and IWDG_WINR.
|
||||
(++) Configure the IWDG prescaler and counter reload value. This reload
|
||||
value will be loaded in the IWDG counter each time the watchdog is
|
||||
reloaded, then the IWDG will start counting down from this value.
|
||||
(++) Depending on window parameter:
|
||||
(+++) If Window Init parameter is same as Window register value,
|
||||
nothing more is done but reload counter value in order to exit
|
||||
function with exact time base.
|
||||
(+++) Else modify Window register. This will automatically reload
|
||||
watchdog counter.
|
||||
(++) Wait for status flags to be reset.
|
||||
|
||||
(#) Then the application program must refresh the IWDG counter at regular
|
||||
intervals during normal operation to prevent an MCU reset, using
|
||||
HAL_IWDG_Refresh() function.
|
||||
|
||||
*** IWDG HAL driver macros list ***
|
||||
====================================
|
||||
[..]
|
||||
Below the list of most used macros in IWDG HAL driver:
|
||||
(+) __HAL_IWDG_START: Enable the IWDG peripheral
|
||||
(+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
|
||||
the reload register
|
||||
|
||||
@endverbatim
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||
/** @addtogroup IWDG
|
||||
* @brief IWDG HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Private_Defines IWDG Private Defines
|
||||
* @{
|
||||
*/
|
||||
/* Status register needs up to 5 LSI clock periods divided by the clock
|
||||
prescaler to be updated. The number of LSI clock periods is upper-rounded to
|
||||
6 for the timeout value calculation.
|
||||
The timeout value is calculated using the highest prescaler (256) and
|
||||
the LSI_VALUE constant. The value of this constant can be changed by the user
|
||||
to take into account possible LSI clock period variations.
|
||||
The timeout value is multiplied by 1000 to be converted in milliseconds.
|
||||
LSI startup time is also considered here by adding LSI_STARTUP_TIME
|
||||
converted in milliseconds. */
|
||||
#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL))
|
||||
#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup IWDG_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IWDG_Exported_Functions_Group1
|
||||
* @brief Initialization and Start functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Start functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Initialize the IWDG according to the specified parameters in the
|
||||
IWDG_InitTypeDef of associated handle.
|
||||
(+) Manage Window option.
|
||||
(+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
|
||||
is reloaded in order to exit function with correct time base.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initialize the IWDG according to the specified parameters in the
|
||||
* IWDG_InitTypeDef and start watchdog. Before exiting function,
|
||||
* watchdog is refreshed in order to have correct time base.
|
||||
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified IWDG module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
|
||||
/* Check the IWDG handle allocation */
|
||||
if (hiwdg == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
|
||||
assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
|
||||
assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
|
||||
assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
|
||||
|
||||
/* Enable IWDG. LSI is turned on automatically */
|
||||
__HAL_IWDG_START(hiwdg);
|
||||
|
||||
/* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing
|
||||
0x5555 in KR */
|
||||
IWDG_ENABLE_WRITE_ACCESS(hiwdg);
|
||||
|
||||
/* Write to IWDG registers the Prescaler & Reload values to work with */
|
||||
hiwdg->Instance->PR = hiwdg->Init.Prescaler;
|
||||
hiwdg->Instance->RLR = hiwdg->Init.Reload;
|
||||
|
||||
/* Check pending flag, if previous update not done, return timeout */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait for register to be updated */
|
||||
while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
|
||||
{
|
||||
if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
|
||||
{
|
||||
if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* If window parameter is different than current value, modify window
|
||||
register */
|
||||
if (hiwdg->Instance->WINR != hiwdg->Init.Window)
|
||||
{
|
||||
/* Write to IWDG WINR the IWDG_Window value to compare with. In any case,
|
||||
even if window feature is disabled, Watchdog will be reloaded by writing
|
||||
windows register */
|
||||
hiwdg->Instance->WINR = hiwdg->Init.Window;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Reload IWDG counter with value defined in the reload register */
|
||||
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
|
||||
}
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup IWDG_Exported_Functions_Group2
|
||||
* @brief IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Refresh the IWDG.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Refresh the IWDG.
|
||||
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified IWDG module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
|
||||
{
|
||||
/* Reload IWDG counter with value defined in the reload register */
|
||||
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_IWDG_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
101
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_msp_template.c
Normal file
101
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_msp_template.c
Normal file
@@ -0,0 +1,101 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_msp_template.c
|
||||
* @author MCD Application Team
|
||||
* @brief HAL MSP module.
|
||||
* This file template is located in the HAL folder and should be copied
|
||||
* to the user folder.
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### How to use this driver #####
|
||||
===============================================================================
|
||||
[..]
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_MSP HAL MSP module driver
|
||||
* @brief HAL MSP module.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup HAL_MSP_Private_Functions HAL MSP Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the Global MSP.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_MspInit(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the Global MSP.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_MspDeInit(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the PPP MSP.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PPP_MspInit(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the PPP MSP.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PPP_MspDeInit(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
2243
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.c
Normal file
2243
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.c
Normal file
File diff suppressed because it is too large
Load Diff
333
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.c
Normal file
333
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.c
Normal file
@@ -0,0 +1,333 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_pcd_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief PCD Extended HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the USB Peripheral Controller:
|
||||
* + Extended features functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PCDEx PCDEx
|
||||
* @brief PCD Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_PCD_MODULE_ENABLED
|
||||
|
||||
#if defined (USB)
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
|
||||
* @brief PCDEx control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extended features functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Update FIFO configuration
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configure PMA for EP
|
||||
* @param hpcd Device instance
|
||||
* @param ep_addr endpoint address
|
||||
* @param ep_kind endpoint Kind
|
||||
* USB_SNG_BUF: Single Buffer used
|
||||
* USB_DBL_BUF: Double Buffer used
|
||||
* @param pmaadress: EP address in The PMA: In case of single buffer endpoint
|
||||
* this parameter is 16-bit value providing the address
|
||||
* in PMA allocated to endpoint.
|
||||
* In case of double buffer endpoint this parameter
|
||||
* is a 32-bit value providing the endpoint buffer 0 address
|
||||
* in the LSB part of 32-bit value and endpoint buffer 1 address
|
||||
* in the MSB part of 32-bit value.
|
||||
* @retval HAL status
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
|
||||
uint16_t ep_kind, uint32_t pmaadress)
|
||||
{
|
||||
PCD_EPTypeDef *ep;
|
||||
|
||||
/* initialize ep structure*/
|
||||
if ((0x80U & ep_addr) == 0x80U)
|
||||
{
|
||||
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
||||
}
|
||||
else
|
||||
{
|
||||
ep = &hpcd->OUT_ep[ep_addr];
|
||||
}
|
||||
|
||||
/* Here we check if the endpoint is single or double Buffer*/
|
||||
if (ep_kind == PCD_SNG_BUF)
|
||||
{
|
||||
/* Single Buffer */
|
||||
ep->doublebuffer = 0U;
|
||||
/* Configure the PMA */
|
||||
ep->pmaadress = (uint16_t)pmaadress;
|
||||
}
|
||||
#if (USE_USB_DOUBLE_BUFFER == 1U)
|
||||
else /* USB_DBL_BUF */
|
||||
{
|
||||
/* Double Buffer Endpoint */
|
||||
ep->doublebuffer = 1U;
|
||||
/* Configure the PMA */
|
||||
ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU);
|
||||
ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16);
|
||||
}
|
||||
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Activate BatteryCharging feature.
|
||||
* @param hpcd PCD handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
|
||||
{
|
||||
USB_TypeDef *USBx = hpcd->Instance;
|
||||
hpcd->battery_charging_active = 1U;
|
||||
|
||||
/* Enable BCD feature */
|
||||
USBx->BCDR |= USB_BCDR_BCDEN;
|
||||
|
||||
/* Enable DCD : Data Contact Detect */
|
||||
USBx->BCDR &= ~(USB_BCDR_PDEN);
|
||||
USBx->BCDR &= ~(USB_BCDR_SDEN);
|
||||
USBx->BCDR |= USB_BCDR_DCDEN;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deactivate BatteryCharging feature.
|
||||
* @param hpcd PCD handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
|
||||
{
|
||||
USB_TypeDef *USBx = hpcd->Instance;
|
||||
hpcd->battery_charging_active = 0U;
|
||||
|
||||
/* Disable BCD feature */
|
||||
USBx->BCDR &= ~(USB_BCDR_BCDEN);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handle BatteryCharging Process.
|
||||
* @param hpcd PCD handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
|
||||
{
|
||||
USB_TypeDef *USBx = hpcd->Instance;
|
||||
uint32_t tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait for Min DCD Timeout */
|
||||
HAL_Delay(300U);
|
||||
|
||||
/* Data Pin Contact ? Check Detect flag */
|
||||
if ((USBx->BCDR & USB_BCDR_DCDET) == USB_BCDR_DCDET)
|
||||
{
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION);
|
||||
#else
|
||||
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
}
|
||||
/* Primary detection: checks if connected to Standard Downstream Port
|
||||
(without charging capability) */
|
||||
USBx->BCDR &= ~(USB_BCDR_DCDEN);
|
||||
HAL_Delay(50U);
|
||||
USBx->BCDR |= (USB_BCDR_PDEN);
|
||||
HAL_Delay(50U);
|
||||
|
||||
/* If Charger detect ? */
|
||||
if ((USBx->BCDR & USB_BCDR_PDET) == USB_BCDR_PDET)
|
||||
{
|
||||
/* Start secondary detection to check connection to Charging Downstream
|
||||
Port or Dedicated Charging Port */
|
||||
USBx->BCDR &= ~(USB_BCDR_PDEN);
|
||||
HAL_Delay(50U);
|
||||
USBx->BCDR |= (USB_BCDR_SDEN);
|
||||
HAL_Delay(50U);
|
||||
|
||||
/* If CDP ? */
|
||||
if ((USBx->BCDR & USB_BCDR_SDET) == USB_BCDR_SDET)
|
||||
{
|
||||
/* Dedicated Downstream Port DCP */
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
|
||||
#else
|
||||
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Charging Downstream Port CDP */
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
|
||||
#else
|
||||
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
}
|
||||
}
|
||||
else /* NO */
|
||||
{
|
||||
/* Standard Downstream Port */
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
|
||||
#else
|
||||
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
}
|
||||
|
||||
/* Battery Charging capability discovery finished Start Enumeration */
|
||||
(void)HAL_PCDEx_DeActivateBCD(hpcd);
|
||||
|
||||
/* Check for the Timeout, else start USB Device */
|
||||
if ((HAL_GetTick() - tickstart) > 1000U)
|
||||
{
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);
|
||||
#else
|
||||
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
}
|
||||
else
|
||||
{
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
|
||||
#else
|
||||
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Activate LPM feature.
|
||||
* @param hpcd PCD handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
|
||||
{
|
||||
|
||||
USB_TypeDef *USBx = hpcd->Instance;
|
||||
hpcd->lpm_active = 1U;
|
||||
hpcd->LPM_State = LPM_L0;
|
||||
|
||||
USBx->LPMCSR |= USB_LPMCSR_LMPEN;
|
||||
USBx->LPMCSR |= USB_LPMCSR_LPMACK;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deactivate LPM feature.
|
||||
* @param hpcd PCD handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
|
||||
{
|
||||
USB_TypeDef *USBx = hpcd->Instance;
|
||||
|
||||
hpcd->lpm_active = 0U;
|
||||
|
||||
USBx->LPMCSR &= ~(USB_LPMCSR_LMPEN);
|
||||
USBx->LPMCSR &= ~(USB_LPMCSR_LPMACK);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Send LPM message to user layer callback.
|
||||
* @param hpcd PCD handle
|
||||
* @param msg LPM message
|
||||
* @retval HAL status
|
||||
*/
|
||||
__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hpcd);
|
||||
UNUSED(msg);
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_PCDEx_LPM_Callback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Send BatteryCharging message to user layer callback.
|
||||
* @param hpcd PCD handle
|
||||
* @param msg LPM message
|
||||
* @retval HAL status
|
||||
*/
|
||||
__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hpcd);
|
||||
UNUSED(msg);
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_PCDEx_BCD_Callback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* defined (USB) */
|
||||
#endif /* HAL_PCD_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
450
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c
Normal file
450
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c
Normal file
@@ -0,0 +1,450 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_pwr.c
|
||||
* @author MCD Application Team
|
||||
* @brief PWR HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Power Controller (PWR) peripheral:
|
||||
* + Initialization/de-initialization function
|
||||
* + Peripheral Control function
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR PWR
|
||||
* @brief PWR HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWR_Exported_Functions PWR Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and de-initialization functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
After reset, the backup domain (RTC registers, RTC backup data
|
||||
registers) is protected against possible unwanted
|
||||
write accesses.
|
||||
To enable access to the RTC Domain and RTC registers, proceed as follows:
|
||||
(+) Enable the Power Controller (PWR) APB1 interface clock using the
|
||||
__HAL_RCC_PWR_CLK_ENABLE() macro.
|
||||
(+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the PWR peripheral registers to their default reset values.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DeInit(void)
|
||||
{
|
||||
__HAL_RCC_PWR_FORCE_RESET();
|
||||
__HAL_RCC_PWR_RELEASE_RESET();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables access to the backup domain (RTC registers, RTC
|
||||
* backup data registers when present).
|
||||
* @note If the HSE divided by 32 is used as the RTC clock, the
|
||||
* Backup Domain Access should be kept enabled.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableBkUpAccess(void)
|
||||
{
|
||||
PWR->CR |= (uint32_t)PWR_CR_DBP;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables access to the backup domain (RTC registers, RTC
|
||||
* backup data registers when present).
|
||||
* @note If the HSE divided by 32 is used as the RTC clock, the
|
||||
* Backup Domain Access should be kept enabled.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableBkUpAccess(void)
|
||||
{
|
||||
PWR->CR &= ~((uint32_t)PWR_CR_DBP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief Low Power modes configuration functions
|
||||
*
|
||||
@verbatim
|
||||
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
|
||||
*** WakeUp pin configuration ***
|
||||
================================
|
||||
[..]
|
||||
(+) WakeUp pin is used to wakeup the system from Standby mode. This pin is
|
||||
forced in input pull down configuration and is active on rising edges.
|
||||
(+) There are two WakeUp pins, and up to eight Wakeup pins on STM32F07x & STM32F09x devices.
|
||||
(++)WakeUp Pin 1 on PA.00.
|
||||
(++)WakeUp Pin 2 on PC.13.
|
||||
(++)WakeUp Pin 3 on PE.06.(STM32F07x/STM32F09x)
|
||||
(++)WakeUp Pin 4 on PA.02.(STM32F07x/STM32F09x)
|
||||
(++)WakeUp Pin 5 on PC.05.(STM32F07x/STM32F09x)
|
||||
(++)WakeUp Pin 6 on PB.05.(STM32F07x/STM32F09x)
|
||||
(++)WakeUp Pin 7 on PB.15.(STM32F07x/STM32F09x)
|
||||
(++)WakeUp Pin 8 on PF.02.(STM32F07x/STM32F09x)
|
||||
|
||||
*** Low Power modes configuration ***
|
||||
=====================================
|
||||
[..]
|
||||
The devices feature 3 low-power modes:
|
||||
(+) Sleep mode: Cortex-M0 core stopped, peripherals kept running.
|
||||
(+) Stop mode: all clocks are stopped, regulator running, regulator
|
||||
in low power mode
|
||||
(+) Standby mode: 1.2V domain powered off (mode not available on STM32F0x8 devices).
|
||||
|
||||
*** Sleep mode ***
|
||||
==================
|
||||
[..]
|
||||
(+) Entry:
|
||||
The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
|
||||
functions with
|
||||
(++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
|
||||
(++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
|
||||
|
||||
(+) Exit:
|
||||
(++) Any peripheral interrupt acknowledged by the nested vectored interrupt
|
||||
controller (NVIC) can wake up the device from Sleep mode.
|
||||
|
||||
*** Stop mode ***
|
||||
=================
|
||||
[..]
|
||||
In Stop mode, all clocks in the 1.8V domain are stopped, the PLL, the HSI,
|
||||
and the HSE RC oscillators are disabled. Internal SRAM and register contents
|
||||
are preserved.
|
||||
The voltage regulator can be configured either in normal or low-power mode.
|
||||
To minimize the consumption.
|
||||
|
||||
(+) Entry:
|
||||
The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFI )
|
||||
function with:
|
||||
(++) Main regulator ON.
|
||||
(++) Low Power regulator ON.
|
||||
(++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction
|
||||
(++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction
|
||||
(+) Exit:
|
||||
(++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
|
||||
(++) Some specific communication peripherals (CEC, USART, I2C) interrupts,
|
||||
when programmed in wakeup mode (the peripheral must be
|
||||
programmed in wakeup mode and the corresponding interrupt vector
|
||||
must be enabled in the NVIC)
|
||||
|
||||
*** Standby mode ***
|
||||
====================
|
||||
[..]
|
||||
The Standby mode allows to achieve the lowest power consumption. It is based
|
||||
on the Cortex-M0 deep sleep mode, with the voltage regulator disabled.
|
||||
The 1.8V domain is consequently powered off. The PLL, the HSI oscillator and
|
||||
the HSE oscillator are also switched off. SRAM and register contents are lost
|
||||
except for the RTC registers, RTC backup registers and Standby circuitry.
|
||||
The voltage regulator is OFF.
|
||||
|
||||
(+) Entry:
|
||||
(++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
|
||||
(+) Exit:
|
||||
(++) WKUP pin rising edge, RTC alarm (Alarm A), RTC wakeup,
|
||||
tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
|
||||
|
||||
*** Auto-wakeup (AWU) from low-power mode ***
|
||||
=============================================
|
||||
[..]
|
||||
The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
|
||||
Wakeup event, a tamper event, a time-stamp event, or a comparator event,
|
||||
without depending on an external interrupt (Auto-wakeup mode).
|
||||
|
||||
(+) RTC auto-wakeup (AWU) from the Stop and Standby modes
|
||||
|
||||
(++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
|
||||
configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
|
||||
|
||||
(++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
|
||||
is necessary to configure the RTC to detect the tamper or time stamp event using the
|
||||
HAL_RTC_SetTimeStamp_IT() or HAL_RTC_SetTamper_IT() functions.
|
||||
|
||||
(++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
|
||||
configure the RTC to generate the RTC WakeUp event using the HAL_RTC_SetWakeUpTimer_IT() function.
|
||||
|
||||
(+) Comparator auto-wakeup (AWU) from the Stop mode
|
||||
|
||||
(++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to:
|
||||
(+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for comparator 2)
|
||||
to be sensitive to to the selected edges (falling, rising or falling
|
||||
and rising) (Interrupt or Event modes) using the EXTI_Init() function.
|
||||
(+++) Configure the comparator to generate the event.
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables the WakeUp PINx functionality.
|
||||
* @param WakeUpPinx Specifies the Power Wake-Up pin to enable.
|
||||
* This parameter can be value of :
|
||||
* @ref PWREx_WakeUp_Pins
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
|
||||
/* Enable the EWUPx pin */
|
||||
SET_BIT(PWR->CSR, WakeUpPinx);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the WakeUp PINx functionality.
|
||||
* @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
|
||||
* This parameter can be values of :
|
||||
* @ref PWREx_WakeUp_Pins
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
|
||||
/* Disable the EWUPx pin */
|
||||
CLEAR_BIT(PWR->CSR, WakeUpPinx);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters Sleep mode.
|
||||
* @note In Sleep mode, all I/O pins keep the same state as in Run mode.
|
||||
* @param Regulator Specifies the regulator state in SLEEP mode.
|
||||
* On STM32F0 devices, this parameter is a dummy value and it is ignored
|
||||
* as regulator can't be modified in this mode. Parameter is kept for platform
|
||||
* compatibility.
|
||||
* @param SLEEPEntry Specifies if SLEEP mode is entered with WFI or WFE instruction.
|
||||
* When WFI entry is used, tick interrupt have to be disabled if not desired as
|
||||
* the interrupt wake up source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
|
||||
* @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_REGULATOR(Regulator));
|
||||
assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
|
||||
|
||||
/* Clear SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
|
||||
|
||||
/* Select SLEEP mode entry -------------------------------------------------*/
|
||||
if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
|
||||
{
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Request Wait For Event */
|
||||
__SEV();
|
||||
__WFE();
|
||||
__WFE();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters STOP mode.
|
||||
* @note In Stop mode, all I/O pins keep the same state as in Run mode.
|
||||
* @note When exiting Stop mode by issuing an interrupt or a wakeup event,
|
||||
* the HSI RC oscillator is selected as system clock.
|
||||
* @note When the voltage regulator operates in low power mode, an additional
|
||||
* startup delay is incurred when waking up from Stop mode.
|
||||
* By keeping the internal regulator ON during Stop mode, the consumption
|
||||
* is higher although the startup time is reduced.
|
||||
* @param Regulator Specifies the regulator state in STOP mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON
|
||||
* @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON
|
||||
* @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction
|
||||
* @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_REGULATOR(Regulator));
|
||||
assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
|
||||
|
||||
/* Select the regulator state in STOP mode ---------------------------------*/
|
||||
tmpreg = PWR->CR;
|
||||
|
||||
/* Clear PDDS and LPDS bits */
|
||||
tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS);
|
||||
|
||||
/* Set LPDS bit according to Regulator value */
|
||||
tmpreg |= Regulator;
|
||||
|
||||
/* Store the new value */
|
||||
PWR->CR = tmpreg;
|
||||
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||||
|
||||
/* Select STOP mode entry --------------------------------------------------*/
|
||||
if(STOPEntry == PWR_STOPENTRY_WFI)
|
||||
{
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Request Wait For Event */
|
||||
__SEV();
|
||||
__WFE();
|
||||
__WFE();
|
||||
}
|
||||
|
||||
/* Reset SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters STANDBY mode.
|
||||
* @note In Standby mode, all I/O pins are high impedance except for:
|
||||
* - Reset pad (still available)
|
||||
* - RTC alternate function pins if configured for tamper, time-stamp, RTC
|
||||
* Alarm out, or RTC clock calibration out.
|
||||
* - WKUP pins if enabled.
|
||||
* STM32F0x8 devices, the Stop mode is available, but it is
|
||||
* aningless to distinguish between voltage regulator in Low power
|
||||
* mode and voltage regulator in Run mode because the regulator
|
||||
* not used and the core is supplied directly from an external source.
|
||||
* Consequently, the Standby mode is not available on those devices.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnterSTANDBYMode(void)
|
||||
{
|
||||
/* Select STANDBY mode */
|
||||
PWR->CR |= (uint32_t)PWR_CR_PDDS;
|
||||
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||||
|
||||
/* This option is used to ensure that store operations are completed */
|
||||
#if defined ( __CC_ARM)
|
||||
__force_stores();
|
||||
#endif
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
|
||||
* @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
|
||||
* re-enters SLEEP mode when an interruption handling is over.
|
||||
* Setting this bit is useful when the processor is expected to run only on
|
||||
* interruptions handling.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableSleepOnExit(void)
|
||||
{
|
||||
/* Set SLEEPONEXIT bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
|
||||
* @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
|
||||
* re-enters SLEEP mode when an interruption handling is over.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableSleepOnExit(void)
|
||||
{
|
||||
/* Clear SLEEPONEXIT bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enables CORTEX M4 SEVONPEND bit.
|
||||
* @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
|
||||
* WFE to wake up when an interrupt moves from inactive to pended.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableSEVOnPend(void)
|
||||
{
|
||||
/* Set SEVONPEND bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disables CORTEX M4 SEVONPEND bit.
|
||||
* @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
|
||||
* WFE to wake up when an interrupt moves from inactive to pended.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableSEVOnPend(void)
|
||||
{
|
||||
/* Clear SEVONPEND bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
271
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c
Normal file
271
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c
Normal file
@@ -0,0 +1,271 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_pwr_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief Extended PWR HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Power Controller (PWR) peripheral:
|
||||
* + Extended Initialization and de-initialization functions
|
||||
* + Extended Peripheral Control functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx PWREx
|
||||
* @brief PWREx HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @defgroup PWREx_Private_Constants PWREx Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define PVD_MODE_IT (0x00010000U)
|
||||
#define PVD_MODE_EVT (0x00020000U)
|
||||
#define PVD_RISING_EDGE (0x00000001U)
|
||||
#define PVD_FALLING_EDGE (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWREx_Exported_Functions PWREx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended Control Functions
|
||||
* @brief Extended Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
|
||||
===============================================================================
|
||||
##### Peripheral extended control functions #####
|
||||
===============================================================================
|
||||
|
||||
*** PVD configuration ***
|
||||
=========================
|
||||
[..]
|
||||
(+) The PVD is used to monitor the VDD power supply by comparing it to a
|
||||
threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
|
||||
(+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
|
||||
than the PVD threshold. This event is internally connected to the EXTI
|
||||
line16 and can generate an interrupt if enabled. This is done through
|
||||
HAL_PWR_ConfigPVD(), HAL_PWR_EnablePVD() functions.
|
||||
(+) The PVD is stopped in Standby mode.
|
||||
-@- PVD is not available on STM32F030x4/x6/x8
|
||||
|
||||
*** VDDIO2 Monitor Configuration ***
|
||||
====================================
|
||||
[..]
|
||||
(+) VDDIO2 monitor is used to monitor the VDDIO2 power supply by comparing it
|
||||
to VREFInt Voltage
|
||||
(+) This monitor is internally connected to the EXTI line31
|
||||
and can generate an interrupt if enabled. This is done through
|
||||
HAL_PWREx_EnableVddio2Monitor() function.
|
||||
-@- VDDIO2 is available on STM32F07x/09x/04x
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (STM32F031x6) || defined (STM32F051x8) || \
|
||||
defined (STM32F071xB) || defined (STM32F091xC) || \
|
||||
defined (STM32F042x6) || defined (STM32F072xB)
|
||||
/**
|
||||
* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
|
||||
* @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration
|
||||
* information for the PVD.
|
||||
* @note Refer to the electrical characteristics of your device datasheet for
|
||||
* more details about the voltage threshold corresponding to each
|
||||
* detection level.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
|
||||
assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
|
||||
|
||||
/* Set PLS[7:5] bits according to PVDLevel value */
|
||||
MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
|
||||
|
||||
/* Clear any previous config. Keep it clear if no event or IT mode is selected */
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_EVENT();
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_IT();
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
|
||||
|
||||
/* Configure interrupt mode */
|
||||
if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_IT();
|
||||
}
|
||||
|
||||
/* Configure event mode */
|
||||
if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_EVENT();
|
||||
}
|
||||
|
||||
/* Configure the edge */
|
||||
if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
|
||||
}
|
||||
|
||||
if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the Power Voltage Detector(PVD).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnablePVD(void)
|
||||
{
|
||||
PWR->CR |= (uint32_t)PWR_CR_PVDE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the Power Voltage Detector(PVD).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisablePVD(void)
|
||||
{
|
||||
PWR->CR &= ~((uint32_t)PWR_CR_PVDE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles the PWR PVD interrupt request.
|
||||
* @note This API should be called under the PVD_IRQHandler() or PVD_VDDIO2_IRQHandler().
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_PVD_IRQHandler(void)
|
||||
{
|
||||
/* Check PWR exti flag */
|
||||
if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
|
||||
{
|
||||
/* PWR PVD interrupt user callback */
|
||||
HAL_PWR_PVDCallback();
|
||||
|
||||
/* Clear PWR Exti pending bit */
|
||||
__HAL_PWR_PVD_EXTI_CLEAR_FLAG();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief PWR PVD interrupt callback
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_PWR_PVDCallback(void)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_PWR_PVDCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
#endif /* defined (STM32F031x6) || defined (STM32F051x8) || */
|
||||
/* defined (STM32F071xB) || defined (STM32F091xC) || */
|
||||
/* defined (STM32F042x6) || defined (STM32F072xB) */
|
||||
|
||||
#if defined (STM32F042x6) || defined (STM32F048xx) || \
|
||||
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
|
||||
defined (STM32F091xC) || defined (STM32F098xx)
|
||||
/**
|
||||
* @brief Enable VDDIO2 monitor: enable Exti 31 and falling edge detection.
|
||||
* @note If Exti 31 is enable correlty and VDDIO2 voltage goes below Vrefint,
|
||||
an interrupt is generated Irq line 1.
|
||||
NVIS has to be enable by user.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWREx_EnableVddio2Monitor(void)
|
||||
{
|
||||
__HAL_PWR_VDDIO2_EXTI_ENABLE_IT();
|
||||
__HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Vddio2 Monitor.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWREx_DisableVddio2Monitor(void)
|
||||
{
|
||||
__HAL_PWR_VDDIO2_EXTI_DISABLE_IT();
|
||||
__HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE();
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles the PWR Vddio2 monitor interrupt request.
|
||||
* @note This API should be called under the VDDIO2_IRQHandler() PVD_VDDIO2_IRQHandler().
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWREx_Vddio2Monitor_IRQHandler(void)
|
||||
{
|
||||
/* Check PWR exti flag */
|
||||
if(__HAL_PWR_VDDIO2_EXTI_GET_FLAG() != RESET)
|
||||
{
|
||||
/* PWR Vddio2 monitor interrupt user callback */
|
||||
HAL_PWREx_Vddio2MonitorCallback();
|
||||
|
||||
/* Clear PWR Exti pending bit */
|
||||
__HAL_PWR_VDDIO2_EXTI_CLEAR_FLAG();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief PWR Vddio2 Monitor interrupt callback
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_PWREx_Vddio2MonitorCallback(void)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_PWREx_Vddio2MonitorCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
|
||||
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
|
||||
defined (STM32F091xC) || defined (STM32F098xx) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
1365
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c
Normal file
1365
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c
Normal file
File diff suppressed because it is too large
Load Diff
961
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c
Normal file
961
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c
Normal file
@@ -0,0 +1,961 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_rcc_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief Extended RCC HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities RCC extension peripheral:
|
||||
* + Extended Peripheral Control functions
|
||||
* + Extended Clock Recovery System Control functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_RCC_MODULE_ENABLED
|
||||
|
||||
/** @defgroup RCCEx RCCEx
|
||||
* @brief RCC Extension HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#if defined(CRS)
|
||||
/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
|
||||
* @{
|
||||
*/
|
||||
/* Bit position in register */
|
||||
#define CRS_CFGR_FELIM_BITNUMBER 16
|
||||
#define CRS_CR_TRIM_BITNUMBER 8
|
||||
#define CRS_ISR_FECAP_BITNUMBER 16
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* CRS */
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
|
||||
* @brief Extended Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extended Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the RCC Clocks
|
||||
frequencies.
|
||||
[..]
|
||||
(@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
|
||||
select the RTC clock source; in this case the Backup domain will be reset in
|
||||
order to modify the RTC Clock source, as consequence RTC registers (including
|
||||
the backup registers) are set to their reset values.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the RCC extended peripherals clocks according to the specified
|
||||
* parameters in the RCC_PeriphCLKInitTypeDef.
|
||||
* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
|
||||
* contains the configuration information for the Extended Peripherals clocks
|
||||
* (USART, RTC, I2C, CEC and USB).
|
||||
*
|
||||
* @note Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to select
|
||||
* the RTC clock source; in this case the Backup domain will be reset in
|
||||
* order to modify the RTC Clock source, as consequence RTC registers (including
|
||||
* the backup registers) and RCC_BDCR register are set to their reset values.
|
||||
*
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
||||
{
|
||||
uint32_t tickstart = 0U;
|
||||
uint32_t temp_reg = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
|
||||
|
||||
/*---------------------------- RTC configuration -------------------------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
|
||||
{
|
||||
/* check for RTC Parameters used to output RTCCLK */
|
||||
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
|
||||
|
||||
FlagStatus pwrclkchanged = RESET;
|
||||
|
||||
/* As soon as function is called to change RTC clock source, activation of the
|
||||
power domain is done. */
|
||||
/* Requires to enable write access to Backup Domain of necessary */
|
||||
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
|
||||
{
|
||||
__HAL_RCC_PWR_CLK_ENABLE();
|
||||
pwrclkchanged = SET;
|
||||
}
|
||||
|
||||
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
||||
{
|
||||
/* Enable write access to Backup domain */
|
||||
SET_BIT(PWR->CR, PWR_CR_DBP);
|
||||
|
||||
/* Wait for Backup domain Write protection disable */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
||||
{
|
||||
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
|
||||
temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
|
||||
if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
|
||||
{
|
||||
/* Store the content of BDCR register before the reset of Backup Domain */
|
||||
temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
|
||||
/* RTC Clock selection can be changed only if the Backup Domain is reset */
|
||||
__HAL_RCC_BACKUPRESET_FORCE();
|
||||
__HAL_RCC_BACKUPRESET_RELEASE();
|
||||
/* Restore the Content of BDCR register */
|
||||
RCC->BDCR = temp_reg;
|
||||
|
||||
/* Wait for LSERDY if LSE was enabled */
|
||||
if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
|
||||
{
|
||||
/* Get Start Tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait till LSE is ready */
|
||||
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
||||
{
|
||||
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
||||
|
||||
/* Require to disable power clock if necessary */
|
||||
if(pwrclkchanged == SET)
|
||||
{
|
||||
__HAL_RCC_PWR_CLK_DISABLE();
|
||||
}
|
||||
}
|
||||
|
||||
/*------------------------------- USART1 Configuration ------------------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
|
||||
|
||||
/* Configure the USART1 clock source */
|
||||
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
|
||||
}
|
||||
|
||||
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
|
||||
|| defined(STM32F091xC) || defined(STM32F098xx)
|
||||
/*----------------------------- USART2 Configuration --------------------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
|
||||
|
||||
/* Configure the USART2 clock source */
|
||||
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
|
||||
}
|
||||
#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
|
||||
/* STM32F091xC || STM32F098xx */
|
||||
|
||||
#if defined(STM32F091xC) || defined(STM32F098xx)
|
||||
/*----------------------------- USART3 Configuration --------------------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
|
||||
|
||||
/* Configure the USART3 clock source */
|
||||
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
|
||||
}
|
||||
#endif /* STM32F091xC || STM32F098xx */
|
||||
|
||||
/*------------------------------ I2C1 Configuration ------------------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
|
||||
|
||||
/* Configure the I2C1 clock source */
|
||||
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
|
||||
}
|
||||
|
||||
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F070x6)
|
||||
/*------------------------------ USB Configuration ------------------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
|
||||
|
||||
/* Configure the USB clock source */
|
||||
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
|
||||
}
|
||||
#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */
|
||||
|
||||
#if defined(STM32F042x6) || defined(STM32F048xx)\
|
||||
|| defined(STM32F051x8) || defined(STM32F058xx)\
|
||||
|| defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
|
||||
|| defined(STM32F091xC) || defined(STM32F098xx)
|
||||
/*------------------------------ CEC clock Configuration -------------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
|
||||
|
||||
/* Configure the CEC clock source */
|
||||
__HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
|
||||
}
|
||||
#endif /* STM32F042x6 || STM32F048xx || */
|
||||
/* STM32F051x8 || STM32F058xx || */
|
||||
/* STM32F071xB || STM32F072xB || STM32F078xx || */
|
||||
/* STM32F091xC || STM32F098xx */
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the RCC_ClkInitStruct according to the internal
|
||||
* RCC configuration registers.
|
||||
* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
|
||||
* returns the configuration information for the Extended Peripherals clocks
|
||||
* (USART, RTC, I2C, CEC and USB).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
||||
{
|
||||
/* Set all possible values for the extended clock type parameter------------*/
|
||||
/* Common part first */
|
||||
PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC;
|
||||
/* Get the RTC configuration --------------------------------------------*/
|
||||
PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
|
||||
/* Get the USART1 clock configuration --------------------------------------------*/
|
||||
PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
|
||||
/* Get the I2C1 clock source -----------------------------------------------*/
|
||||
PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
|
||||
|
||||
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
|
||||
|| defined(STM32F091xC) || defined(STM32F098xx)
|
||||
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART2;
|
||||
/* Get the USART2 clock source ---------------------------------------------*/
|
||||
PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
|
||||
#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
|
||||
/* STM32F091xC || STM32F098xx */
|
||||
|
||||
#if defined(STM32F091xC) || defined(STM32F098xx)
|
||||
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART3;
|
||||
/* Get the USART3 clock source ---------------------------------------------*/
|
||||
PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
|
||||
#endif /* STM32F091xC || STM32F098xx */
|
||||
|
||||
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F070x6)
|
||||
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
|
||||
/* Get the USB clock source ---------------------------------------------*/
|
||||
PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
|
||||
#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */
|
||||
|
||||
#if defined(STM32F042x6) || defined(STM32F048xx)\
|
||||
|| defined(STM32F051x8) || defined(STM32F058xx)\
|
||||
|| defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
|
||||
|| defined(STM32F091xC) || defined(STM32F098xx)
|
||||
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_CEC;
|
||||
/* Get the CEC clock source ------------------------------------------------*/
|
||||
PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
|
||||
#endif /* STM32F042x6 || STM32F048xx || */
|
||||
/* STM32F051x8 || STM32F058xx || */
|
||||
/* STM32F071xB || STM32F072xB || STM32F078xx || */
|
||||
/* STM32F091xC || STM32F098xx */
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the peripheral clock frequency
|
||||
* @note Returns 0 if peripheral clock is unknown
|
||||
* @param PeriphClk Peripheral clock identifier
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
|
||||
* @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
|
||||
* @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
|
||||
@if STM32F042x6
|
||||
* @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
|
||||
* @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
|
||||
@endif
|
||||
@if STM32F048xx
|
||||
* @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
|
||||
* @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
|
||||
@endif
|
||||
@if STM32F051x8
|
||||
* @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
|
||||
@endif
|
||||
@if STM32F058xx
|
||||
* @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
|
||||
@endif
|
||||
@if STM32F070x6
|
||||
* @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
|
||||
@endif
|
||||
@if STM32F070xB
|
||||
* @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
|
||||
@endif
|
||||
@if STM32F071xB
|
||||
* @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
|
||||
* @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
|
||||
@endif
|
||||
@if STM32F072xB
|
||||
* @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
|
||||
* @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
|
||||
* @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
|
||||
@endif
|
||||
@if STM32F078xx
|
||||
* @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
|
||||
* @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
|
||||
* @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
|
||||
@endif
|
||||
@if STM32F091xC
|
||||
* @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
|
||||
* @arg @ref RCC_PERIPHCLK_USART3 USART2 peripheral clock
|
||||
* @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
|
||||
@endif
|
||||
@if STM32F098xx
|
||||
* @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
|
||||
* @arg @ref RCC_PERIPHCLK_USART3 USART2 peripheral clock
|
||||
* @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
|
||||
@endif
|
||||
* @retval Frequency in Hz (0: means that no available frequency for the peripheral)
|
||||
*/
|
||||
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
|
||||
{
|
||||
/* frequency == 0 : means that no available frequency for the peripheral */
|
||||
uint32_t frequency = 0U;
|
||||
|
||||
uint32_t srcclk = 0U;
|
||||
#if defined(USB)
|
||||
uint32_t pllmull = 0U, pllsource = 0U, predivfactor = 0U;
|
||||
#endif /* USB */
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
|
||||
|
||||
switch (PeriphClk)
|
||||
{
|
||||
case RCC_PERIPHCLK_RTC:
|
||||
{
|
||||
/* Get the current RTC source */
|
||||
srcclk = __HAL_RCC_GET_RTC_SOURCE();
|
||||
|
||||
/* Check if LSE is ready and if RTC clock selection is LSE */
|
||||
if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
|
||||
{
|
||||
frequency = LSE_VALUE;
|
||||
}
|
||||
/* Check if LSI is ready and if RTC clock selection is LSI */
|
||||
else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
|
||||
{
|
||||
frequency = LSI_VALUE;
|
||||
}
|
||||
/* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/
|
||||
else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
|
||||
{
|
||||
frequency = HSE_VALUE / 32U;
|
||||
}
|
||||
break;
|
||||
}
|
||||
case RCC_PERIPHCLK_USART1:
|
||||
{
|
||||
/* Get the current USART1 source */
|
||||
srcclk = __HAL_RCC_GET_USART1_SOURCE();
|
||||
|
||||
/* Check if USART1 clock selection is PCLK1 */
|
||||
if (srcclk == RCC_USART1CLKSOURCE_PCLK1)
|
||||
{
|
||||
frequency = HAL_RCC_GetPCLK1Freq();
|
||||
}
|
||||
/* Check if HSI is ready and if USART1 clock selection is HSI */
|
||||
else if ((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
|
||||
{
|
||||
frequency = HSI_VALUE;
|
||||
}
|
||||
/* Check if USART1 clock selection is SYSCLK */
|
||||
else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK)
|
||||
{
|
||||
frequency = HAL_RCC_GetSysClockFreq();
|
||||
}
|
||||
/* Check if LSE is ready and if USART1 clock selection is LSE */
|
||||
else if ((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
|
||||
{
|
||||
frequency = LSE_VALUE;
|
||||
}
|
||||
break;
|
||||
}
|
||||
#if defined(RCC_CFGR3_USART2SW)
|
||||
case RCC_PERIPHCLK_USART2:
|
||||
{
|
||||
/* Get the current USART2 source */
|
||||
srcclk = __HAL_RCC_GET_USART2_SOURCE();
|
||||
|
||||
/* Check if USART2 clock selection is PCLK1 */
|
||||
if (srcclk == RCC_USART2CLKSOURCE_PCLK1)
|
||||
{
|
||||
frequency = HAL_RCC_GetPCLK1Freq();
|
||||
}
|
||||
/* Check if HSI is ready and if USART2 clock selection is HSI */
|
||||
else if ((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
|
||||
{
|
||||
frequency = HSI_VALUE;
|
||||
}
|
||||
/* Check if USART2 clock selection is SYSCLK */
|
||||
else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK)
|
||||
{
|
||||
frequency = HAL_RCC_GetSysClockFreq();
|
||||
}
|
||||
/* Check if LSE is ready and if USART2 clock selection is LSE */
|
||||
else if ((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
|
||||
{
|
||||
frequency = LSE_VALUE;
|
||||
}
|
||||
break;
|
||||
}
|
||||
#endif /* RCC_CFGR3_USART2SW */
|
||||
#if defined(RCC_CFGR3_USART3SW)
|
||||
case RCC_PERIPHCLK_USART3:
|
||||
{
|
||||
/* Get the current USART3 source */
|
||||
srcclk = __HAL_RCC_GET_USART3_SOURCE();
|
||||
|
||||
/* Check if USART3 clock selection is PCLK1 */
|
||||
if (srcclk == RCC_USART3CLKSOURCE_PCLK1)
|
||||
{
|
||||
frequency = HAL_RCC_GetPCLK1Freq();
|
||||
}
|
||||
/* Check if HSI is ready and if USART3 clock selection is HSI */
|
||||
else if ((srcclk == RCC_USART3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
|
||||
{
|
||||
frequency = HSI_VALUE;
|
||||
}
|
||||
/* Check if USART3 clock selection is SYSCLK */
|
||||
else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK)
|
||||
{
|
||||
frequency = HAL_RCC_GetSysClockFreq();
|
||||
}
|
||||
/* Check if LSE is ready and if USART3 clock selection is LSE */
|
||||
else if ((srcclk == RCC_USART3CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
|
||||
{
|
||||
frequency = LSE_VALUE;
|
||||
}
|
||||
break;
|
||||
}
|
||||
#endif /* RCC_CFGR3_USART3SW */
|
||||
case RCC_PERIPHCLK_I2C1:
|
||||
{
|
||||
/* Get the current I2C1 source */
|
||||
srcclk = __HAL_RCC_GET_I2C1_SOURCE();
|
||||
|
||||
/* Check if HSI is ready and if I2C1 clock selection is HSI */
|
||||
if ((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
|
||||
{
|
||||
frequency = HSI_VALUE;
|
||||
}
|
||||
/* Check if I2C1 clock selection is SYSCLK */
|
||||
else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
|
||||
{
|
||||
frequency = HAL_RCC_GetSysClockFreq();
|
||||
}
|
||||
break;
|
||||
}
|
||||
#if defined(USB)
|
||||
case RCC_PERIPHCLK_USB:
|
||||
{
|
||||
/* Get the current USB source */
|
||||
srcclk = __HAL_RCC_GET_USB_SOURCE();
|
||||
|
||||
/* Check if PLL is ready and if USB clock selection is PLL */
|
||||
if ((srcclk == RCC_USBCLKSOURCE_PLL) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
|
||||
{
|
||||
/* Get PLL clock source and multiplication factor ----------------------*/
|
||||
pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
|
||||
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
|
||||
pllmull = (pllmull >> RCC_CFGR_PLLMUL_BITNUMBER) + 2U;
|
||||
predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1U;
|
||||
|
||||
if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
|
||||
{
|
||||
/* HSE used as PLL clock source : frequency = HSE/PREDIV * PLLMUL */
|
||||
frequency = (HSE_VALUE/predivfactor) * pllmull;
|
||||
}
|
||||
#if defined(RCC_CR2_HSI48ON)
|
||||
else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
|
||||
{
|
||||
/* HSI48 used as PLL clock source : frequency = HSI48/PREDIV * PLLMUL */
|
||||
frequency = (HSI48_VALUE / predivfactor) * pllmull;
|
||||
}
|
||||
#endif /* RCC_CR2_HSI48ON */
|
||||
else
|
||||
{
|
||||
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F078xx) || defined(STM32F072xB) || defined(STM32F070xB)
|
||||
/* HSI used as PLL clock source : frequency = HSI/PREDIV * PLLMUL */
|
||||
frequency = (HSI_VALUE / predivfactor) * pllmull;
|
||||
#else
|
||||
/* HSI used as PLL clock source : frequency = HSI/2U * PLLMUL */
|
||||
frequency = (HSI_VALUE >> 1U) * pllmull;
|
||||
#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB */
|
||||
}
|
||||
}
|
||||
#if defined(RCC_CR2_HSI48ON)
|
||||
/* Check if HSI48 is ready and if USB clock selection is HSI48 */
|
||||
else if ((srcclk == RCC_USBCLKSOURCE_HSI48) && (HAL_IS_BIT_SET(RCC->CR2, RCC_CR2_HSI48RDY)))
|
||||
{
|
||||
frequency = HSI48_VALUE;
|
||||
}
|
||||
#endif /* RCC_CR2_HSI48ON */
|
||||
break;
|
||||
}
|
||||
#endif /* USB */
|
||||
#if defined(CEC)
|
||||
case RCC_PERIPHCLK_CEC:
|
||||
{
|
||||
/* Get the current CEC source */
|
||||
srcclk = __HAL_RCC_GET_CEC_SOURCE();
|
||||
|
||||
/* Check if HSI is ready and if CEC clock selection is HSI */
|
||||
if ((srcclk == RCC_CECCLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
|
||||
{
|
||||
frequency = HSI_VALUE;
|
||||
}
|
||||
/* Check if LSE is ready and if CEC clock selection is LSE */
|
||||
else if ((srcclk == RCC_CECCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
|
||||
{
|
||||
frequency = LSE_VALUE;
|
||||
}
|
||||
break;
|
||||
}
|
||||
#endif /* CEC */
|
||||
default:
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
return(frequency);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(CRS)
|
||||
|
||||
/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
|
||||
* @brief Extended Clock Recovery System Control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extended Clock Recovery System Control functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows:
|
||||
|
||||
(#) In System clock config, HSI48 needs to be enabled
|
||||
|
||||
(#) Enable CRS clock in IP MSP init which will use CRS functions
|
||||
|
||||
(#) Call CRS functions as follows:
|
||||
(##) Prepare synchronization configuration necessary for HSI48 calibration
|
||||
(+++) Default values can be set for frequency Error Measurement (reload and error limit)
|
||||
and also HSI48 oscillator smooth trimming.
|
||||
(+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
|
||||
directly reload value with target and synchronization frequencies values
|
||||
(##) Call function HAL_RCCEx_CRSConfig which
|
||||
(+++) Reset CRS registers to their default values.
|
||||
(+++) Configure CRS registers with synchronization configuration
|
||||
(+++) Enable automatic calibration and frequency error counter feature
|
||||
Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
|
||||
periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
|
||||
provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
|
||||
precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
|
||||
should be used as SYNC signal.
|
||||
|
||||
(##) A polling function is provided to wait for complete synchronization
|
||||
(+++) Call function HAL_RCCEx_CRSWaitSynchronization()
|
||||
(+++) According to CRS status, user can decide to adjust again the calibration or continue
|
||||
application if synchronization is OK
|
||||
|
||||
(#) User can retrieve information related to synchronization in calling function
|
||||
HAL_RCCEx_CRSGetSynchronizationInfo()
|
||||
|
||||
(#) Regarding synchronization status and synchronization information, user can try a new calibration
|
||||
in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
|
||||
Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value),
|
||||
it means that the actual frequency is lower than the target (and so, that the TRIM value should be
|
||||
incremented), while when it is detected during the upcounting phase it means that the actual frequency
|
||||
is higher (and that the TRIM value should be decremented).
|
||||
|
||||
(#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
|
||||
through CRS Handler (RCC_IRQn/RCC_IRQHandler)
|
||||
(++) Call function HAL_RCCEx_CRSConfig()
|
||||
(++) Enable RCC_IRQn (thanks to NVIC functions)
|
||||
(++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)
|
||||
(++) Implement CRS status management in the following user callbacks called from
|
||||
HAL_RCCEx_CRS_IRQHandler():
|
||||
(+++) HAL_RCCEx_CRS_SyncOkCallback()
|
||||
(+++) HAL_RCCEx_CRS_SyncWarnCallback()
|
||||
(+++) HAL_RCCEx_CRS_ExpectedSyncCallback()
|
||||
(+++) HAL_RCCEx_CRS_ErrorCallback()
|
||||
|
||||
(#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
|
||||
This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Start automatic synchronization for polling mode
|
||||
* @param pInit Pointer on RCC_CRSInitTypeDef structure
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
|
||||
{
|
||||
uint32_t value = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
|
||||
assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
|
||||
assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
|
||||
assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
|
||||
assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
|
||||
assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
|
||||
|
||||
/* CONFIGURATION */
|
||||
|
||||
/* Before configuration, reset CRS registers to their default values*/
|
||||
__HAL_RCC_CRS_FORCE_RESET();
|
||||
__HAL_RCC_CRS_RELEASE_RESET();
|
||||
|
||||
/* Set the SYNCDIV[2:0] bits according to Prescaler value */
|
||||
/* Set the SYNCSRC[1:0] bits according to Source value */
|
||||
/* Set the SYNCSPOL bit according to Polarity value */
|
||||
value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
|
||||
/* Set the RELOAD[15:0] bits according to ReloadValue value */
|
||||
value |= pInit->ReloadValue;
|
||||
/* Set the FELIM[7:0] bits according to ErrorLimitValue value */
|
||||
value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_BITNUMBER);
|
||||
WRITE_REG(CRS->CFGR, value);
|
||||
|
||||
/* Adjust HSI48 oscillator smooth trimming */
|
||||
/* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */
|
||||
MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_BITNUMBER));
|
||||
|
||||
/* START AUTOMATIC SYNCHRONIZATION*/
|
||||
|
||||
/* Enable Automatic trimming & Frequency error counter */
|
||||
SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Generate the software synchronization event
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
|
||||
{
|
||||
SET_BIT(CRS->CR, CRS_CR_SWSYNC);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return synchronization info
|
||||
* @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(pSynchroInfo != NULL);
|
||||
|
||||
/* Get the reload value */
|
||||
pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
|
||||
|
||||
/* Get HSI48 oscillator smooth trimming */
|
||||
pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_BITNUMBER);
|
||||
|
||||
/* Get Frequency error capture */
|
||||
pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_BITNUMBER);
|
||||
|
||||
/* Get Frequency error direction */
|
||||
pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Wait for CRS Synchronization status.
|
||||
* @param Timeout Duration of the timeout
|
||||
* @note Timeout is based on the maximum time to receive a SYNC event based on synchronization
|
||||
* frequency.
|
||||
* @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
|
||||
* @retval Combination of Synchronization status
|
||||
* This parameter can be a combination of the following values:
|
||||
* @arg @ref RCC_CRS_TIMEOUT
|
||||
* @arg @ref RCC_CRS_SYNCOK
|
||||
* @arg @ref RCC_CRS_SYNCWARN
|
||||
* @arg @ref RCC_CRS_SYNCERR
|
||||
* @arg @ref RCC_CRS_SYNCMISS
|
||||
* @arg @ref RCC_CRS_TRIMOVF
|
||||
*/
|
||||
uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
|
||||
{
|
||||
uint32_t crsstatus = RCC_CRS_NONE;
|
||||
uint32_t tickstart = 0U;
|
||||
|
||||
/* Get timeout */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait for CRS flag or timeout detection */
|
||||
do
|
||||
{
|
||||
if(Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
|
||||
{
|
||||
crsstatus = RCC_CRS_TIMEOUT;
|
||||
}
|
||||
}
|
||||
/* Check CRS SYNCOK flag */
|
||||
if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
|
||||
{
|
||||
/* CRS SYNC event OK */
|
||||
crsstatus |= RCC_CRS_SYNCOK;
|
||||
|
||||
/* Clear CRS SYNC event OK bit */
|
||||
__HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
|
||||
}
|
||||
|
||||
/* Check CRS SYNCWARN flag */
|
||||
if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
|
||||
{
|
||||
/* CRS SYNC warning */
|
||||
crsstatus |= RCC_CRS_SYNCWARN;
|
||||
|
||||
/* Clear CRS SYNCWARN bit */
|
||||
__HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
|
||||
}
|
||||
|
||||
/* Check CRS TRIM overflow flag */
|
||||
if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
|
||||
{
|
||||
/* CRS SYNC Error */
|
||||
crsstatus |= RCC_CRS_TRIMOVF;
|
||||
|
||||
/* Clear CRS Error bit */
|
||||
__HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
|
||||
}
|
||||
|
||||
/* Check CRS Error flag */
|
||||
if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
|
||||
{
|
||||
/* CRS SYNC Error */
|
||||
crsstatus |= RCC_CRS_SYNCERR;
|
||||
|
||||
/* Clear CRS Error bit */
|
||||
__HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
|
||||
}
|
||||
|
||||
/* Check CRS SYNC Missed flag */
|
||||
if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
|
||||
{
|
||||
/* CRS SYNC Missed */
|
||||
crsstatus |= RCC_CRS_SYNCMISS;
|
||||
|
||||
/* Clear CRS SYNC Missed bit */
|
||||
__HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
|
||||
}
|
||||
|
||||
/* Check CRS Expected SYNC flag */
|
||||
if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
|
||||
{
|
||||
/* frequency error counter reached a zero value */
|
||||
__HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
|
||||
}
|
||||
} while(RCC_CRS_NONE == crsstatus);
|
||||
|
||||
return crsstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handle the Clock Recovery System interrupt request.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_RCCEx_CRS_IRQHandler(void)
|
||||
{
|
||||
uint32_t crserror = RCC_CRS_NONE;
|
||||
/* Get current IT flags and IT sources values */
|
||||
uint32_t itflags = READ_REG(CRS->ISR);
|
||||
uint32_t itsources = READ_REG(CRS->CR);
|
||||
|
||||
/* Check CRS SYNCOK flag */
|
||||
if(((itflags & RCC_CRS_FLAG_SYNCOK) != RESET) && ((itsources & RCC_CRS_IT_SYNCOK) != RESET))
|
||||
{
|
||||
/* Clear CRS SYNC event OK flag */
|
||||
WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
|
||||
|
||||
/* user callback */
|
||||
HAL_RCCEx_CRS_SyncOkCallback();
|
||||
}
|
||||
/* Check CRS SYNCWARN flag */
|
||||
else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != RESET) && ((itsources & RCC_CRS_IT_SYNCWARN) != RESET))
|
||||
{
|
||||
/* Clear CRS SYNCWARN flag */
|
||||
WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
|
||||
|
||||
/* user callback */
|
||||
HAL_RCCEx_CRS_SyncWarnCallback();
|
||||
}
|
||||
/* Check CRS Expected SYNC flag */
|
||||
else if(((itflags & RCC_CRS_FLAG_ESYNC) != RESET) && ((itsources & RCC_CRS_IT_ESYNC) != RESET))
|
||||
{
|
||||
/* frequency error counter reached a zero value */
|
||||
WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
|
||||
|
||||
/* user callback */
|
||||
HAL_RCCEx_CRS_ExpectedSyncCallback();
|
||||
}
|
||||
/* Check CRS Error flags */
|
||||
else
|
||||
{
|
||||
if(((itflags & RCC_CRS_FLAG_ERR) != RESET) && ((itsources & RCC_CRS_IT_ERR) != RESET))
|
||||
{
|
||||
if((itflags & RCC_CRS_FLAG_SYNCERR) != RESET)
|
||||
{
|
||||
crserror |= RCC_CRS_SYNCERR;
|
||||
}
|
||||
if((itflags & RCC_CRS_FLAG_SYNCMISS) != RESET)
|
||||
{
|
||||
crserror |= RCC_CRS_SYNCMISS;
|
||||
}
|
||||
if((itflags & RCC_CRS_FLAG_TRIMOVF) != RESET)
|
||||
{
|
||||
crserror |= RCC_CRS_TRIMOVF;
|
||||
}
|
||||
|
||||
/* Clear CRS Error flags */
|
||||
WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
|
||||
|
||||
/* user error callback */
|
||||
HAL_RCCEx_CRS_ErrorCallback(crserror);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief RCCEx Clock Recovery System SYNCOK interrupt callback.
|
||||
* @retval none
|
||||
*/
|
||||
__weak void HAL_RCCEx_CRS_SyncOkCallback(void)
|
||||
{
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief RCCEx Clock Recovery System SYNCWARN interrupt callback.
|
||||
* @retval none
|
||||
*/
|
||||
__weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
|
||||
{
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief RCCEx Clock Recovery System Expected SYNC interrupt callback.
|
||||
* @retval none
|
||||
*/
|
||||
__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
|
||||
{
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief RCCEx Clock Recovery System Error interrupt callback.
|
||||
* @param Error Combination of Error status.
|
||||
* This parameter can be a combination of the following values:
|
||||
* @arg @ref RCC_CRS_SYNCERR
|
||||
* @arg @ref RCC_CRS_SYNCMISS
|
||||
* @arg @ref RCC_CRS_TRIMOVF
|
||||
* @retval none
|
||||
*/
|
||||
__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(Error);
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* CRS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_RCC_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
1779
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rtc.c
Normal file
1779
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rtc.c
Normal file
File diff suppressed because it is too large
Load Diff
1740
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rtc_ex.c
Normal file
1740
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rtc_ex.c
Normal file
File diff suppressed because it is too large
Load Diff
2929
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_smartcard.c
Normal file
2929
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_smartcard.c
Normal file
File diff suppressed because it is too large
Load Diff
198
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_smartcard_ex.c
Normal file
198
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_smartcard_ex.c
Normal file
@@ -0,0 +1,198 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_smartcard_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief SMARTCARD HAL module driver.
|
||||
* This file provides extended firmware functions to manage the following
|
||||
* functionalities of the SmartCard.
|
||||
* + Initialization and de-initialization functions
|
||||
* + Peripheral Control functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
=============================================================================
|
||||
##### SMARTCARD peripheral extended features #####
|
||||
=============================================================================
|
||||
[..]
|
||||
The Extended SMARTCARD HAL driver can be used as follows:
|
||||
|
||||
(#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
|
||||
then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut,
|
||||
auto-retry counter,...) in the hsmartcard AdvancedInit structure.
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
*/
|
||||
#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) \
|
||||
&& !defined(STM32F070xB) && !defined(STM32F030xC)
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARDEx SMARTCARDEx
|
||||
* @brief SMARTCARD Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
#ifdef HAL_SMARTCARD_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup SMARTCARDEx_Exported_Functions SMARTCARD Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions
|
||||
* @brief Extended control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to initialize the SMARTCARD.
|
||||
(+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
|
||||
(+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
|
||||
(+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature
|
||||
(+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Update on the fly the SMARTCARD block length in RTOR register.
|
||||
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified SMARTCARD module.
|
||||
* @param BlockLength SMARTCARD block length (8-bit long at most)
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
|
||||
{
|
||||
MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << USART_RTOR_BLEN_Pos));
|
||||
}
|
||||
|
||||
/** @brief Update on the fly the receiver timeout value in RTOR register.
|
||||
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified SMARTCARD module.
|
||||
* @param TimeOutValue receiver timeout value in number of baud blocks. The timeout
|
||||
* value must be less or equal to 0x0FFFFFFFF.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
|
||||
{
|
||||
assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
|
||||
MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_RTO, TimeOutValue);
|
||||
}
|
||||
|
||||
/** @brief Enable the SMARTCARD receiver timeout feature.
|
||||
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified SMARTCARD module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
|
||||
{
|
||||
if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hsmartcard);
|
||||
|
||||
hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
|
||||
|
||||
/* Set the USART RTOEN bit */
|
||||
SET_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
|
||||
|
||||
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hsmartcard);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/** @brief Disable the SMARTCARD receiver timeout feature.
|
||||
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified SMARTCARD module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
|
||||
{
|
||||
if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hsmartcard);
|
||||
|
||||
hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
|
||||
|
||||
/* Clear the USART RTOEN bit */
|
||||
CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
|
||||
|
||||
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hsmartcard);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARDEx_Exported_Functions_Group2 Extended Peripheral IO operation functions
|
||||
* @brief SMARTCARD Transmit and Receive functions
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARDEx_Private_Functions SMARTCARD Extended Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* !STM32F030x6 && !STM32F030x8 && !STM32F070x6 && !STM32F070xB && !STM32F030xC */
|
||||
2810
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_smbus.c
Normal file
2810
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_smbus.c
Normal file
File diff suppressed because it is too large
Load Diff
4448
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_spi.c
Normal file
4448
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_spi.c
Normal file
File diff suppressed because it is too large
Load Diff
112
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_spi_ex.c
Normal file
112
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_spi_ex.c
Normal file
@@ -0,0 +1,112 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_spi_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief Extended SPI HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* SPI peripheral extended functionalities :
|
||||
* + IO operation functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SPIEx SPIEx
|
||||
* @brief SPI Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
#ifdef HAL_SPI_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/** @defgroup SPIEx_Private_Constants SPIEx Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define SPI_FIFO_SIZE 4UL
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions
|
||||
* @brief Data transfers functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of extended functions to manage the SPI
|
||||
data transfers.
|
||||
|
||||
(#) Rx data flush function:
|
||||
(++) HAL_SPIEx_FlushRxFifo()
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Flush the RX fifo.
|
||||
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified SPI module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi)
|
||||
{
|
||||
__IO uint32_t tmpreg;
|
||||
uint8_t count = 0U;
|
||||
while ((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_FRLVL_EMPTY)
|
||||
{
|
||||
count++;
|
||||
tmpreg = hspi->Instance->DR;
|
||||
UNUSED(tmpreg); /* To avoid GCC warning */
|
||||
if (count == SPI_FIFO_SIZE)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_SPI_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
7641
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c
Normal file
7641
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c
Normal file
File diff suppressed because it is too large
Load Diff
2372
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c
Normal file
2372
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c
Normal file
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,319 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_timebase_rtc_alarm_template.c
|
||||
* @brief HAL time base based on the hardware RTC_ALARM Template.
|
||||
*
|
||||
* This file override the native HAL time base functions (defined as weak)
|
||||
* to use the RTC ALARM for time base generation:
|
||||
* + Initializes the RTC peripheral to increment the seconds registers each 1ms
|
||||
* + The alarm is configured to assert an interrupt when the RTC reaches 1ms
|
||||
* + HAL_IncTick is called at each Alarm event and the time is reset to 00:00:00
|
||||
* + HSE (default), LSE or LSI can be selected as RTC clock source
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This file must be copied to the application folder and modified as follows:
|
||||
(#) Rename it to 'stm32f0xx_hal_timebase_rtc_alarm.c'
|
||||
(#) Add this file and the RTC HAL drivers to your project and uncomment
|
||||
HAL_RTC_MODULE_ENABLED define in stm32f0xx_hal_conf.h
|
||||
|
||||
[..]
|
||||
(@) HAL RTC alarm and HAL RTC wakeup drivers can<61>t be used with low power modes:
|
||||
The wake up capability of the RTC may be intrusive in case of prior low power mode
|
||||
configuration requiring different wake up sources.
|
||||
Application/Example behavior is no more guaranteed
|
||||
(@) The stm32f0xx_hal_timebase_tim use is recommended for the Applications/Examples
|
||||
requiring low power modes
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_TimeBase_RTC_Alarm_Template HAL TimeBase RTC Alarm Template
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
|
||||
/* Uncomment the line below to select the appropriate RTC Clock source for your application:
|
||||
+ RTC_CLOCK_SOURCE_HSE: can be selected for applications requiring timing precision.
|
||||
+ RTC_CLOCK_SOURCE_LSE: can be selected for applications with low constraint on timing
|
||||
precision.
|
||||
+ RTC_CLOCK_SOURCE_LSI: can be selected for applications with low constraint on timing
|
||||
precision.
|
||||
*/
|
||||
#define RTC_CLOCK_SOURCE_HSE
|
||||
/* #define RTC_CLOCK_SOURCE_LSE */
|
||||
/* #define RTC_CLOCK_SOURCE_LSI */
|
||||
|
||||
#if defined(RTC_CLOCK_SOURCE_HSE)
|
||||
#define RTC_ASYNCH_PREDIV 49U
|
||||
#define RTC_SYNCH_PREDIV 4U
|
||||
#elif defined(RTC_CLOCK_SOURCE_LSE)
|
||||
#define RTC_ASYNCH_PREDIV 0U
|
||||
#define RTC_SYNCH_PREDIV 31U
|
||||
#else /* CLOCK_SOURCE_LSI */
|
||||
#define RTC_ASYNCH_PREDIV 0U
|
||||
#define RTC_SYNCH_PREDIV 39U
|
||||
#endif /* RTC_CLOCK_SOURCE_HSE */
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
RTC_HandleTypeDef hRTC_Handle;
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
void RTC_IRQHandler(void);
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief This function configures the RTC_ALARMA as a time base source.
|
||||
* The time source is configured to have 1ms time base with a dedicated
|
||||
* Tick interrupt priority.
|
||||
* @note This function is called automatically at the beginning of program after
|
||||
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
|
||||
* @param TickPriority Tick interrupt priority.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
|
||||
{
|
||||
__IO uint32_t counter = 0U;
|
||||
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct;
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
|
||||
HAL_StatusTypeDef status;
|
||||
|
||||
#ifdef RTC_CLOCK_SOURCE_LSE
|
||||
/* Configure LSE as RTC clock source */
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
|
||||
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
|
||||
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
|
||||
#elif defined (RTC_CLOCK_SOURCE_LSI)
|
||||
/* Configure LSI as RTC clock source */
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
|
||||
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
|
||||
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
|
||||
#elif defined (RTC_CLOCK_SOURCE_HSE)
|
||||
/* Configure HSE as RTC clock source */
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
||||
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_HSE_DIV32;
|
||||
#else
|
||||
#error Please select the RTC Clock source
|
||||
#endif /* RTC_CLOCK_SOURCE_LSE */
|
||||
|
||||
status = HAL_RCC_OscConfig(&RCC_OscInitStruct);
|
||||
if (status == HAL_OK)
|
||||
{
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
|
||||
status = HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
|
||||
}
|
||||
if (status == HAL_OK)
|
||||
{
|
||||
/* Enable RTC Clock */
|
||||
__HAL_RCC_RTC_ENABLE();
|
||||
/* The time base should be 1ms
|
||||
Time base = ((RTC_ASYNCH_PREDIV + 1) * (RTC_SYNCH_PREDIV + 1)) / RTC_CLOCK
|
||||
HSE/32 as RTC clock and HSE 8MHz
|
||||
Time base = ((49 + 1) * (4 + 1)) / 250kHz
|
||||
= 1ms
|
||||
LSE as RTC clock
|
||||
Time base = ((31 + 1) * (0 + 1)) / 32.768KHz
|
||||
= ~1ms
|
||||
LSI as RTC clock
|
||||
Time base = ((39 + 1) * (0 + 1)) / 40KHz
|
||||
= 1ms
|
||||
*/
|
||||
hRTC_Handle.Instance = RTC;
|
||||
hRTC_Handle.Init.HourFormat = RTC_HOURFORMAT_24;
|
||||
hRTC_Handle.Init.AsynchPrediv = RTC_ASYNCH_PREDIV;
|
||||
hRTC_Handle.Init.SynchPrediv = RTC_SYNCH_PREDIV;
|
||||
hRTC_Handle.Init.OutPut = RTC_OUTPUT_DISABLE;
|
||||
hRTC_Handle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
|
||||
hRTC_Handle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
|
||||
status = HAL_RTC_Init(&hRTC_Handle);
|
||||
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
|
||||
|
||||
/* Disable the Alarm A interrupt */
|
||||
__HAL_RTC_ALARMA_DISABLE(&hRTC_Handle);
|
||||
|
||||
/* Clear flag alarm A */
|
||||
__HAL_RTC_ALARM_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_ALRAF);
|
||||
|
||||
counter = 0U;
|
||||
/* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
|
||||
while (__HAL_RTC_ALARM_GET_FLAG(&hRTC_Handle, RTC_FLAG_ALRAWF) == RESET)
|
||||
{
|
||||
if (counter++ == (SystemCoreClock / 48U)) /* Timeout = ~ 1s */
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
if (status == HAL_OK)
|
||||
{
|
||||
hRTC_Handle.Instance->ALRMAR = 0x01U;
|
||||
|
||||
/* Configure the Alarm state: Enable Alarm */
|
||||
__HAL_RTC_ALARMA_ENABLE(&hRTC_Handle);
|
||||
/* Configure the Alarm interrupt */
|
||||
__HAL_RTC_ALARM_ENABLE_IT(&hRTC_Handle, RTC_IT_ALRA);
|
||||
|
||||
/* RTC Alarm Interrupt Configuration: EXTI configuration */
|
||||
__HAL_RTC_ALARM_EXTI_ENABLE_IT();
|
||||
__HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
|
||||
|
||||
/* Check if the Initialization mode is set */
|
||||
if ((hRTC_Handle.Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
|
||||
{
|
||||
/* Set the Initialization mode */
|
||||
hRTC_Handle.Instance->ISR = (uint32_t)RTC_INIT_MASK;
|
||||
counter = 0U;
|
||||
while ((hRTC_Handle.Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
|
||||
{
|
||||
if (counter++ == (SystemCoreClock / 48U)) /* Timeout = ~ 1s */
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
if (status == HAL_OK)
|
||||
{
|
||||
hRTC_Handle.Instance->DR = 0U;
|
||||
hRTC_Handle.Instance->TR = 0U;
|
||||
|
||||
hRTC_Handle.Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
|
||||
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
|
||||
|
||||
/* Enable the RTC Alarm Interrupt */
|
||||
HAL_NVIC_EnableIRQ(RTC_IRQn);
|
||||
|
||||
/* Configure the SysTick IRQ priority */
|
||||
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
||||
{
|
||||
HAL_NVIC_SetPriority(RTC_IRQn, TickPriority, 0U);
|
||||
uwTickPrio = TickPriority;
|
||||
}
|
||||
else
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Suspend Tick increment.
|
||||
* @note Disable the tick increment by disabling RTC ALARM interrupt.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SuspendTick(void)
|
||||
{
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
|
||||
/* Disable RTC ALARM update Interrupt */
|
||||
__HAL_RTC_ALARM_DISABLE_IT(&hRTC_Handle, RTC_IT_ALRA);
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resume Tick increment.
|
||||
* @note Enable the tick increment by Enabling RTC ALARM interrupt.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_ResumeTick(void)
|
||||
{
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
|
||||
/* Enable RTC ALARM Update interrupt */
|
||||
__HAL_RTC_ALARM_ENABLE_IT(&hRTC_Handle, RTC_IT_ALRA);
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief ALARM A Event Callback in non blocking mode
|
||||
* @note This function is called when RTC_ALARM interrupt took place, inside
|
||||
* RTC_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
|
||||
* a global variable "uwTick" used as application time base.
|
||||
* @param hrtc RTC handle
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
|
||||
{
|
||||
__IO uint32_t counter = 0U;
|
||||
|
||||
HAL_IncTick();
|
||||
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
|
||||
/* Set the Initialization mode */
|
||||
hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
|
||||
|
||||
while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
|
||||
{
|
||||
if(counter++ == (SystemCoreClock /48U)) /* Timeout = ~ 1s */
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
hrtc->Instance->DR = 0U;
|
||||
hrtc->Instance->TR = 0U;
|
||||
|
||||
hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
|
||||
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles RTC ALARM interrupt request.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void RTC_IRQHandler(void)
|
||||
{
|
||||
HAL_RTC_AlarmIRQHandler(&hRTC_Handle);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
@@ -0,0 +1,296 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_timebase_rtc_wakeup_template.c
|
||||
* @brief HAL time base based on the hardware RTC_WAKEUP Template.
|
||||
*
|
||||
* This file overrides the native HAL time base functions (defined as weak)
|
||||
* to use the RTC WAKEUP for the time base generation:
|
||||
* + Initializes the RTC peripheral and configures the wakeup timer to be
|
||||
* incremented each 1ms
|
||||
* + The wakeup feature is configured to assert an interrupt each 1ms
|
||||
* + HAL_IncTick is called inside the HAL_RTCEx_WakeUpTimerEventCallback
|
||||
* + HSE (default), LSE or LSI can be selected as RTC clock source
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This file must be copied to the application folder and modified as follows:
|
||||
(#) Rename it to 'stm32f0xx_hal_timebase_rtc_wakeup.c'
|
||||
(#) Add this file and the RTC HAL drivers to your project and uncomment
|
||||
HAL_RTC_MODULE_ENABLED define in stm32f0xx_hal_conf.h
|
||||
|
||||
[..]
|
||||
(@) HAL RTC alarm and HAL RTC wakeup drivers can<61>t be used with low power modes:
|
||||
The wake up capability of the RTC may be intrusive in case of prior low power mode
|
||||
configuration requiring different wake up sources.
|
||||
Application/Example behavior is no more guaranteed
|
||||
(@) The stm32f0xx_hal_timebase_tim use is recommended for the Applications/Examples
|
||||
requiring low power modes
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_TimeBase_RTC_WakeUp_Template HAL TimeBase RTC WakeUp Template
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
|
||||
/* Uncomment the line below to select the appropriate RTC Clock source for your application:
|
||||
+ RTC_CLOCK_SOURCE_HSE: can be selected for applications requiring timing precision.
|
||||
+ RTC_CLOCK_SOURCE_LSE: can be selected for applications with low constraint on timing
|
||||
precision.
|
||||
+ RTC_CLOCK_SOURCE_LSI: can be selected for applications with low constraint on timing
|
||||
precision.
|
||||
*/
|
||||
#define RTC_CLOCK_SOURCE_HSE
|
||||
/* #define RTC_CLOCK_SOURCE_LSE */
|
||||
/* #define RTC_CLOCK_SOURCE_LSI */
|
||||
|
||||
#if defined(RTC_CLOCK_SOURCE_HSE)
|
||||
#define RTC_ASYNCH_PREDIV 49U
|
||||
#define RTC_SYNCH_PREDIV 4U
|
||||
#elif defined(RTC_CLOCK_SOURCE_LSE)
|
||||
#define RTC_ASYNCH_PREDIV 0U
|
||||
#define RTC_SYNCH_PREDIV 31U
|
||||
#else /* CLOCK_SOURCE_LSI */
|
||||
#define RTC_ASYNCH_PREDIV 0U
|
||||
#define RTC_SYNCH_PREDIV 39U
|
||||
#endif /* RTC_CLOCK_SOURCE_HSE */
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
RTC_HandleTypeDef hRTC_Handle;
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
void RTC_IRQHandler(void);
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief This function configures the RTC_WKUP as a time base source.
|
||||
* The time source is configured to have 1ms time base with a dedicated
|
||||
* Tick interrupt priority.
|
||||
* Wakeup Time base = ((RTC_ASYNCH_PREDIV + 1) * (RTC_SYNCH_PREDIV + 1)) / RTC_CLOCK
|
||||
= 1ms
|
||||
* Wakeup Time = WakeupTimebase * WakeUpCounter (0 + 1)
|
||||
= 1 ms
|
||||
* @note This function is called automatically at the beginning of program after
|
||||
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
|
||||
* @param TickPriority Tick interrupt priority.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
||||
{
|
||||
__IO uint32_t counter = 0U;
|
||||
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct;
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
|
||||
HAL_StatusTypeDef status;
|
||||
|
||||
#ifdef RTC_CLOCK_SOURCE_LSE
|
||||
/* Configure LSE as RTC clock source */
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
|
||||
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
|
||||
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
|
||||
#elif defined (RTC_CLOCK_SOURCE_LSI)
|
||||
/* Configure LSI as RTC clock source */
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
|
||||
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
|
||||
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
|
||||
#elif defined (RTC_CLOCK_SOURCE_HSE)
|
||||
/* Configure HSE as RTC clock source */
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
||||
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_HSE_DIV32;
|
||||
#else
|
||||
#error Please select the RTC Clock source
|
||||
#endif /* RTC_CLOCK_SOURCE_LSE */
|
||||
|
||||
status = HAL_RCC_OscConfig(&RCC_OscInitStruct);
|
||||
if (status == HAL_OK)
|
||||
{
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
|
||||
status = HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
|
||||
}
|
||||
if (status == HAL_OK)
|
||||
{
|
||||
/* Enable RTC Clock */
|
||||
__HAL_RCC_RTC_ENABLE();
|
||||
/* The time base should be 1ms
|
||||
Time base = ((RTC_ASYNCH_PREDIV + 1) * (RTC_SYNCH_PREDIV + 1)) / RTC_CLOCK
|
||||
HSE/32 as RTC clock and HSE 8MHz
|
||||
Time base = ((49 + 1) * (4 + 1)) / 250kHz
|
||||
= 1ms
|
||||
LSE as RTC clock
|
||||
Time base = ((31 + 1) * (0 + 1)) / 32.768Khz
|
||||
= ~1ms
|
||||
LSI as RTC clock
|
||||
Time base = ((39 + 1) * (0 + 1)) / 40Khz
|
||||
= 1ms
|
||||
*/
|
||||
hRTC_Handle.Instance = RTC;
|
||||
hRTC_Handle.Init.HourFormat = RTC_HOURFORMAT_24;
|
||||
hRTC_Handle.Init.AsynchPrediv = RTC_ASYNCH_PREDIV;
|
||||
hRTC_Handle.Init.SynchPrediv = RTC_SYNCH_PREDIV;
|
||||
hRTC_Handle.Init.OutPut = RTC_OUTPUT_DISABLE;
|
||||
hRTC_Handle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
|
||||
hRTC_Handle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
|
||||
status = HAL_RTC_Init(&hRTC_Handle);
|
||||
}
|
||||
if (status == HAL_OK)
|
||||
{
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
|
||||
|
||||
/* Disable the Wake-up Timer */
|
||||
__HAL_RTC_WAKEUPTIMER_DISABLE(&hRTC_Handle);
|
||||
|
||||
/* In case of interrupt mode is used, the interrupt source must disabled */
|
||||
__HAL_RTC_WAKEUPTIMER_DISABLE_IT(&hRTC_Handle,RTC_IT_WUT);
|
||||
|
||||
/* Wait till RTC WUTWF flag is set */
|
||||
while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hRTC_Handle, RTC_FLAG_WUTWF) == RESET)
|
||||
{
|
||||
if (counter++ == (SystemCoreClock /48U))
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
if (status == HAL_OK)
|
||||
{
|
||||
/* Clear PWR wake up Flag */
|
||||
__HAL_PWR_CLEAR_FLAG(PWR_FLAG_WU);
|
||||
|
||||
/* Clear RTC Wake Up timer Flag */
|
||||
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_WUTF);
|
||||
|
||||
/* Configure the Wake-up Timer counter */
|
||||
hRTC_Handle.Instance->WUTR = 0U;
|
||||
|
||||
/* Clear the Wake-up Timer clock source bits in CR register */
|
||||
hRTC_Handle.Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
|
||||
|
||||
/* Configure the clock source */
|
||||
hRTC_Handle.Instance->CR |= (uint32_t)RTC_WAKEUPCLOCK_CK_SPRE_16BITS;
|
||||
|
||||
/* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
|
||||
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
|
||||
|
||||
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
|
||||
|
||||
/* Configure the Interrupt in the RTC_CR register */
|
||||
__HAL_RTC_WAKEUPTIMER_ENABLE_IT(&hRTC_Handle, RTC_IT_WUT);
|
||||
|
||||
/* Enable the Wake-up Timer */
|
||||
__HAL_RTC_WAKEUPTIMER_ENABLE(&hRTC_Handle);
|
||||
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
|
||||
|
||||
/* Enable the RTC global Interrupt */
|
||||
HAL_NVIC_EnableIRQ(RTC_IRQn);
|
||||
|
||||
/* Configure the SysTick IRQ priority */
|
||||
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
||||
{
|
||||
HAL_NVIC_SetPriority(RTC_IRQn, TickPriority, 0U);
|
||||
uwTickPrio = TickPriority;
|
||||
}
|
||||
else
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Suspend Tick increment.
|
||||
* @note Disable the tick increment by disabling RTC_WKUP interrupt.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SuspendTick(void)
|
||||
{
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
|
||||
/* Disable WAKE UP TIMER Interrupt */
|
||||
__HAL_RTC_WAKEUPTIMER_DISABLE_IT(&hRTC_Handle, RTC_IT_WUT);
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resume Tick increment.
|
||||
* @note Enable the tick increment by Enabling RTC_WKUP interrupt.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_ResumeTick(void)
|
||||
{
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
|
||||
/* Enable WAKE UP TIMER interrupt */
|
||||
__HAL_RTC_WAKEUPTIMER_ENABLE_IT(&hRTC_Handle, RTC_IT_WUT);
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Wake Up Timer Event Callback in non blocking mode
|
||||
* @note This function is called when RTC_WKUP interrupt took place, inside
|
||||
* RTC_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
|
||||
* a global variable "uwTick" used as application time base.
|
||||
* @param hrtc RTC handle
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
|
||||
{
|
||||
HAL_IncTick();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles WAKE UP TIMER interrupt request.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void RTC_IRQHandler(void)
|
||||
{
|
||||
HAL_RTCEx_WakeUpTimerIRQHandler(&hRTC_Handle);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
@@ -0,0 +1,178 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_timebase_tim_template.c
|
||||
* @brief HAL time base based on the hardware TIM Template.
|
||||
*
|
||||
* This file override the native HAL time base functions (defined as weak)
|
||||
* the TIM time base:
|
||||
* + Initializes the TIM peripheral generate a Period elapsed Event each 1ms
|
||||
* + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback ie each 1ms
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL_TimeBase_TIM
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
TIM_HandleTypeDef TimHandle;
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
void TIM6_DAC_IRQHandler(void);
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief This function configures the TIM6 as a time base source.
|
||||
* The time source is configured to have 1ms time base with a dedicated
|
||||
* Tick interrupt priority.
|
||||
* @note This function is called automatically at the beginning of program after
|
||||
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
|
||||
* @param TickPriority Tick interrupt priority.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
|
||||
{
|
||||
RCC_ClkInitTypeDef clkconfig;
|
||||
uint32_t uwTimclock, uwAPB1Prescaler = 0U;
|
||||
uint32_t uwPrescalerValue = 0U;
|
||||
uint32_t pFLatency;
|
||||
HAL_StatusTypeDef status;
|
||||
|
||||
/* Enable TIM6 clock */
|
||||
__HAL_RCC_TIM6_CLK_ENABLE();
|
||||
|
||||
/* Get clock configuration */
|
||||
HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
|
||||
|
||||
/* Get APB1 prescaler */
|
||||
uwAPB1Prescaler = clkconfig.APB1CLKDivider;
|
||||
|
||||
/* Compute TIM6 clock */
|
||||
if (uwAPB1Prescaler == RCC_HCLK_DIV1)
|
||||
{
|
||||
uwTimclock = HAL_RCC_GetPCLK1Freq();
|
||||
}
|
||||
else
|
||||
{
|
||||
uwTimclock = 2 * HAL_RCC_GetPCLK1Freq();
|
||||
}
|
||||
|
||||
/* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */
|
||||
uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
|
||||
|
||||
/* Initialize TIM6 */
|
||||
TimHandle.Instance = TIM6;
|
||||
|
||||
/* Initialize TIMx peripheral as follow:
|
||||
+ Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base.
|
||||
+ Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
|
||||
+ ClockDivision = 0
|
||||
+ Counter direction = Up
|
||||
*/
|
||||
TimHandle.Init.Period = (1000000U / 1000U) - 1U;
|
||||
TimHandle.Init.Prescaler = uwPrescalerValue;
|
||||
TimHandle.Init.ClockDivision = 0U;
|
||||
TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
|
||||
TimHandle.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
||||
status = HAL_TIM_Base_Init(&TimHandle);
|
||||
if (status == HAL_OK)
|
||||
{
|
||||
/* Start the TIM time Base generation in interrupt mode */
|
||||
status = HAL_TIM_Base_Start_IT(&TimHandle);
|
||||
if (status == HAL_OK)
|
||||
{
|
||||
/* Enable the TIM6 global Interrupt */
|
||||
HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
|
||||
|
||||
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
||||
{
|
||||
/* Enable the TIM6 global Interrupt */
|
||||
HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority, 0);
|
||||
uwTickPrio = TickPriority;
|
||||
}
|
||||
else
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
/* Return function status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Suspend Tick increment.
|
||||
* @note Disable the tick increment by disabling TIM6 update interrupt.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SuspendTick(void)
|
||||
{
|
||||
/* Disable TIM6 update Interrupt */
|
||||
__HAL_TIM_DISABLE_IT(&TimHandle, TIM_IT_UPDATE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resume Tick increment.
|
||||
* @note Enable the tick increment by Enabling TIM6 update interrupt.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_ResumeTick(void)
|
||||
{
|
||||
/* Enable TIM6 Update interrupt */
|
||||
__HAL_TIM_ENABLE_IT(&TimHandle, TIM_IT_UPDATE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Period elapsed callback in non blocking mode
|
||||
* @note This function is called when TIM6 interrupt took place, inside
|
||||
* HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
|
||||
* a global variable "uwTick" used as application time base.
|
||||
* @param htim TIM handle
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
|
||||
{
|
||||
HAL_IncTick();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles TIM interrupt request.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void TIM6_DAC_IRQHandler(void)
|
||||
{
|
||||
HAL_TIM_IRQHandler(&TimHandle);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
1079
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tsc.c
Normal file
1079
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tsc.c
Normal file
File diff suppressed because it is too large
Load Diff
4180
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c
Normal file
4180
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c
Normal file
File diff suppressed because it is too large
Load Diff
839
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.c
Normal file
839
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.c
Normal file
@@ -0,0 +1,839 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_uart_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief Extended UART HAL module driver.
|
||||
* This file provides firmware functions to manage the following extended
|
||||
* functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
|
||||
* + Initialization and de-initialization functions
|
||||
* + Peripheral Control functions
|
||||
*
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### UART peripheral extended features #####
|
||||
==============================================================================
|
||||
|
||||
(#) Declare a UART_HandleTypeDef handle structure.
|
||||
|
||||
(#) For the UART RS485 Driver Enable mode, initialize the UART registers
|
||||
by calling the HAL_RS485Ex_Init() API.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UARTEx UARTEx
|
||||
* @brief UART Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_UART_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup UARTEx_Private_Functions UARTEx Private Functions
|
||||
* @{
|
||||
*/
|
||||
#if defined(USART_CR1_UESM)
|
||||
static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
|
||||
#endif /* USART_CR1_UESM */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Extended Initialization and Configuration Functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Configuration functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
|
||||
in asynchronous mode.
|
||||
(+) For the asynchronous mode the parameters below can be configured:
|
||||
(++) Baud Rate
|
||||
(++) Word Length
|
||||
(++) Stop Bit
|
||||
(++) Parity: If the parity is enabled, then the MSB bit of the data written
|
||||
in the data register is transmitted but is changed by the parity bit.
|
||||
(++) Hardware flow control
|
||||
(++) Receiver/transmitter modes
|
||||
(++) Over Sampling Method
|
||||
(++) One-Bit Sampling Method
|
||||
(+) For the asynchronous mode, the following advanced features can be configured as well:
|
||||
(++) TX and/or RX pin level inversion
|
||||
(++) data logical level inversion
|
||||
(++) RX and TX pins swap
|
||||
(++) RX overrun detection disabling
|
||||
(++) DMA disabling on RX error
|
||||
(++) MSB first on communication line
|
||||
(++) auto Baud rate detection
|
||||
[..]
|
||||
The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
|
||||
procedures (details for the procedures are available in reference manual).
|
||||
|
||||
@endverbatim
|
||||
|
||||
Depending on the frame length defined by the M1 and M0 bits (7-bit,
|
||||
8-bit or 9-bit), the possible UART formats are listed in the
|
||||
following table.
|
||||
|
||||
Table 1. UART frame format.
|
||||
+-----------------------------------------------------------------------+
|
||||
| M1 bit | M0 bit | PCE bit | UART frame |
|
||||
|---------|---------|-----------|---------------------------------------|
|
||||
| 0 | 0 | 0 | | SB | 8 bit data | STB | |
|
||||
|---------|---------|-----------|---------------------------------------|
|
||||
| 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
|
||||
|---------|---------|-----------|---------------------------------------|
|
||||
| 0 | 1 | 0 | | SB | 9 bit data | STB | |
|
||||
|---------|---------|-----------|---------------------------------------|
|
||||
| 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
|
||||
|---------|---------|-----------|---------------------------------------|
|
||||
| 1 | 0 | 0 | | SB | 7 bit data | STB | |
|
||||
|---------|---------|-----------|---------------------------------------|
|
||||
| 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
|
||||
+-----------------------------------------------------------------------+
|
||||
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initialize the RS485 Driver enable feature according to the specified
|
||||
* parameters in the UART_InitTypeDef and creates the associated handle.
|
||||
* @param huart UART handle.
|
||||
* @param Polarity Select the driver enable polarity.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
|
||||
* @arg @ref UART_DE_POLARITY_LOW DE signal is active low
|
||||
* @param AssertionTime Driver Enable assertion time:
|
||||
* 5-bit value defining the time between the activation of the DE (Driver Enable)
|
||||
* signal and the beginning of the start bit. It is expressed in sample time
|
||||
* units (1/8 or 1/16 bit time, depending on the oversampling rate)
|
||||
* @param DeassertionTime Driver Enable deassertion time:
|
||||
* 5-bit value defining the time between the end of the last stop bit, in a
|
||||
* transmitted message, and the de-activation of the DE (Driver Enable) signal.
|
||||
* It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
|
||||
* oversampling rate).
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
|
||||
uint32_t DeassertionTime)
|
||||
{
|
||||
uint32_t temp;
|
||||
|
||||
/* Check the UART handle allocation */
|
||||
if (huart == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Check the Driver Enable UART instance */
|
||||
assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
|
||||
|
||||
/* Check the Driver Enable polarity */
|
||||
assert_param(IS_UART_DE_POLARITY(Polarity));
|
||||
|
||||
/* Check the Driver Enable assertion time */
|
||||
assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
|
||||
|
||||
/* Check the Driver Enable deassertion time */
|
||||
assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
|
||||
|
||||
if (huart->gState == HAL_UART_STATE_RESET)
|
||||
{
|
||||
/* Allocate lock resource and initialize it */
|
||||
huart->Lock = HAL_UNLOCKED;
|
||||
|
||||
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
||||
UART_InitCallbacksToDefault(huart);
|
||||
|
||||
if (huart->MspInitCallback == NULL)
|
||||
{
|
||||
huart->MspInitCallback = HAL_UART_MspInit;
|
||||
}
|
||||
|
||||
/* Init the low level hardware */
|
||||
huart->MspInitCallback(huart);
|
||||
#else
|
||||
/* Init the low level hardware : GPIO, CLOCK, CORTEX */
|
||||
HAL_UART_MspInit(huart);
|
||||
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
||||
}
|
||||
|
||||
huart->gState = HAL_UART_STATE_BUSY;
|
||||
|
||||
/* Disable the Peripheral */
|
||||
__HAL_UART_DISABLE(huart);
|
||||
|
||||
/* Perform advanced settings configuration */
|
||||
/* For some items, configuration requires to be done prior TE and RE bits are set */
|
||||
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
||||
{
|
||||
UART_AdvFeatureConfig(huart);
|
||||
}
|
||||
|
||||
/* Set the UART Communication parameters */
|
||||
if (UART_SetConfig(huart) == HAL_ERROR)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
|
||||
SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
|
||||
|
||||
/* Set the Driver Enable polarity */
|
||||
MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
|
||||
|
||||
/* Set the Driver Enable assertion and deassertion times */
|
||||
temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
|
||||
temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
|
||||
MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
|
||||
|
||||
/* Enable the Peripheral */
|
||||
__HAL_UART_ENABLE(huart);
|
||||
|
||||
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
|
||||
return (UART_CheckIdleState(huart));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions
|
||||
* @brief Extended functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
This subsection provides a set of Wakeup and FIFO mode related callback functions.
|
||||
|
||||
#if defined(USART_CR1_UESM)
|
||||
#if defined(USART_CR3_WUFIE)
|
||||
(#) Wakeup from Stop mode Callback:
|
||||
(+) HAL_UARTEx_WakeupCallback()
|
||||
|
||||
#endif
|
||||
#endif
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(USART_CR1_UESM)
|
||||
#if defined(USART_CR3_WUFIE)
|
||||
/**
|
||||
* @brief UART wakeup from Stop mode callback.
|
||||
* @param huart UART handle.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(huart);
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_UARTEx_WakeupCallback can be implemented in the user file.
|
||||
*/
|
||||
}
|
||||
|
||||
#endif /* USART_CR3_WUFIE */
|
||||
#endif /* USART_CR1_UESM */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @brief Extended Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..] This section provides the following functions:
|
||||
(+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
|
||||
detection length to more than 4 bits for multiprocessor address mark wake up.
|
||||
#if defined(USART_CR1_UESM)
|
||||
(+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode
|
||||
trigger: address match, Start Bit detection or RXNE bit status.
|
||||
(+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
|
||||
(+) HAL_UARTEx_DisableStopMode() API disables the above functionality
|
||||
#endif
|
||||
|
||||
[..] This subsection also provides a set of additional functions providing enhanced reception
|
||||
services to user. (For example, these functions allow application to handle use cases
|
||||
where number of data to be received is unknown).
|
||||
|
||||
(#) Compared to standard reception services which only consider number of received
|
||||
data elements as reception completion criteria, these functions also consider additional events
|
||||
as triggers for updating reception status to caller :
|
||||
(+) Detection of inactivity period (RX line has not been active for a given period).
|
||||
(++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state)
|
||||
for 1 frame time, after last received byte.
|
||||
(++) RX inactivity detected by RTO, i.e. line has been in idle state
|
||||
for a programmable time, after last received byte.
|
||||
(+) Detection that a specific character has been received.
|
||||
|
||||
(#) There are two mode of transfer:
|
||||
(+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received,
|
||||
or till IDLE event occurs. Reception is handled only during function execution.
|
||||
When function exits, no data reception could occur. HAL status and number of actually received data elements,
|
||||
are returned by function after finishing transfer.
|
||||
(+) Non-Blocking mode: The reception is performed using Interrupts or DMA.
|
||||
These API's return the HAL status.
|
||||
The end of the data processing will be indicated through the
|
||||
dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode.
|
||||
The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process
|
||||
The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected.
|
||||
|
||||
(#) Blocking mode API:
|
||||
(+) HAL_UARTEx_ReceiveToIdle()
|
||||
|
||||
(#) Non-Blocking mode API with Interrupt:
|
||||
(+) HAL_UARTEx_ReceiveToIdle_IT()
|
||||
|
||||
(#) Non-Blocking mode API with DMA:
|
||||
(+) HAL_UARTEx_ReceiveToIdle_DMA()
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief By default in multiprocessor mode, when the wake up method is set
|
||||
* to address mark, the UART handles only 4-bit long addresses detection;
|
||||
* this API allows to enable longer addresses detection (6-, 7- or 8-bit
|
||||
* long).
|
||||
* @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
|
||||
* 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
|
||||
* @param huart UART handle.
|
||||
* @param AddressLength This parameter can be one of the following values:
|
||||
* @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
|
||||
* @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
|
||||
{
|
||||
/* Check the UART handle allocation */
|
||||
if (huart == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the address length parameter */
|
||||
assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
|
||||
|
||||
huart->gState = HAL_UART_STATE_BUSY;
|
||||
|
||||
/* Disable the Peripheral */
|
||||
__HAL_UART_DISABLE(huart);
|
||||
|
||||
/* Set the address length */
|
||||
MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
|
||||
|
||||
/* Enable the Peripheral */
|
||||
__HAL_UART_ENABLE(huart);
|
||||
|
||||
/* TEACK and/or REACK to check before moving huart->gState to Ready */
|
||||
return (UART_CheckIdleState(huart));
|
||||
}
|
||||
|
||||
#if defined(USART_CR1_UESM)
|
||||
/**
|
||||
* @brief Set Wakeup from Stop mode interrupt flag selection.
|
||||
* @note It is the application responsibility to enable the interrupt used as
|
||||
* usart_wkup interrupt source before entering low-power mode.
|
||||
* @param huart UART handle.
|
||||
* @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref UART_WAKEUP_ON_ADDRESS
|
||||
* @arg @ref UART_WAKEUP_ON_STARTBIT
|
||||
* @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint32_t tickstart;
|
||||
|
||||
/* check the wake-up from stop mode UART instance */
|
||||
assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
|
||||
/* check the wake-up selection parameter */
|
||||
assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(huart);
|
||||
|
||||
huart->gState = HAL_UART_STATE_BUSY;
|
||||
|
||||
/* Disable the Peripheral */
|
||||
__HAL_UART_DISABLE(huart);
|
||||
|
||||
#if defined(USART_CR3_WUS)
|
||||
/* Set the wake-up selection scheme */
|
||||
MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
|
||||
#endif /* USART_CR3_WUS */
|
||||
|
||||
if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
|
||||
{
|
||||
UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection);
|
||||
}
|
||||
|
||||
/* Enable the Peripheral */
|
||||
__HAL_UART_ENABLE(huart);
|
||||
|
||||
/* Init tickstart for timeout management */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait until REACK flag is set */
|
||||
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
||||
{
|
||||
status = HAL_TIMEOUT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Initialize the UART State */
|
||||
huart->gState = HAL_UART_STATE_READY;
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(huart);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable UART Stop Mode.
|
||||
* @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
|
||||
* @param huart UART handle.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(huart);
|
||||
|
||||
/* Set UESM bit */
|
||||
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(huart);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable UART Stop Mode.
|
||||
* @param huart UART handle.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(huart);
|
||||
|
||||
/* Clear UESM bit */
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(huart);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
#endif /* USART_CR1_UESM */
|
||||
/**
|
||||
* @brief Receive an amount of data in blocking mode till either the expected number of data
|
||||
* is received or an IDLE event occurs.
|
||||
* @note HAL_OK is returned if reception is completed (expected number of data has been received)
|
||||
* or if reception is stopped after IDLE event (less than the expected number of data has been received)
|
||||
* In this case, RxLen output parameter indicates number of data available in reception buffer.
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* the received data is handled as a set of uint16_t. In this case, Size must indicate the number
|
||||
* of uint16_t available through pData.
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* address of user data buffer for storing data to be received, should be aligned on a half word frontier
|
||||
* (16 bits) (as received data will be handled using uint16_t pointer cast). Depending on compilation chain,
|
||||
* use of specific alignment compilation directives or pragmas might be required to ensure proper
|
||||
* alignment for pData.
|
||||
* @param huart UART handle.
|
||||
* @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
|
||||
* @param Size Amount of data elements (uint8_t or uint16_t) to be received.
|
||||
* @param RxLen Number of data elements finally received
|
||||
* (could be lower than Size, in case reception ends on IDLE event)
|
||||
* @param Timeout Timeout duration expressed in ms (covers the whole reception sequence).
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
|
||||
uint32_t Timeout)
|
||||
{
|
||||
uint8_t *pdata8bits;
|
||||
uint16_t *pdata16bits;
|
||||
uint16_t uhMask;
|
||||
uint32_t tickstart;
|
||||
|
||||
/* Check that a Rx process is not already ongoing */
|
||||
if (huart->RxState == HAL_UART_STATE_READY)
|
||||
{
|
||||
if ((pData == NULL) || (Size == 0U))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
|
||||
should be aligned on a uint16_t frontier, as data to be received from RDR will be
|
||||
handled through a uint16_t cast. */
|
||||
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
||||
{
|
||||
if ((((uint32_t)pData) & 1U) != 0U)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
||||
huart->RxState = HAL_UART_STATE_BUSY_RX;
|
||||
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
|
||||
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
||||
|
||||
/* Init tickstart for timeout management */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
huart->RxXferSize = Size;
|
||||
huart->RxXferCount = Size;
|
||||
|
||||
/* Computation of UART mask to apply to RDR register */
|
||||
UART_MASK_COMPUTATION(huart);
|
||||
uhMask = huart->Mask;
|
||||
|
||||
/* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
|
||||
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
||||
{
|
||||
pdata8bits = NULL;
|
||||
pdata16bits = (uint16_t *) pData;
|
||||
}
|
||||
else
|
||||
{
|
||||
pdata8bits = pData;
|
||||
pdata16bits = NULL;
|
||||
}
|
||||
|
||||
/* Initialize output number of received elements */
|
||||
*RxLen = 0U;
|
||||
|
||||
/* as long as data have to be received */
|
||||
while (huart->RxXferCount > 0U)
|
||||
{
|
||||
/* Check if IDLE flag is set */
|
||||
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
|
||||
{
|
||||
/* Clear IDLE flag in ISR */
|
||||
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
||||
|
||||
/* If Set, but no data ever received, clear flag without exiting loop */
|
||||
/* If Set, and data has already been received, this means Idle Event is valid : End reception */
|
||||
if (*RxLen > 0U)
|
||||
{
|
||||
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
|
||||
huart->RxState = HAL_UART_STATE_READY;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
}
|
||||
|
||||
/* Check if RXNE flag is set */
|
||||
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE))
|
||||
{
|
||||
if (pdata8bits == NULL)
|
||||
{
|
||||
*pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
|
||||
pdata16bits++;
|
||||
}
|
||||
else
|
||||
{
|
||||
*pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
|
||||
pdata8bits++;
|
||||
}
|
||||
/* Increment number of received elements */
|
||||
*RxLen += 1U;
|
||||
huart->RxXferCount--;
|
||||
}
|
||||
|
||||
/* Check for the Timeout */
|
||||
if (Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
|
||||
{
|
||||
huart->RxState = HAL_UART_STATE_READY;
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Set number of received elements in output parameter : RxLen */
|
||||
*RxLen = huart->RxXferSize - huart->RxXferCount;
|
||||
/* At end of Rx process, restore huart->RxState to Ready */
|
||||
huart->RxState = HAL_UART_STATE_READY;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Receive an amount of data in interrupt mode till either the expected number of data
|
||||
* is received or an IDLE event occurs.
|
||||
* @note Reception is initiated by this function call. Further progress of reception is achieved thanks
|
||||
* to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating
|
||||
* number of received data elements.
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* the received data is handled as a set of uint16_t. In this case, Size must indicate the number
|
||||
* of uint16_t available through pData.
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* address of user data buffer for storing data to be received, should be aligned on a half word frontier
|
||||
* (16 bits) (as received data will be handled using uint16_t pointer cast). Depending on compilation chain,
|
||||
* use of specific alignment compilation directives or pragmas might be required
|
||||
* to ensure proper alignment for pData.
|
||||
* @param huart UART handle.
|
||||
* @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
|
||||
* @param Size Amount of data elements (uint8_t or uint16_t) to be received.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check that a Rx process is not already ongoing */
|
||||
if (huart->RxState == HAL_UART_STATE_READY)
|
||||
{
|
||||
if ((pData == NULL) || (Size == 0U))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
|
||||
should be aligned on a uint16_t frontier, as data to be received from RDR will be
|
||||
handled through a uint16_t cast. */
|
||||
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
||||
{
|
||||
if ((((uint32_t)pData) & 1U) != 0U)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/* Set Reception type to reception till IDLE Event*/
|
||||
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
|
||||
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
||||
|
||||
(void)UART_Start_Receive_IT(huart, pData, Size);
|
||||
|
||||
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
||||
{
|
||||
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
||||
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* In case of errors already pending when reception is started,
|
||||
Interrupts may have already been raised and lead to reception abortion.
|
||||
(Overrun error for instance).
|
||||
In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Receive an amount of data in DMA mode till either the expected number
|
||||
* of data is received or an IDLE event occurs.
|
||||
* @note Reception is initiated by this function call. Further progress of reception is achieved thanks
|
||||
* to DMA services, transferring automatically received data elements in user reception buffer and
|
||||
* calling registered callbacks at half/end of reception. UART IDLE events are also used to consider
|
||||
* reception phase as ended. In all cases, callback execution will indicate number of received data elements.
|
||||
* @note When the UART parity is enabled (PCE = 1), the received data contain
|
||||
* the parity bit (MSB position).
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* the received data is handled as a set of uint16_t. In this case, Size must indicate the number
|
||||
* of uint16_t available through pData.
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* address of user data buffer for storing data to be received, should be aligned on a half word frontier
|
||||
* (16 bits) (as received data will be handled by DMA from halfword frontier). Depending on compilation chain,
|
||||
* use of specific alignment compilation directives or pragmas might be required
|
||||
* to ensure proper alignment for pData.
|
||||
* @param huart UART handle.
|
||||
* @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
|
||||
* @param Size Amount of data elements (uint8_t or uint16_t) to be received.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
|
||||
{
|
||||
HAL_StatusTypeDef status;
|
||||
|
||||
/* Check that a Rx process is not already ongoing */
|
||||
if (huart->RxState == HAL_UART_STATE_READY)
|
||||
{
|
||||
if ((pData == NULL) || (Size == 0U))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
|
||||
should be aligned on a uint16_t frontier, as data copy from RDR will be
|
||||
handled by DMA from a uint16_t frontier. */
|
||||
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
||||
{
|
||||
if ((((uint32_t)pData) & 1U) != 0U)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/* Set Reception type to reception till IDLE Event*/
|
||||
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
|
||||
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
||||
|
||||
status = UART_Start_Receive_DMA(huart, pData, Size);
|
||||
|
||||
/* Check Rx process has been successfully started */
|
||||
if (status == HAL_OK)
|
||||
{
|
||||
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
||||
{
|
||||
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
||||
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* In case of errors already pending when reception is started,
|
||||
Interrupts may have already been raised and lead to reception abortion.
|
||||
(Overrun error for instance).
|
||||
In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Provide Rx Event type that has lead to RxEvent callback execution.
|
||||
* @note When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress
|
||||
* of reception process is provided to application through calls of Rx Event callback (either default one
|
||||
* HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event,
|
||||
* Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead
|
||||
* to Rx Event callback execution.
|
||||
* @note This function is expected to be called within the user implementation of Rx Event Callback,
|
||||
* in order to provide the accurate value :
|
||||
* In Interrupt Mode :
|
||||
* - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received)
|
||||
* - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of
|
||||
* received data is lower than expected one)
|
||||
* In DMA Mode :
|
||||
* - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received)
|
||||
* - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received
|
||||
* - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of
|
||||
* received data is lower than expected one).
|
||||
* In DMA mode, RxEvent callback could be called several times;
|
||||
* When DMA is configured in Normal Mode, HT event does not stop Reception process;
|
||||
* When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process;
|
||||
* @param huart UART handle.
|
||||
* @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values)
|
||||
*/
|
||||
HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart)
|
||||
{
|
||||
/* Return Rx Event type value, as stored in UART handle */
|
||||
return (huart->RxEventType);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup UARTEx_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
#if defined(USART_CR1_UESM)
|
||||
|
||||
/**
|
||||
* @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.
|
||||
* @param huart UART handle.
|
||||
* @param WakeUpSelection UART wake up from stop mode parameters.
|
||||
* @retval None
|
||||
*/
|
||||
static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
|
||||
{
|
||||
assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
|
||||
|
||||
/* Set the USART address length */
|
||||
MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
|
||||
|
||||
/* Set the USART address node */
|
||||
MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
|
||||
}
|
||||
#endif /* USART_CR1_UESM */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_UART_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
3291
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_usart.c
Normal file
3291
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_usart.c
Normal file
File diff suppressed because it is too large
Load Diff
137
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_usart_ex.c
Normal file
137
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_usart_ex.c
Normal file
@@ -0,0 +1,137 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_usart_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief Extended USART HAL module driver.
|
||||
* This file provides firmware functions to manage the following extended
|
||||
* functionalities of the Universal Synchronous Receiver Transmitter Peripheral (USART).
|
||||
* + Peripheral Control functions
|
||||
*
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### USART peripheral extended features #####
|
||||
==============================================================================
|
||||
|
||||
(#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
|
||||
|
||||
-@- When USART operates in FIFO mode, FIFO mode must be enabled prior
|
||||
starting RX/TX transfers. Also RX/TX FIFO thresholds must be
|
||||
configured prior starting RX/TX transfers.
|
||||
|
||||
(#) Slave mode enabling/disabling and NSS pin configuration.
|
||||
|
||||
-@- When USART operates in Slave mode, Slave mode must be enabled prior
|
||||
starting RX/TX transfers.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USARTEx USARTEx
|
||||
* @brief USART Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_USART_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup USARTEx_Exported_Functions USARTEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USARTEx_Exported_Functions_Group1 IO operation functions
|
||||
* @brief Extended USART Transmit/Receive functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
This subsection provides a set of FIFO mode related callback functions.
|
||||
|
||||
(#) TX/RX Fifos Callbacks:
|
||||
(+) HAL_USARTEx_RxFifoFullCallback()
|
||||
(+) HAL_USARTEx_TxFifoEmptyCallback()
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USARTEx_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief Extended Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..] This section provides the following functions:
|
||||
(+) HAL_USARTEx_EnableSPISlaveMode() API enables the SPI slave mode
|
||||
(+) HAL_USARTEx_DisableSPISlaveMode() API disables the SPI slave mode
|
||||
(+) HAL_USARTEx_ConfigNSS API configures the Slave Select input pin (NSS)
|
||||
(+) HAL_USARTEx_EnableFifoMode() API enables the FIFO mode
|
||||
(+) HAL_USARTEx_DisableFifoMode() API disables the FIFO mode
|
||||
(+) HAL_USARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
|
||||
(+) HAL_USARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold
|
||||
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup USARTEx_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_USART_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
420
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_wwdg.c
Normal file
420
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_wwdg.c
Normal file
@@ -0,0 +1,420 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_wwdg.c
|
||||
* @author MCD Application Team
|
||||
* @brief WWDG HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Window Watchdog (WWDG) peripheral:
|
||||
* + Initialization and Configuration functions
|
||||
* + IO operation functions
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### WWDG Specific features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
Once enabled the WWDG generates a system reset on expiry of a programmed
|
||||
time period, unless the program refreshes the counter (T[6;0] downcounter)
|
||||
before reaching 0x3F value (i.e. a reset is generated when the counter
|
||||
value rolls down from 0x40 to 0x3F).
|
||||
|
||||
(+) An MCU reset is also generated if the counter value is refreshed
|
||||
before the counter has reached the refresh window value. This
|
||||
implies that the counter must be refreshed in a limited window.
|
||||
(+) Once enabled the WWDG cannot be disabled except by a system reset.
|
||||
(+) If required by application, an Early Wakeup Interrupt can be triggered
|
||||
in order to be warned before WWDG expiration. The Early Wakeup Interrupt
|
||||
(EWI) can be used if specific safety operations or data logging must
|
||||
be performed before the actual reset is generated. When the downcounter
|
||||
reaches 0x40, interrupt occurs. This mechanism requires WWDG interrupt
|
||||
line to be enabled in NVIC. Once enabled, EWI interrupt cannot be
|
||||
disabled except by a system reset.
|
||||
(+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG
|
||||
reset occurs.
|
||||
(+) The WWDG counter input clock is derived from the APB clock divided
|
||||
by a programmable prescaler.
|
||||
(+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
|
||||
(+) WWDG timeout (mS) = 1000 * (T[5;0] + 1) / WWDG clock (Hz)
|
||||
where T[5;0] are the lowest 6 bits of Counter.
|
||||
(+) WWDG Counter refresh is allowed between the following limits :
|
||||
(++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
|
||||
(++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
|
||||
(+) Typical values:
|
||||
(++) Counter min (T[5;0] = 0x00) at 48MHz (PCLK1) with zero prescaler:
|
||||
max timeout before reset: approximately 85.3us
|
||||
(++) Counter max (T[5;0] = 0x3F) at 48MHz (PCLK1) with prescaler
|
||||
dividing by 8:
|
||||
max timeout before reset: approximately 43.7ms
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
|
||||
*** Common driver usage ***
|
||||
===========================
|
||||
|
||||
[..]
|
||||
(+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
|
||||
(+) Configure the WWDG prescaler, refresh window value, counter value and early
|
||||
interrupt status using HAL_WWDG_Init() function. This will automatically
|
||||
enable WWDG and start its downcounter. Time reference can be taken from
|
||||
function exit. Care must be taken to provide a counter value
|
||||
greater than 0x40 to prevent generation of immediate reset.
|
||||
(+) If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is
|
||||
generated when the counter reaches 0x40. When HAL_WWDG_IRQHandler is
|
||||
triggered by the interrupt service routine, flag will be automatically
|
||||
cleared and HAL_WWDG_WakeupCallback user callback will be executed. User
|
||||
can add his own code by customization of callback HAL_WWDG_WakeupCallback.
|
||||
(+) Then the application program must refresh the WWDG counter at regular
|
||||
intervals during normal operation to prevent an MCU reset, using
|
||||
HAL_WWDG_Refresh() function. This operation must occur only when
|
||||
the counter is lower than the refresh window value already programmed.
|
||||
|
||||
*** Callback registration ***
|
||||
=============================
|
||||
|
||||
[..]
|
||||
The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
|
||||
the user to configure dynamically the driver callbacks. Use Functions
|
||||
HAL_WWDG_RegisterCallback() to register a user callback.
|
||||
|
||||
(+) Function HAL_WWDG_RegisterCallback() allows to register following
|
||||
callbacks:
|
||||
(++) EwiCallback : callback for Early WakeUp Interrupt.
|
||||
(++) MspInitCallback : WWDG MspInit.
|
||||
This function takes as parameters the HAL peripheral handle, the Callback ID
|
||||
and a pointer to the user callback function.
|
||||
|
||||
(+) Use function HAL_WWDG_UnRegisterCallback() to reset a callback to
|
||||
the default weak (surcharged) function. HAL_WWDG_UnRegisterCallback()
|
||||
takes as parameters the HAL peripheral handle and the Callback ID.
|
||||
This function allows to reset following callbacks:
|
||||
(++) EwiCallback : callback for Early WakeUp Interrupt.
|
||||
(++) MspInitCallback : WWDG MspInit.
|
||||
|
||||
[..]
|
||||
When calling HAL_WWDG_Init function, callbacks are reset to the
|
||||
corresponding legacy weak (surcharged) functions:
|
||||
HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have
|
||||
not been registered before.
|
||||
|
||||
[..]
|
||||
When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or
|
||||
not defined, the callback registering feature is not available
|
||||
and weak (surcharged) callbacks are used.
|
||||
|
||||
*** WWDG HAL driver macros list ***
|
||||
===================================
|
||||
[..]
|
||||
Below the list of available macros in WWDG HAL driver.
|
||||
(+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
|
||||
(+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
|
||||
(+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
|
||||
(+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt
|
||||
|
||||
@endverbatim
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_WWDG_MODULE_ENABLED
|
||||
/** @defgroup WWDG WWDG
|
||||
* @brief WWDG HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup WWDG_Exported_Functions WWDG Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions
|
||||
* @brief Initialization and Configuration functions.
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Initialization and Configuration functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This section provides functions allowing to:
|
||||
(+) Initialize and start the WWDG according to the specified parameters
|
||||
in the WWDG_InitTypeDef of associated handle.
|
||||
(+) Initialize the WWDG MSP.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initialize the WWDG according to the specified.
|
||||
* parameters in the WWDG_InitTypeDef of associated handle.
|
||||
* @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified WWDG module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
|
||||
{
|
||||
/* Check the WWDG handle allocation */
|
||||
if (hwwdg == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
|
||||
assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
|
||||
assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
|
||||
assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
|
||||
assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));
|
||||
|
||||
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
|
||||
/* Reset Callback pointers */
|
||||
if (hwwdg->EwiCallback == NULL)
|
||||
{
|
||||
hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
|
||||
}
|
||||
|
||||
if (hwwdg->MspInitCallback == NULL)
|
||||
{
|
||||
hwwdg->MspInitCallback = HAL_WWDG_MspInit;
|
||||
}
|
||||
|
||||
/* Init the low level hardware */
|
||||
hwwdg->MspInitCallback(hwwdg);
|
||||
#else
|
||||
/* Init the low level hardware */
|
||||
HAL_WWDG_MspInit(hwwdg);
|
||||
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
|
||||
|
||||
/* Set WWDG Counter */
|
||||
WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
|
||||
|
||||
/* Set WWDG Prescaler and Window */
|
||||
WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window));
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initialize the WWDG MSP.
|
||||
* @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified WWDG module.
|
||||
* @note When rewriting this function in user file, mechanism may be added
|
||||
* to avoid multiple initialize when HAL_WWDG_Init function is called
|
||||
* again to change parameters.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hwwdg);
|
||||
|
||||
/* NOTE: This function should not be modified, when the callback is needed,
|
||||
the HAL_WWDG_MspInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
|
||||
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief Register a User WWDG Callback
|
||||
* To be used instead of the weak (surcharged) predefined callback
|
||||
* @param hwwdg WWDG handle
|
||||
* @param CallbackID ID of the callback to be registered
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
|
||||
* @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
|
||||
* @param pCallback pointer to the Callback function
|
||||
* @retval status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
|
||||
pWWDG_CallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
if (pCallback == NULL)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_WWDG_EWI_CB_ID:
|
||||
hwwdg->EwiCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_WWDG_MSPINIT_CB_ID:
|
||||
hwwdg->MspInitCallback = pCallback;
|
||||
break;
|
||||
|
||||
default:
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Unregister a WWDG Callback
|
||||
* WWDG Callback is redirected to the weak (surcharged) predefined callback
|
||||
* @param hwwdg WWDG handle
|
||||
* @param CallbackID ID of the callback to be registered
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
|
||||
* @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
|
||||
* @retval status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_WWDG_EWI_CB_ID:
|
||||
hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
|
||||
break;
|
||||
|
||||
case HAL_WWDG_MSPINIT_CB_ID:
|
||||
hwwdg->MspInitCallback = HAL_WWDG_MspInit;
|
||||
break;
|
||||
|
||||
default:
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
|
||||
* @brief IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### IO operation functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This section provides functions allowing to:
|
||||
(+) Refresh the WWDG.
|
||||
(+) Handle WWDG interrupt request and associated function callback.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Refresh the WWDG.
|
||||
* @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified WWDG module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg)
|
||||
{
|
||||
/* Write to WWDG CR the WWDG Counter value to refresh with */
|
||||
WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter));
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handle WWDG interrupt request.
|
||||
* @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations
|
||||
* or data logging must be performed before the actual reset is generated.
|
||||
* The EWI interrupt is enabled by calling HAL_WWDG_Init function with
|
||||
* EWIMode set to WWDG_EWI_ENABLE.
|
||||
* When the downcounter reaches the value 0x40, and EWI interrupt is
|
||||
* generated and the corresponding Interrupt Service Routine (ISR) can
|
||||
* be used to trigger specific actions (such as communications or data
|
||||
* logging), before resetting the device.
|
||||
* @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified WWDG module.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
|
||||
{
|
||||
/* Check if Early Wakeup Interrupt is enable */
|
||||
if (__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
|
||||
{
|
||||
/* Check if WWDG Early Wakeup Interrupt occurred */
|
||||
if (__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
|
||||
{
|
||||
/* Clear the WWDG Early Wakeup flag */
|
||||
__HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
|
||||
|
||||
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
|
||||
/* Early Wakeup registered callback */
|
||||
hwwdg->EwiCallback(hwwdg);
|
||||
#else
|
||||
/* Early Wakeup callback */
|
||||
HAL_WWDG_EarlyWakeupCallback(hwwdg);
|
||||
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief WWDG Early Wakeup callback.
|
||||
* @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified WWDG module.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hwwdg);
|
||||
|
||||
/* NOTE: This function should not be modified, when the callback is needed,
|
||||
the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_WWDG_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
557
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_adc.c
Normal file
557
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_adc.c
Normal file
@@ -0,0 +1,557 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_ll_adc.c
|
||||
* @author MCD Application Team
|
||||
* @brief ADC LL module driver
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_ll_adc.h"
|
||||
#include "stm32f0xx_ll_bus.h"
|
||||
|
||||
#ifdef USE_FULL_ASSERT
|
||||
#include "stm32_assert.h"
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32F0xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (ADC1)
|
||||
|
||||
/** @addtogroup ADC_LL ADC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @addtogroup ADC_LL_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Definitions of ADC hardware constraints delays */
|
||||
/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
|
||||
/* not timeout values: */
|
||||
/* Timeout values for ADC operations are dependent to device clock */
|
||||
/* configuration (system clock versus ADC clock), */
|
||||
/* and therefore must be defined in user application. */
|
||||
/* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
|
||||
/* values definition. */
|
||||
/* Note: ADC timeout values are defined here in CPU cycles to be independent */
|
||||
/* of device clock setting. */
|
||||
/* In user application, ADC timeout values should be defined with */
|
||||
/* temporal values, in function of device clock settings. */
|
||||
/* Highest ratio CPU clock frequency vs ADC clock frequency: */
|
||||
/* - ADC clock from synchronous clock with AHB prescaler 512, */
|
||||
/* APB prescaler 16, ADC prescaler 4. */
|
||||
/* - ADC clock from asynchronous clock (HSI) with prescaler 1, */
|
||||
/* with highest ratio CPU clock frequency vs HSI clock frequency: */
|
||||
/* CPU clock frequency max 48MHz, HSI frequency 14MHz: ratio 4. */
|
||||
/* Unit: CPU cycles. */
|
||||
#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST ((uint32_t) 512U * 16U * 4U)
|
||||
#define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
|
||||
#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup ADC_LL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Check of parameters for configuration of ADC hierarchical scope: */
|
||||
/* common to several ADC instances. */
|
||||
/* Check of parameters for configuration of ADC hierarchical scope: */
|
||||
/* ADC instance. */
|
||||
#define IS_LL_ADC_CLOCK(__CLOCK__) \
|
||||
( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
|
||||
|| ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
|
||||
|| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC) \
|
||||
)
|
||||
|
||||
#define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
|
||||
( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
|
||||
|| ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
|
||||
|| ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
|
||||
|| ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
|
||||
)
|
||||
|
||||
#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
|
||||
( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
|
||||
|| ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
|
||||
)
|
||||
|
||||
#define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
|
||||
( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
|
||||
|| ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
|
||||
|| ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF) \
|
||||
|| ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF) \
|
||||
)
|
||||
|
||||
/* Check of parameters for configuration of ADC hierarchical scope: */
|
||||
/* ADC group regular */
|
||||
#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
|
||||
( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
|
||||
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
|
||||
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4) \
|
||||
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
|
||||
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
|
||||
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
|
||||
)
|
||||
|
||||
#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
|
||||
( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
|
||||
|| ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
|
||||
)
|
||||
|
||||
#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
|
||||
( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
|
||||
|| ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
|
||||
|| ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
|
||||
)
|
||||
|
||||
#define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
|
||||
( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
|
||||
|| ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
|
||||
)
|
||||
|
||||
#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
|
||||
( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
|
||||
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
|
||||
)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup ADC_LL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_LL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief De-initialize registers of all ADC instances belonging to
|
||||
* the same ADC common instance to their default reset values.
|
||||
* @note This function is performing a hard reset, using high level
|
||||
* clock source RCC ADC reset.
|
||||
* @param ADCxy_COMMON ADC common instance
|
||||
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: ADC common registers are de-initialized
|
||||
* - ERROR: not applicable
|
||||
*/
|
||||
ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
|
||||
|
||||
/* Force reset of ADC clock (core clock) */
|
||||
LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_ADC1);
|
||||
|
||||
/* Release reset of ADC clock (core clock) */
|
||||
LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_ADC1);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief De-initialize registers of the selected ADC instance
|
||||
* to their default reset values.
|
||||
* @note To reset all ADC instances quickly (perform a hard reset),
|
||||
* use function @ref LL_ADC_CommonDeInit().
|
||||
* @note If this functions returns error status, it means that ADC instance
|
||||
* is in an unknown state.
|
||||
* In this case, perform a hard reset using high level
|
||||
* clock source RCC ADC reset.
|
||||
* Refer to function @ref LL_ADC_CommonDeInit().
|
||||
* @param ADCx ADC instance
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: ADC registers are de-initialized
|
||||
* - ERROR: ADC registers are not de-initialized
|
||||
*/
|
||||
ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
|
||||
__IO uint32_t timeout_cpu_cycles = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_ALL_INSTANCE(ADCx));
|
||||
|
||||
/* Disable ADC instance if not already disabled. */
|
||||
if(LL_ADC_IsEnabled(ADCx) == 1U)
|
||||
{
|
||||
/* Stop potential ADC conversion on going on ADC group regular. */
|
||||
if(LL_ADC_REG_IsConversionOngoing(ADCx) != 0U)
|
||||
{
|
||||
if(LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0U)
|
||||
{
|
||||
LL_ADC_REG_StopConversion(ADCx);
|
||||
}
|
||||
}
|
||||
|
||||
/* Wait for ADC conversions are effectively stopped */
|
||||
timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
|
||||
while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1UL)
|
||||
{
|
||||
timeout_cpu_cycles--;
|
||||
if (timeout_cpu_cycles == 0UL)
|
||||
{
|
||||
/* Time-out error */
|
||||
status = ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Disable the ADC instance */
|
||||
LL_ADC_Disable(ADCx);
|
||||
|
||||
/* Wait for ADC instance is effectively disabled */
|
||||
timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
|
||||
while (LL_ADC_IsDisableOngoing(ADCx) == 1U)
|
||||
{
|
||||
if(timeout_cpu_cycles-- == 0U)
|
||||
{
|
||||
/* Time-out error */
|
||||
status = ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/* Check whether ADC state is compliant with expected state */
|
||||
if(READ_BIT(ADCx->CR,
|
||||
( ADC_CR_ADSTP | ADC_CR_ADSTART
|
||||
| ADC_CR_ADDIS | ADC_CR_ADEN )
|
||||
)
|
||||
== 0U)
|
||||
{
|
||||
/* ========== Reset ADC registers ========== */
|
||||
/* Reset register IER */
|
||||
CLEAR_BIT(ADCx->IER,
|
||||
( LL_ADC_IT_ADRDY
|
||||
| LL_ADC_IT_EOC
|
||||
| LL_ADC_IT_EOS
|
||||
| LL_ADC_IT_OVR
|
||||
| LL_ADC_IT_EOSMP
|
||||
| LL_ADC_IT_AWD1 )
|
||||
);
|
||||
|
||||
/* Reset register ISR */
|
||||
SET_BIT(ADCx->ISR,
|
||||
( LL_ADC_FLAG_ADRDY
|
||||
| LL_ADC_FLAG_EOC
|
||||
| LL_ADC_FLAG_EOS
|
||||
| LL_ADC_FLAG_OVR
|
||||
| LL_ADC_FLAG_EOSMP
|
||||
| LL_ADC_FLAG_AWD1 )
|
||||
);
|
||||
|
||||
/* Reset register CR */
|
||||
/* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
|
||||
/* "read-set": no direct reset applicable. */
|
||||
/* No action on register CR */
|
||||
|
||||
/* Reset register CFGR1 */
|
||||
CLEAR_BIT(ADCx->CFGR1,
|
||||
( ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_DISCEN
|
||||
| ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD
|
||||
| ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES
|
||||
| ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN )
|
||||
);
|
||||
|
||||
/* Reset register CFGR2 */
|
||||
/* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
|
||||
/* already done above. */
|
||||
CLEAR_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE);
|
||||
|
||||
/* Reset register SMPR */
|
||||
CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP);
|
||||
|
||||
/* Reset register TR */
|
||||
MODIFY_REG(ADCx->TR, ADC_TR_HT | ADC_TR_LT, ADC_TR_HT);
|
||||
|
||||
/* Reset register CHSELR */
|
||||
#if defined(ADC_CCR_VBATEN)
|
||||
CLEAR_BIT(ADCx->CHSELR,
|
||||
( ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16
|
||||
| ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12
|
||||
| ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8
|
||||
| ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4
|
||||
| ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0 )
|
||||
);
|
||||
#else
|
||||
CLEAR_BIT(ADCx->CHSELR,
|
||||
( ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16
|
||||
| ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12
|
||||
| ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8
|
||||
| ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4
|
||||
| ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0 )
|
||||
);
|
||||
#endif
|
||||
|
||||
/* Reset register DR */
|
||||
/* bits in access mode read only, no direct reset applicable */
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
/* ADC instance is in an unknown state */
|
||||
/* Need to performing a hard reset of ADC instance, using high level */
|
||||
/* clock source RCC ADC reset. */
|
||||
/* Caution: On this STM32 series, if several ADC instances are available */
|
||||
/* on the selected device, RCC ADC reset will reset */
|
||||
/* all ADC instances belonging to the common ADC instance. */
|
||||
status = ERROR;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize some features of ADC instance.
|
||||
* @note These parameters have an impact on ADC scope: ADC instance.
|
||||
* Refer to corresponding unitary functions into
|
||||
* @ref ADC_LL_EF_Configuration_ADC_Instance .
|
||||
* @note The setting of these parameters by function @ref LL_ADC_Init()
|
||||
* is conditioned to ADC state:
|
||||
* ADC instance must be disabled.
|
||||
* This condition is applied to all ADC features, for efficiency
|
||||
* and compatibility over all STM32 families. However, the different
|
||||
* features can be set under different ADC state conditions
|
||||
* (setting possible with ADC enabled without conversion on going,
|
||||
* ADC enabled with conversion on going, ...)
|
||||
* Each feature can be updated afterwards with a unitary function
|
||||
* and potentially with ADC in a different state than disabled,
|
||||
* refer to description of each function for setting
|
||||
* conditioned to ADC state.
|
||||
* @note After using this function, some other features must be configured
|
||||
* using LL unitary functions.
|
||||
* The minimum configuration remaining to be done is:
|
||||
* - Set ADC group regular sequencer:
|
||||
* map channel on rank corresponding to channel number.
|
||||
* Refer to function @ref LL_ADC_REG_SetSequencerChannels();
|
||||
* - Set ADC channel sampling time
|
||||
* Refer to function LL_ADC_SetChannelSamplingTime();
|
||||
* @param ADCx ADC instance
|
||||
* @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: ADC registers are initialized
|
||||
* - ERROR: ADC registers are not initialized
|
||||
*/
|
||||
ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_ALL_INSTANCE(ADCx));
|
||||
|
||||
assert_param(IS_LL_ADC_CLOCK(ADC_InitStruct->Clock));
|
||||
assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
|
||||
assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
|
||||
assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
|
||||
|
||||
/* Note: Hardware constraint (refer to description of this function): */
|
||||
/* ADC instance must be disabled. */
|
||||
if(LL_ADC_IsEnabled(ADCx) == 0U)
|
||||
{
|
||||
/* Configuration of ADC hierarchical scope: */
|
||||
/* - ADC instance */
|
||||
/* - Set ADC data resolution */
|
||||
/* - Set ADC conversion data alignment */
|
||||
/* - Set ADC low power mode */
|
||||
MODIFY_REG(ADCx->CFGR1,
|
||||
ADC_CFGR1_RES
|
||||
| ADC_CFGR1_ALIGN
|
||||
| ADC_CFGR1_WAIT
|
||||
| ADC_CFGR1_AUTOFF
|
||||
,
|
||||
ADC_InitStruct->Resolution
|
||||
| ADC_InitStruct->DataAlignment
|
||||
| ADC_InitStruct->LowPowerMode
|
||||
);
|
||||
|
||||
MODIFY_REG(ADCx->CFGR2,
|
||||
ADC_CFGR2_CKMODE
|
||||
,
|
||||
ADC_InitStruct->Clock
|
||||
);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Initialization error: ADC instance is not disabled. */
|
||||
status = ERROR;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set each @ref LL_ADC_InitTypeDef field to default value.
|
||||
* @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
|
||||
* whose fields will be set to default values.
|
||||
* @retval None
|
||||
*/
|
||||
void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
|
||||
{
|
||||
/* Set ADC_InitStruct fields to default values */
|
||||
/* Set fields of ADC instance */
|
||||
ADC_InitStruct->Clock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
|
||||
ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
|
||||
ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
|
||||
ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize some features of ADC group regular.
|
||||
* @note These parameters have an impact on ADC scope: ADC group regular.
|
||||
* Refer to corresponding unitary functions into
|
||||
* @ref ADC_LL_EF_Configuration_ADC_Group_Regular
|
||||
* (functions with prefix "REG").
|
||||
* @note The setting of these parameters by function @ref LL_ADC_Init()
|
||||
* is conditioned to ADC state:
|
||||
* ADC instance must be disabled.
|
||||
* This condition is applied to all ADC features, for efficiency
|
||||
* and compatibility over all STM32 families. However, the different
|
||||
* features can be set under different ADC state conditions
|
||||
* (setting possible with ADC enabled without conversion on going,
|
||||
* ADC enabled with conversion on going, ...)
|
||||
* Each feature can be updated afterwards with a unitary function
|
||||
* and potentially with ADC in a different state than disabled,
|
||||
* refer to description of each function for setting
|
||||
* conditioned to ADC state.
|
||||
* @note After using this function, other features must be configured
|
||||
* using LL unitary functions.
|
||||
* The minimum configuration remaining to be done is:
|
||||
* - Set ADC group regular sequencer:
|
||||
* map channel on rank corresponding to channel number.
|
||||
* Refer to function @ref LL_ADC_REG_SetSequencerChannels();
|
||||
* - Set ADC channel sampling time
|
||||
* Refer to function LL_ADC_SetChannelSamplingTime();
|
||||
* @param ADCx ADC instance
|
||||
* @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: ADC registers are initialized
|
||||
* - ERROR: ADC registers are not initialized
|
||||
*/
|
||||
ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_ALL_INSTANCE(ADCx));
|
||||
assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
|
||||
assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
|
||||
assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
|
||||
assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
|
||||
assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
|
||||
|
||||
/* ADC group regular continuous mode and discontinuous mode */
|
||||
/* can not be enabled simultenaeously */
|
||||
assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
|
||||
|| (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
|
||||
|
||||
/* Note: Hardware constraint (refer to description of this function): */
|
||||
/* ADC instance must be disabled. */
|
||||
if(LL_ADC_IsEnabled(ADCx) == 0U)
|
||||
{
|
||||
/* Configuration of ADC hierarchical scope: */
|
||||
/* - ADC group regular */
|
||||
/* - Set ADC group regular trigger source */
|
||||
/* - Set ADC group regular sequencer discontinuous mode */
|
||||
/* - Set ADC group regular continuous mode */
|
||||
/* - Set ADC group regular conversion data transfer: no transfer or */
|
||||
/* transfer by DMA, and DMA requests mode */
|
||||
/* - Set ADC group regular overrun behavior */
|
||||
/* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
|
||||
/* setting of trigger source to SW start. */
|
||||
MODIFY_REG(ADCx->CFGR1,
|
||||
ADC_CFGR1_EXTSEL
|
||||
| ADC_CFGR1_EXTEN
|
||||
| ADC_CFGR1_DISCEN
|
||||
| ADC_CFGR1_CONT
|
||||
| ADC_CFGR1_DMAEN
|
||||
| ADC_CFGR1_DMACFG
|
||||
| ADC_CFGR1_OVRMOD
|
||||
,
|
||||
ADC_REG_InitStruct->TriggerSource
|
||||
| ADC_REG_InitStruct->SequencerDiscont
|
||||
| ADC_REG_InitStruct->ContinuousMode
|
||||
| ADC_REG_InitStruct->DMATransfer
|
||||
| ADC_REG_InitStruct->Overrun
|
||||
);
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Initialization error: ADC instance is not disabled. */
|
||||
status = ERROR;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
|
||||
* @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
|
||||
* whose fields will be set to default values.
|
||||
* @retval None
|
||||
*/
|
||||
void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
|
||||
{
|
||||
/* Set ADC_REG_InitStruct fields to default values */
|
||||
/* Set fields of ADC group regular */
|
||||
/* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
|
||||
/* setting of trigger source to SW start. */
|
||||
ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
|
||||
ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
|
||||
ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
|
||||
ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
|
||||
ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* ADC1 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
314
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_comp.c
Normal file
314
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_comp.c
Normal file
@@ -0,0 +1,314 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_ll_comp.c
|
||||
* @author MCD Application Team
|
||||
* @brief COMP LL module driver
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_ll_comp.h"
|
||||
|
||||
#ifdef USE_FULL_ASSERT
|
||||
#include "stm32_assert.h"
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32F0xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (COMP1) || defined (COMP2)
|
||||
|
||||
/** @addtogroup COMP_LL COMP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup COMP_LL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Check of parameters for configuration of COMP hierarchical scope: */
|
||||
/* COMP instance. */
|
||||
|
||||
#define IS_LL_COMP_POWER_MODE(__POWER_MODE__) \
|
||||
( ((__POWER_MODE__) == LL_COMP_POWERMODE_HIGHSPEED) \
|
||||
|| ((__POWER_MODE__) == LL_COMP_POWERMODE_MEDIUMSPEED) \
|
||||
|| ((__POWER_MODE__) == LL_COMP_POWERMODE_LOWPOWER) \
|
||||
|| ((__POWER_MODE__) == LL_COMP_POWERMODE_ULTRALOWPOWER) \
|
||||
)
|
||||
|
||||
/* Note: On this STM32 series, comparator input plus parameters are */
|
||||
/* the different depending on COMP instances. */
|
||||
#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \
|
||||
(((__COMP_INSTANCE__) == COMP1) \
|
||||
? ( \
|
||||
((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \
|
||||
|| ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_DAC1_CH1) \
|
||||
) \
|
||||
: \
|
||||
( \
|
||||
((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \
|
||||
) \
|
||||
)
|
||||
|
||||
/* Note: On this STM32 series, comparator input minus parameters are */
|
||||
/* the same on all COMP instances. */
|
||||
/* However, comparator instance kept as macro parameter for */
|
||||
/* compatibility with other STM32 families. */
|
||||
#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \
|
||||
( ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \
|
||||
|| ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \
|
||||
|| ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) \
|
||||
|| ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) \
|
||||
|| ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) \
|
||||
|| ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2) \
|
||||
|| ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) \
|
||||
)
|
||||
|
||||
#define IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__) \
|
||||
( ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE) \
|
||||
|| ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_LOW) \
|
||||
|| ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_MEDIUM) \
|
||||
|| ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_HIGH) \
|
||||
)
|
||||
|
||||
#define IS_LL_COMP_OUTPUT_SELECTION(__OUTPUT_SELECTION__) \
|
||||
( ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_NONE) \
|
||||
|| ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN) \
|
||||
|| ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC1) \
|
||||
|| ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR) \
|
||||
|| ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC4) \
|
||||
|| ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR) \
|
||||
|| ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC1) \
|
||||
|| ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR) \
|
||||
)
|
||||
|
||||
#define IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__) \
|
||||
( ((__POLARITY__) == LL_COMP_OUTPUTPOL_NONINVERTED) \
|
||||
|| ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED) \
|
||||
)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup COMP_LL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup COMP_LL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief De-initialize registers of the selected COMP instance
|
||||
* to their default reset values.
|
||||
* @note If comparator is locked, de-initialization by software is
|
||||
* not possible.
|
||||
* The only way to unlock the comparator is a device hardware reset.
|
||||
* @param COMPx COMP instance
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: COMP registers are de-initialized
|
||||
* - ERROR: COMP registers are not de-initialized
|
||||
*/
|
||||
ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(COMPx));
|
||||
|
||||
/* Note: Hardware constraint (refer to description of this function): */
|
||||
/* COMP instance must not be locked. */
|
||||
if(LL_COMP_IsLocked(COMPx) == 0U)
|
||||
{
|
||||
/* Note: Connection switch is applicable only to COMP instance COMP1, */
|
||||
/* therefore is COMP2 is selected the equivalent bit is */
|
||||
/* kept unmodified. */
|
||||
if(COMPx == COMP1)
|
||||
{
|
||||
CLEAR_BIT(COMP->CSR,
|
||||
( COMP_CSR_COMP1MODE
|
||||
| COMP_CSR_COMP1INSEL
|
||||
| COMP_CSR_COMP1SW1
|
||||
| COMP_CSR_COMP1OUTSEL
|
||||
| COMP_CSR_COMP1HYST
|
||||
| COMP_CSR_COMP1POL
|
||||
| COMP_CSR_COMP1EN
|
||||
) << __COMP_BITOFFSET_INSTANCE(COMPx)
|
||||
);
|
||||
}
|
||||
else
|
||||
{
|
||||
CLEAR_BIT(COMP->CSR,
|
||||
( COMP_CSR_COMP1MODE
|
||||
| COMP_CSR_COMP1INSEL
|
||||
| COMP_CSR_COMP1OUTSEL
|
||||
| COMP_CSR_COMP1HYST
|
||||
| COMP_CSR_COMP1POL
|
||||
| COMP_CSR_COMP1EN
|
||||
) << __COMP_BITOFFSET_INSTANCE(COMPx)
|
||||
);
|
||||
}
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Comparator instance is locked: de-initialization by software is */
|
||||
/* not possible. */
|
||||
/* The only way to unlock the comparator is a device hardware reset. */
|
||||
status = ERROR;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize some features of COMP instance.
|
||||
* @note This function configures features of the selected COMP instance.
|
||||
* Some features are also available at scope COMP common instance
|
||||
* (common to several COMP instances).
|
||||
* Refer to functions having argument "COMPxy_COMMON" as parameter.
|
||||
* @param COMPx COMP instance
|
||||
* @param COMP_InitStruct Pointer to a @ref LL_COMP_InitTypeDef structure
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: COMP registers are initialized
|
||||
* - ERROR: COMP registers are not initialized
|
||||
*/
|
||||
ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(COMPx));
|
||||
assert_param(IS_LL_COMP_POWER_MODE(COMP_InitStruct->PowerMode));
|
||||
assert_param(IS_LL_COMP_INPUT_PLUS(COMPx, COMP_InitStruct->InputPlus));
|
||||
assert_param(IS_LL_COMP_INPUT_MINUS(COMPx, COMP_InitStruct->InputMinus));
|
||||
assert_param(IS_LL_COMP_INPUT_HYSTERESIS(COMP_InitStruct->InputHysteresis));
|
||||
assert_param(IS_LL_COMP_OUTPUT_SELECTION(COMP_InitStruct->OutputSelection));
|
||||
assert_param(IS_LL_COMP_OUTPUT_POLARITY(COMP_InitStruct->OutputPolarity));
|
||||
|
||||
/* Note: Hardware constraint (refer to description of this function) */
|
||||
/* COMP instance must not be locked. */
|
||||
if(LL_COMP_IsLocked(COMPx) == 0U)
|
||||
{
|
||||
/* Configuration of comparator instance : */
|
||||
/* - PowerMode */
|
||||
/* - InputPlus */
|
||||
/* - InputMinus */
|
||||
/* - InputHysteresis */
|
||||
/* - OutputSelection */
|
||||
/* - OutputPolarity */
|
||||
/* Note: Connection switch is applicable only to COMP instance COMP1, */
|
||||
/* therefore is COMP2 is selected the equivalent bit is */
|
||||
/* kept unmodified. */
|
||||
if(COMPx == COMP1)
|
||||
{
|
||||
MODIFY_REG(COMP->CSR,
|
||||
( COMP_CSR_COMP1MODE
|
||||
| COMP_CSR_COMP1INSEL
|
||||
| COMP_CSR_COMP1SW1
|
||||
| COMP_CSR_COMP1OUTSEL
|
||||
| COMP_CSR_COMP1HYST
|
||||
| COMP_CSR_COMP1POL
|
||||
) << __COMP_BITOFFSET_INSTANCE(COMPx)
|
||||
,
|
||||
( COMP_InitStruct->PowerMode
|
||||
| COMP_InitStruct->InputPlus
|
||||
| COMP_InitStruct->InputMinus
|
||||
| COMP_InitStruct->InputHysteresis
|
||||
| COMP_InitStruct->OutputSelection
|
||||
| COMP_InitStruct->OutputPolarity
|
||||
) << __COMP_BITOFFSET_INSTANCE(COMPx)
|
||||
);
|
||||
}
|
||||
else
|
||||
{
|
||||
MODIFY_REG(COMP->CSR,
|
||||
( COMP_CSR_COMP1MODE
|
||||
| COMP_CSR_COMP1INSEL
|
||||
| COMP_CSR_COMP1OUTSEL
|
||||
| COMP_CSR_COMP1HYST
|
||||
| COMP_CSR_COMP1POL
|
||||
) << __COMP_BITOFFSET_INSTANCE(COMPx)
|
||||
,
|
||||
( COMP_InitStruct->PowerMode
|
||||
| COMP_InitStruct->InputPlus
|
||||
| COMP_InitStruct->InputMinus
|
||||
| COMP_InitStruct->InputHysteresis
|
||||
| COMP_InitStruct->OutputSelection
|
||||
| COMP_InitStruct->OutputPolarity
|
||||
) << __COMP_BITOFFSET_INSTANCE(COMPx)
|
||||
);
|
||||
}
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Initialization error: COMP instance is locked. */
|
||||
status = ERROR;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set each @ref LL_COMP_InitTypeDef field to default value.
|
||||
* @param COMP_InitStruct pointer to a @ref LL_COMP_InitTypeDef structure
|
||||
* whose fields will be set to default values.
|
||||
* @retval None
|
||||
*/
|
||||
void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct)
|
||||
{
|
||||
/* Set COMP_InitStruct fields to default values */
|
||||
COMP_InitStruct->PowerMode = LL_COMP_POWERMODE_ULTRALOWPOWER;
|
||||
COMP_InitStruct->InputPlus = LL_COMP_INPUT_PLUS_IO1;
|
||||
COMP_InitStruct->InputMinus = LL_COMP_INPUT_MINUS_VREFINT;
|
||||
COMP_InitStruct->InputHysteresis = LL_COMP_HYSTERESIS_NONE;
|
||||
COMP_InitStruct->OutputSelection = LL_COMP_OUTPUT_NONE;
|
||||
COMP_InitStruct->OutputPolarity = LL_COMP_OUTPUTPOL_NONINVERTED;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* COMP1 || COMP2 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
118
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_crc.c
Normal file
118
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_crc.c
Normal file
@@ -0,0 +1,118 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_ll_crc.c
|
||||
* @author MCD Application Team
|
||||
* @brief CRC LL module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_ll_crc.h"
|
||||
#include "stm32f0xx_ll_bus.h"
|
||||
|
||||
#ifdef USE_FULL_ASSERT
|
||||
#include "stm32_assert.h"
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
/** @addtogroup STM32F0xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (CRC)
|
||||
|
||||
/** @addtogroup CRC_LL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup CRC_LL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC_LL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief De-initialize CRC registers (Registers restored to their default values).
|
||||
* @param CRCx CRC Instance
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: CRC registers are de-initialized
|
||||
* - ERROR: CRC registers are not de-initialized
|
||||
*/
|
||||
ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CRC_ALL_INSTANCE(CRCx));
|
||||
|
||||
if (CRCx == CRC)
|
||||
{
|
||||
#if defined(CRC_POL_POL)
|
||||
/* Set programmable polynomial size in CR register to reset value (32 bits)*/
|
||||
LL_CRC_SetPolynomialSize(CRCx, LL_CRC_POLYLENGTH_32B);
|
||||
|
||||
/* Set programmable polynomial in POL register to reset value */
|
||||
LL_CRC_SetPolynomialCoef(CRCx, LL_CRC_DEFAULT_CRC32_POLY);
|
||||
#endif /* CRC_POL_POL */
|
||||
|
||||
/* Set INIT register to reset value */
|
||||
LL_CRC_SetInitialData(CRCx, LL_CRC_DEFAULT_CRC_INITVALUE);
|
||||
|
||||
/* Set Reversibility options on I/O data values in CR register to reset value */
|
||||
LL_CRC_SetInputDataReverseMode(CRCx, LL_CRC_INDATA_REVERSE_NONE);
|
||||
LL_CRC_SetOutputDataReverseMode(CRCx, LL_CRC_OUTDATA_REVERSE_NONE);
|
||||
|
||||
/* Reset the CRC calculation unit */
|
||||
LL_CRC_ResetCRCCalculationUnit(CRCx);
|
||||
|
||||
/* Reset IDR register */
|
||||
LL_CRC_Write_IDR(CRCx, 0x00U);
|
||||
}
|
||||
else
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
|
||||
return (status);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined (CRC) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
84
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_crs.c
Normal file
84
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_crs.c
Normal file
@@ -0,0 +1,84 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_ll_crs.h
|
||||
* @author MCD Application Team
|
||||
* @brief CRS LL module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_ll_crs.h"
|
||||
#include "stm32f0xx_ll_bus.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(CRS)
|
||||
|
||||
/** @defgroup CRS_LL CRS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup CRS_LL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRS_LL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief De-Initializes CRS peripheral registers to their default reset values.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: CRS registers are de-initialized
|
||||
* - ERROR: not applicable
|
||||
*/
|
||||
ErrorStatus LL_CRS_DeInit(void)
|
||||
{
|
||||
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_CRS);
|
||||
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_CRS);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined(CRS) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
274
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_dac.c
Normal file
274
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_dac.c
Normal file
@@ -0,0 +1,274 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_ll_dac.c
|
||||
* @author MCD Application Team
|
||||
* @brief DAC LL module driver
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_ll_dac.h"
|
||||
#include "stm32f0xx_ll_bus.h"
|
||||
|
||||
#ifdef USE_FULL_ASSERT
|
||||
#include "stm32_assert.h"
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32F0xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (DAC1)
|
||||
|
||||
/** @addtogroup DAC_LL DAC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup DAC_LL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
#define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \
|
||||
( \
|
||||
((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \
|
||||
|| ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2) \
|
||||
)
|
||||
#else
|
||||
#define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \
|
||||
( \
|
||||
((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \
|
||||
)
|
||||
#endif /* DAC_CHANNEL2_SUPPORT */
|
||||
|
||||
#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \
|
||||
( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
|
||||
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \
|
||||
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO) \
|
||||
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \
|
||||
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \
|
||||
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \
|
||||
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \
|
||||
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \
|
||||
)
|
||||
|
||||
#if defined(DAC_CR_WAVE1)
|
||||
#define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \
|
||||
( ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \
|
||||
|| ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \
|
||||
|| ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
|
||||
)
|
||||
|
||||
#define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_CONFIG__) \
|
||||
( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \
|
||||
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \
|
||||
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \
|
||||
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \
|
||||
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \
|
||||
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \
|
||||
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \
|
||||
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \
|
||||
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \
|
||||
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \
|
||||
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \
|
||||
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0) \
|
||||
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \
|
||||
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \
|
||||
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \
|
||||
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \
|
||||
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \
|
||||
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \
|
||||
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \
|
||||
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \
|
||||
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \
|
||||
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \
|
||||
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \
|
||||
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095) \
|
||||
)
|
||||
#endif
|
||||
|
||||
#define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__) \
|
||||
( ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \
|
||||
|| ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \
|
||||
)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup DAC_LL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_LL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief De-initialize registers of the selected DAC instance
|
||||
* to their default reset values.
|
||||
* @param DACx DAC instance
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: DAC registers are de-initialized
|
||||
* - ERROR: not applicable
|
||||
*/
|
||||
ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALL_INSTANCE(DACx));
|
||||
|
||||
/* Force reset of DAC clock */
|
||||
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC1);
|
||||
|
||||
/* Release reset of DAC clock */
|
||||
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC1);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize some features of DAC instance.
|
||||
* @note The setting of these parameters by function @ref LL_DAC_Init()
|
||||
* is conditioned to DAC state:
|
||||
* DAC instance must be disabled.
|
||||
* @param DACx DAC instance
|
||||
* @param DAC_Channel This parameter can be one of the following values:
|
||||
* @arg @ref LL_DAC_CHANNEL_1
|
||||
* @arg @ref LL_DAC_CHANNEL_2 (1)
|
||||
*
|
||||
* (1) On this STM32 series, parameter not available on all devices.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @param DAC_InitStruct Pointer to a @ref LL_DAC_InitTypeDef structure
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: DAC registers are initialized
|
||||
* - ERROR: DAC registers are not initialized
|
||||
*/
|
||||
ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALL_INSTANCE(DACx));
|
||||
assert_param(IS_LL_DAC_CHANNEL(DACx, DAC_Channel));
|
||||
assert_param(IS_LL_DAC_TRIGGER_SOURCE(DAC_InitStruct->TriggerSource));
|
||||
assert_param(IS_LL_DAC_OUTPUT_BUFFER(DAC_InitStruct->OutputBuffer));
|
||||
#if defined(DAC_CR_WAVE1)
|
||||
assert_param(IS_LL_DAC_WAVE_AUTO_GENER_MODE(DAC_InitStruct->WaveAutoGeneration));
|
||||
if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
|
||||
{
|
||||
assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGenerationConfig));
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Note: Hardware constraint (refer to description of this function) */
|
||||
/* DAC instance must be disabled. */
|
||||
if(LL_DAC_IsEnabled(DACx, DAC_Channel) == 0U)
|
||||
{
|
||||
/* Configuration of DAC channel: */
|
||||
/* - TriggerSource */
|
||||
#if defined(DAC_CR_WAVE1)
|
||||
/* - WaveAutoGeneration */
|
||||
#endif
|
||||
/* - OutputBuffer */
|
||||
#if defined(DAC_CR_WAVE1)
|
||||
if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
|
||||
{
|
||||
MODIFY_REG(DACx->CR,
|
||||
( DAC_CR_TSEL1
|
||||
| DAC_CR_WAVE1
|
||||
| DAC_CR_MAMP1
|
||||
| DAC_CR_BOFF1
|
||||
) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
|
||||
,
|
||||
( DAC_InitStruct->TriggerSource
|
||||
| DAC_InitStruct->WaveAutoGeneration
|
||||
| DAC_InitStruct->WaveAutoGenerationConfig
|
||||
| DAC_InitStruct->OutputBuffer
|
||||
) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
|
||||
);
|
||||
}
|
||||
else
|
||||
{
|
||||
MODIFY_REG(DACx->CR,
|
||||
( DAC_CR_TSEL1
|
||||
| DAC_CR_WAVE1
|
||||
| DAC_CR_BOFF1
|
||||
) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
|
||||
,
|
||||
( DAC_InitStruct->TriggerSource
|
||||
| LL_DAC_WAVE_AUTO_GENERATION_NONE
|
||||
| DAC_InitStruct->OutputBuffer
|
||||
) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
|
||||
);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Initialization error: DAC instance is not disabled. */
|
||||
status = ERROR;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set each @ref LL_DAC_InitTypeDef field to default value.
|
||||
* @param DAC_InitStruct pointer to a @ref LL_DAC_InitTypeDef structure
|
||||
* whose fields will be set to default values.
|
||||
* @retval None
|
||||
*/
|
||||
void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct)
|
||||
{
|
||||
/* Set DAC_InitStruct fields to default values */
|
||||
DAC_InitStruct->TriggerSource = LL_DAC_TRIG_SOFTWARE;
|
||||
#if defined(DAC_CR_WAVE1)
|
||||
DAC_InitStruct->WaveAutoGeneration = LL_DAC_WAVE_AUTO_GENERATION_NONE;
|
||||
/* Note: Parameter discarded if wave auto generation is disabled, */
|
||||
/* set anyway to its default value. */
|
||||
DAC_InitStruct->WaveAutoGenerationConfig = LL_DAC_NOISE_LFSR_UNMASK_BIT0;
|
||||
#endif
|
||||
DAC_InitStruct->OutputBuffer = LL_DAC_OUTPUT_BUFFER_ENABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* DAC1 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
395
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_dma.c
Normal file
395
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_dma.c
Normal file
@@ -0,0 +1,395 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_ll_dma.c
|
||||
* @author MCD Application Team
|
||||
* @brief DMA LL module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_ll_dma.h"
|
||||
#include "stm32f0xx_ll_bus.h"
|
||||
#ifdef USE_FULL_ASSERT
|
||||
#include "stm32_assert.h"
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32F0xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (DMA1) || defined (DMA2)
|
||||
|
||||
/** @defgroup DMA_LL DMA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup DMA_LL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
|
||||
((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
|
||||
((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
|
||||
|
||||
#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
|
||||
((__VALUE__) == LL_DMA_MODE_CIRCULAR))
|
||||
|
||||
#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
|
||||
((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
|
||||
|
||||
#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
|
||||
((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
|
||||
|
||||
#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
|
||||
((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
|
||||
((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
|
||||
|
||||
#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
|
||||
((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
|
||||
((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
|
||||
|
||||
#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
|
||||
|
||||
#if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
|
||||
#define IS_LL_DMA_PERIPHREQUEST(__VALUE__) (((__VALUE__) == LL_DMA_REQUEST_0) || \
|
||||
((__VALUE__) == LL_DMA_REQUEST_1) || \
|
||||
((__VALUE__) == LL_DMA_REQUEST_2) || \
|
||||
((__VALUE__) == LL_DMA_REQUEST_3) || \
|
||||
((__VALUE__) == LL_DMA_REQUEST_4) || \
|
||||
((__VALUE__) == LL_DMA_REQUEST_5) || \
|
||||
((__VALUE__) == LL_DMA_REQUEST_6) || \
|
||||
((__VALUE__) == LL_DMA_REQUEST_7) || \
|
||||
((__VALUE__) == LL_DMA_REQUEST_8) || \
|
||||
((__VALUE__) == LL_DMA_REQUEST_9) || \
|
||||
((__VALUE__) == LL_DMA_REQUEST_10) || \
|
||||
((__VALUE__) == LL_DMA_REQUEST_11) || \
|
||||
((__VALUE__) == LL_DMA_REQUEST_12) || \
|
||||
((__VALUE__) == LL_DMA_REQUEST_13) || \
|
||||
((__VALUE__) == LL_DMA_REQUEST_14) || \
|
||||
((__VALUE__) == LL_DMA_REQUEST_15))
|
||||
#endif
|
||||
|
||||
#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
|
||||
((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
|
||||
((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
|
||||
((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
|
||||
|
||||
#if defined (DMA2)
|
||||
#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
|
||||
#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
|
||||
(((CHANNEL) == LL_DMA_CHANNEL_1) || \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_2) || \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_3) || \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_4) || \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_5) || \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_6) || \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_7))) || \
|
||||
(((INSTANCE) == DMA2) && \
|
||||
(((CHANNEL) == LL_DMA_CHANNEL_1) || \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_2) || \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_3) || \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_4) || \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_5) || \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_6) || \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_7))))
|
||||
#else
|
||||
#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
|
||||
(((CHANNEL) == LL_DMA_CHANNEL_1) || \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_2) || \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_3) || \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_4) || \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_5) || \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_6) || \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_7))) || \
|
||||
(((INSTANCE) == DMA2) && \
|
||||
(((CHANNEL) == LL_DMA_CHANNEL_1) || \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_2) || \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_3) || \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_4) || \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_5))))
|
||||
#endif
|
||||
#else
|
||||
#if defined(DMA1_Channel6) && defined(DMA1_Channel7)
|
||||
#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
|
||||
(((CHANNEL) == LL_DMA_CHANNEL_1)|| \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_2) || \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_3) || \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_4) || \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_5) || \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_6) || \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_7))))
|
||||
#elif defined (DMA1_Channel6)
|
||||
#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
|
||||
(((CHANNEL) == LL_DMA_CHANNEL_1)|| \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_2) || \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_3) || \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_4) || \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_5) || \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_6))))
|
||||
#else
|
||||
#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
|
||||
(((CHANNEL) == LL_DMA_CHANNEL_1)|| \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_2) || \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_3) || \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_4) || \
|
||||
((CHANNEL) == LL_DMA_CHANNEL_5))))
|
||||
#endif /* DMA1_Channel6 && DMA1_Channel7 */
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup DMA_LL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_LL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief De-initialize the DMA registers to their default reset values.
|
||||
* @param DMAx DMAx Instance
|
||||
* @param Channel This parameter can be one of the following values:
|
||||
* @arg @ref LL_DMA_CHANNEL_1
|
||||
* @arg @ref LL_DMA_CHANNEL_2
|
||||
* @arg @ref LL_DMA_CHANNEL_3
|
||||
* @arg @ref LL_DMA_CHANNEL_4
|
||||
* @arg @ref LL_DMA_CHANNEL_5
|
||||
* @arg @ref LL_DMA_CHANNEL_6 (*)
|
||||
* @arg @ref LL_DMA_CHANNEL_7 (*)
|
||||
*
|
||||
* (*) value not defined in all devices
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: DMA registers are de-initialized
|
||||
* - ERROR: DMA registers are not de-initialized
|
||||
*/
|
||||
uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
|
||||
{
|
||||
DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1;
|
||||
ErrorStatus status = SUCCESS;
|
||||
|
||||
/* Check the DMA Instance DMAx and Channel parameters*/
|
||||
assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
|
||||
|
||||
tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
|
||||
|
||||
/* Disable the selected DMAx_Channely */
|
||||
CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
|
||||
|
||||
/* Reset DMAx_Channely control register */
|
||||
LL_DMA_WriteReg(tmp, CCR, 0U);
|
||||
|
||||
/* Reset DMAx_Channely remaining bytes register */
|
||||
LL_DMA_WriteReg(tmp, CNDTR, 0U);
|
||||
|
||||
/* Reset DMAx_Channely peripheral address register */
|
||||
LL_DMA_WriteReg(tmp, CPAR, 0U);
|
||||
|
||||
/* Reset DMAx_Channely memory address register */
|
||||
LL_DMA_WriteReg(tmp, CMAR, 0U);
|
||||
|
||||
#if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
|
||||
/* Reset Request register field for DMAx Channel */
|
||||
LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMA_REQUEST_0);
|
||||
#endif
|
||||
|
||||
if (Channel == LL_DMA_CHANNEL_1)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMAx Channel1 */
|
||||
LL_DMA_ClearFlag_GI1(DMAx);
|
||||
}
|
||||
else if (Channel == LL_DMA_CHANNEL_2)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMAx Channel2 */
|
||||
LL_DMA_ClearFlag_GI2(DMAx);
|
||||
}
|
||||
else if (Channel == LL_DMA_CHANNEL_3)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMAx Channel3 */
|
||||
LL_DMA_ClearFlag_GI3(DMAx);
|
||||
}
|
||||
else if (Channel == LL_DMA_CHANNEL_4)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMAx Channel4 */
|
||||
LL_DMA_ClearFlag_GI4(DMAx);
|
||||
}
|
||||
else if (Channel == LL_DMA_CHANNEL_5)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMAx Channel5 */
|
||||
LL_DMA_ClearFlag_GI5(DMAx);
|
||||
}
|
||||
|
||||
#if defined(DMA1_Channel6)
|
||||
else if (Channel == LL_DMA_CHANNEL_6)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMAx Channel6 */
|
||||
LL_DMA_ClearFlag_GI6(DMAx);
|
||||
}
|
||||
#endif
|
||||
#if defined(DMA1_Channel7)
|
||||
else if (Channel == LL_DMA_CHANNEL_7)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMAx Channel7 */
|
||||
LL_DMA_ClearFlag_GI7(DMAx);
|
||||
}
|
||||
#endif
|
||||
else
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
|
||||
* @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
|
||||
* @arg @ref __LL_DMA_GET_INSTANCE
|
||||
* @arg @ref __LL_DMA_GET_CHANNEL
|
||||
* @param DMAx DMAx Instance
|
||||
* @param Channel This parameter can be one of the following values:
|
||||
* @arg @ref LL_DMA_CHANNEL_1
|
||||
* @arg @ref LL_DMA_CHANNEL_2
|
||||
* @arg @ref LL_DMA_CHANNEL_3
|
||||
* @arg @ref LL_DMA_CHANNEL_4
|
||||
* @arg @ref LL_DMA_CHANNEL_5
|
||||
* @arg @ref LL_DMA_CHANNEL_6 (*)
|
||||
* @arg @ref LL_DMA_CHANNEL_7 (*)
|
||||
*
|
||||
* (*) value not defined in all devices
|
||||
* @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: DMA registers are initialized
|
||||
* - ERROR: Not applicable
|
||||
*/
|
||||
uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
|
||||
{
|
||||
/* Check the DMA Instance DMAx and Channel parameters*/
|
||||
assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
|
||||
|
||||
/* Check the DMA parameters from DMA_InitStruct */
|
||||
assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
|
||||
assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
|
||||
assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
|
||||
assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
|
||||
assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
|
||||
assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
|
||||
assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
|
||||
#if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
|
||||
assert_param(IS_LL_DMA_PERIPHREQUEST(DMA_InitStruct->PeriphRequest));
|
||||
#endif
|
||||
assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
|
||||
|
||||
/*---------------------------- DMAx CCR Configuration ------------------------
|
||||
* Configure DMAx_Channely: data transfer direction, data transfer mode,
|
||||
* peripheral and memory increment mode,
|
||||
* data size alignment and priority level with parameters :
|
||||
* - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
|
||||
* - Mode: DMA_CCR_CIRC bit
|
||||
* - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit
|
||||
* - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit
|
||||
* - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
|
||||
* - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
|
||||
* - Priority: DMA_CCR_PL[1:0] bits
|
||||
*/
|
||||
LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \
|
||||
DMA_InitStruct->Mode | \
|
||||
DMA_InitStruct->PeriphOrM2MSrcIncMode | \
|
||||
DMA_InitStruct->MemoryOrM2MDstIncMode | \
|
||||
DMA_InitStruct->PeriphOrM2MSrcDataSize | \
|
||||
DMA_InitStruct->MemoryOrM2MDstDataSize | \
|
||||
DMA_InitStruct->Priority);
|
||||
|
||||
/*-------------------------- DMAx CMAR Configuration -------------------------
|
||||
* Configure the memory or destination base address with parameter :
|
||||
* - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
|
||||
*/
|
||||
LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
|
||||
|
||||
/*-------------------------- DMAx CPAR Configuration -------------------------
|
||||
* Configure the peripheral or source base address with parameter :
|
||||
* - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
|
||||
*/
|
||||
LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
|
||||
|
||||
/*--------------------------- DMAx CNDTR Configuration -----------------------
|
||||
* Configure the peripheral base address with parameter :
|
||||
* - NbData: DMA_CNDTR_NDT[15:0] bits
|
||||
*/
|
||||
LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
|
||||
|
||||
#if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
|
||||
/*--------------------------- DMAx CSELR Configuration -----------------------
|
||||
* Configure the DMA request for DMA instance on Channel x with parameter :
|
||||
* - PeriphRequest: DMA_CSELR[31:0] bits
|
||||
*/
|
||||
LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest);
|
||||
#endif
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set each @ref LL_DMA_InitTypeDef field to default value.
|
||||
* @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
|
||||
* @retval None
|
||||
*/
|
||||
void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
|
||||
{
|
||||
/* Set DMA_InitStruct fields to default values */
|
||||
DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
|
||||
DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
|
||||
DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
|
||||
DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
|
||||
DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
|
||||
DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
|
||||
DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
|
||||
DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
|
||||
DMA_InitStruct->NbData = 0x00000000U;
|
||||
#if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
|
||||
DMA_InitStruct->PeriphRequest = LL_DMA_REQUEST_0;
|
||||
#endif
|
||||
DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* DMA1 || DMA2 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
221
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c
Normal file
221
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c
Normal file
@@ -0,0 +1,221 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_ll_exti.c
|
||||
* @author MCD Application Team
|
||||
* @brief EXTI LL module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_ll_exti.h"
|
||||
#ifdef USE_FULL_ASSERT
|
||||
#include "stm32_assert.h"
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32F0xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (EXTI)
|
||||
|
||||
/** @defgroup EXTI_LL EXTI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup EXTI_LL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
|
||||
|
||||
#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \
|
||||
|| ((__VALUE__) == LL_EXTI_MODE_EVENT) \
|
||||
|| ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
|
||||
|
||||
|
||||
#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \
|
||||
|| ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \
|
||||
|| ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \
|
||||
|| ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup EXTI_LL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI_LL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief De-initialize the EXTI registers to their default reset values.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: EXTI registers are de-initialized
|
||||
* - ERROR: not applicable
|
||||
*/
|
||||
uint32_t LL_EXTI_DeInit(void)
|
||||
{
|
||||
/* Interrupt mask register set to default reset values */
|
||||
#if defined(STM32F030x6) || defined(STM32F031x6) ||defined(STM32F038xx)
|
||||
LL_EXTI_WriteReg(IMR, 0x0FF40000U);
|
||||
#elif defined(STM32F070x6) || defined(STM32F042x6) || defined(STM32F048xx)
|
||||
LL_EXTI_WriteReg(IMR, 0x7FF40000U);
|
||||
#elif defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
|
||||
LL_EXTI_WriteReg(IMR, 0x0F940000U);
|
||||
#else
|
||||
LL_EXTI_WriteReg(IMR, 0x7F840000U);
|
||||
#endif
|
||||
/* Event mask register set to default reset values */
|
||||
LL_EXTI_WriteReg(EMR, 0x00000000U);
|
||||
/* Rising Trigger selection register set to default reset values */
|
||||
LL_EXTI_WriteReg(RTSR, 0x00000000U);
|
||||
/* Falling Trigger selection register set to default reset values */
|
||||
LL_EXTI_WriteReg(FTSR, 0x00000000U);
|
||||
/* Software interrupt event register set to default reset values */
|
||||
LL_EXTI_WriteReg(SWIER, 0x00000000U);
|
||||
/* Pending register clear */
|
||||
LL_EXTI_WriteReg(PR, 0x007BFFFFU);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
|
||||
* @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: EXTI registers are initialized
|
||||
* - ERROR: not applicable
|
||||
*/
|
||||
uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
|
||||
assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
|
||||
assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
|
||||
|
||||
/* ENABLE LineCommand */
|
||||
if (EXTI_InitStruct->LineCommand != DISABLE)
|
||||
{
|
||||
assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
|
||||
|
||||
/* Configure EXTI Lines in range from 0 to 31 */
|
||||
if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
|
||||
{
|
||||
switch (EXTI_InitStruct->Mode)
|
||||
{
|
||||
case LL_EXTI_MODE_IT:
|
||||
/* First Disable Event on provided Lines */
|
||||
LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
|
||||
/* Then Enable IT on provided Lines */
|
||||
LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
|
||||
break;
|
||||
case LL_EXTI_MODE_EVENT:
|
||||
/* First Disable IT on provided Lines */
|
||||
LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
|
||||
/* Then Enable Event on provided Lines */
|
||||
LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
|
||||
break;
|
||||
case LL_EXTI_MODE_IT_EVENT:
|
||||
/* Directly Enable IT & Event on provided Lines */
|
||||
LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
|
||||
LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
|
||||
break;
|
||||
default:
|
||||
status = ERROR;
|
||||
break;
|
||||
}
|
||||
if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
|
||||
{
|
||||
switch (EXTI_InitStruct->Trigger)
|
||||
{
|
||||
case LL_EXTI_TRIGGER_RISING:
|
||||
/* First Disable Falling Trigger on provided Lines */
|
||||
LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
|
||||
/* Then Enable Rising Trigger on provided Lines */
|
||||
LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
|
||||
break;
|
||||
case LL_EXTI_TRIGGER_FALLING:
|
||||
/* First Disable Rising Trigger on provided Lines */
|
||||
LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
|
||||
/* Then Enable Falling Trigger on provided Lines */
|
||||
LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
|
||||
break;
|
||||
case LL_EXTI_TRIGGER_RISING_FALLING:
|
||||
LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
|
||||
LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
|
||||
break;
|
||||
default:
|
||||
status = ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
/* DISABLE LineCommand */
|
||||
else
|
||||
{
|
||||
/* De-configure EXTI Lines in range from 0 to 31 */
|
||||
LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
|
||||
LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set each @ref LL_EXTI_InitTypeDef field to default value.
|
||||
* @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
|
||||
* @retval None
|
||||
*/
|
||||
void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
|
||||
{
|
||||
EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE;
|
||||
EXTI_InitStruct->LineCommand = DISABLE;
|
||||
EXTI_InitStruct->Mode = LL_EXTI_MODE_IT;
|
||||
EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined (EXTI) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
275
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c
Normal file
275
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c
Normal file
@@ -0,0 +1,275 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_ll_gpio.c
|
||||
* @author MCD Application Team
|
||||
* @brief GPIO LL module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_ll_gpio.h"
|
||||
#include "stm32f0xx_ll_bus.h"
|
||||
#ifdef USE_FULL_ASSERT
|
||||
#include "stm32_assert.h"
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32F0xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF)
|
||||
|
||||
/** @addtogroup GPIO_LL
|
||||
* @{
|
||||
*/
|
||||
/** MISRA C:2012 deviation rule has been granted for following rules:
|
||||
* Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of
|
||||
* range of the shift operator in following API :
|
||||
* LL_GPIO_Init
|
||||
* LL_GPIO_DeInit
|
||||
* LL_GPIO_SetPinMode
|
||||
* LL_GPIO_GetPinMode
|
||||
* LL_GPIO_SetPinSpeed
|
||||
* LL_GPIO_GetPinSpeed
|
||||
* LL_GPIO_SetPinPull
|
||||
* LL_GPIO_GetPinPull
|
||||
* LL_GPIO_GetAFPin_0_7
|
||||
* LL_GPIO_SetAFPin_0_7
|
||||
* LL_GPIO_SetAFPin_8_15
|
||||
* LL_GPIO_GetAFPin_8_15
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup GPIO_LL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_LL_GPIO_PIN(__VALUE__) (((0x00u) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
|
||||
|
||||
#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\
|
||||
((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\
|
||||
((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
|
||||
((__VALUE__) == LL_GPIO_MODE_ANALOG))
|
||||
|
||||
#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\
|
||||
((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
|
||||
|
||||
#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\
|
||||
((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\
|
||||
((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH))
|
||||
|
||||
#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_NO) ||\
|
||||
((__VALUE__) == LL_GPIO_PULL_UP) ||\
|
||||
((__VALUE__) == LL_GPIO_PULL_DOWN))
|
||||
|
||||
#define IS_LL_GPIO_ALTERNATE(__VALUE__) (((__VALUE__) == LL_GPIO_AF_0 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_1 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_2 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_3 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_4 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_5 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_6 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_7 ))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup GPIO_LL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_LL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief De-initialize GPIO registers (Registers restored to their default values).
|
||||
* @param GPIOx GPIO Port
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: GPIO registers are de-initialized
|
||||
* - ERROR: Wrong GPIO Port
|
||||
*/
|
||||
ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
||||
|
||||
/* Force and Release reset on clock of GPIOx Port */
|
||||
if (GPIOx == GPIOA)
|
||||
{
|
||||
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOA);
|
||||
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOA);
|
||||
}
|
||||
else if (GPIOx == GPIOB)
|
||||
{
|
||||
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOB);
|
||||
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOB);
|
||||
}
|
||||
else if (GPIOx == GPIOC)
|
||||
{
|
||||
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOC);
|
||||
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOC);
|
||||
}
|
||||
#if defined(GPIOD)
|
||||
else if (GPIOx == GPIOD)
|
||||
{
|
||||
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOD);
|
||||
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOD);
|
||||
}
|
||||
#endif /* GPIOD */
|
||||
#if defined(GPIOE)
|
||||
else if (GPIOx == GPIOE)
|
||||
{
|
||||
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOE);
|
||||
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOE);
|
||||
}
|
||||
#endif /* GPIOE */
|
||||
#if defined(GPIOF)
|
||||
else if (GPIOx == GPIOF)
|
||||
{
|
||||
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOF);
|
||||
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOF);
|
||||
}
|
||||
#endif /* GPIOF */
|
||||
else
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
|
||||
return (status);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
|
||||
* @param GPIOx GPIO Port
|
||||
* @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
|
||||
* that contains the configuration information for the specified GPIO peripheral.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
|
||||
* - ERROR: Not applicable
|
||||
*/
|
||||
ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
|
||||
{
|
||||
uint32_t pinpos;
|
||||
uint32_t currentpin;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
||||
assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
|
||||
assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
|
||||
assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
|
||||
|
||||
/* ------------------------- Configure the port pins ---------------- */
|
||||
/* Initialize pinpos on first pin set */
|
||||
pinpos = 0;
|
||||
|
||||
/* Configure the port pins */
|
||||
while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00u)
|
||||
{
|
||||
/* Get current io position */
|
||||
currentpin = (GPIO_InitStruct->Pin) & (0x00000001uL << pinpos);
|
||||
|
||||
if (currentpin != 0x00u)
|
||||
{
|
||||
if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
|
||||
{
|
||||
/* Check Speed mode parameters */
|
||||
assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
|
||||
|
||||
/* Speed mode configuration */
|
||||
LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
|
||||
|
||||
/* Check Output mode parameters */
|
||||
assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
|
||||
|
||||
/* Output mode configuration*/
|
||||
LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
|
||||
}
|
||||
|
||||
/* Pull-up Pull down resistor configuration*/
|
||||
LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
|
||||
|
||||
if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)
|
||||
{
|
||||
/* Check Alternate parameter */
|
||||
assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
|
||||
|
||||
/* Speed mode configuration */
|
||||
if (currentpin < LL_GPIO_PIN_8)
|
||||
{
|
||||
LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);
|
||||
}
|
||||
else
|
||||
{
|
||||
LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
|
||||
}
|
||||
}
|
||||
|
||||
/* Pin Mode configuration */
|
||||
LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
|
||||
}
|
||||
pinpos++;
|
||||
}
|
||||
|
||||
return (SUCCESS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
|
||||
* @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
|
||||
* whose fields will be set to default values.
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
|
||||
{
|
||||
/* Reset GPIO init structure parameters values */
|
||||
GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL;
|
||||
GPIO_InitStruct->Mode = LL_GPIO_MODE_ANALOG;
|
||||
GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW;
|
||||
GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL;
|
||||
GPIO_InitStruct->Pull = LL_GPIO_PULL_NO;
|
||||
GPIO_InitStruct->Alternate = LL_GPIO_AF_0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
226
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_i2c.c
Normal file
226
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_i2c.c
Normal file
@@ -0,0 +1,226 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_ll_i2c.c
|
||||
* @author MCD Application Team
|
||||
* @brief I2C LL module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_ll_i2c.h"
|
||||
#include "stm32f0xx_ll_bus.h"
|
||||
#ifdef USE_FULL_ASSERT
|
||||
#include "stm32_assert.h"
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
/** @addtogroup STM32F0xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (I2C1) || defined (I2C2)
|
||||
|
||||
/** @defgroup I2C_LL I2C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup I2C_LL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_LL_I2C_PERIPHERAL_MODE(__VALUE__) (((__VALUE__) == LL_I2C_MODE_I2C) || \
|
||||
((__VALUE__) == LL_I2C_MODE_SMBUS_HOST) || \
|
||||
((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
|
||||
((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))
|
||||
|
||||
#define IS_LL_I2C_ANALOG_FILTER(__VALUE__) (((__VALUE__) == LL_I2C_ANALOGFILTER_ENABLE) || \
|
||||
((__VALUE__) == LL_I2C_ANALOGFILTER_DISABLE))
|
||||
|
||||
#define IS_LL_I2C_DIGITAL_FILTER(__VALUE__) ((__VALUE__) <= 0x0000000FU)
|
||||
|
||||
#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU)
|
||||
|
||||
#define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__) (((__VALUE__) == LL_I2C_ACK) || \
|
||||
((__VALUE__) == LL_I2C_NACK))
|
||||
|
||||
#define IS_LL_I2C_OWN_ADDRSIZE(__VALUE__) (((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \
|
||||
((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup I2C_LL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_LL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief De-initialize the I2C registers to their default reset values.
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: I2C registers are de-initialized
|
||||
* - ERROR: I2C registers are not de-initialized
|
||||
*/
|
||||
ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
|
||||
/* Check the I2C Instance I2Cx */
|
||||
assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
|
||||
|
||||
if (I2Cx == I2C1)
|
||||
{
|
||||
/* Force reset of I2C clock */
|
||||
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1);
|
||||
|
||||
/* Release reset of I2C clock */
|
||||
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1);
|
||||
}
|
||||
#if defined(I2C2)
|
||||
else if (I2Cx == I2C2)
|
||||
{
|
||||
/* Force reset of I2C clock */
|
||||
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2);
|
||||
|
||||
/* Release reset of I2C clock */
|
||||
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2);
|
||||
|
||||
}
|
||||
#endif /* I2C2 */
|
||||
else
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
|
||||
* @param I2Cx I2C Instance.
|
||||
* @param I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: I2C registers are initialized
|
||||
* - ERROR: Not applicable
|
||||
*/
|
||||
ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct)
|
||||
{
|
||||
/* Check the I2C Instance I2Cx */
|
||||
assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
|
||||
|
||||
/* Check the I2C parameters from I2C_InitStruct */
|
||||
assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode));
|
||||
assert_param(IS_LL_I2C_ANALOG_FILTER(I2C_InitStruct->AnalogFilter));
|
||||
assert_param(IS_LL_I2C_DIGITAL_FILTER(I2C_InitStruct->DigitalFilter));
|
||||
assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1));
|
||||
assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge));
|
||||
assert_param(IS_LL_I2C_OWN_ADDRSIZE(I2C_InitStruct->OwnAddrSize));
|
||||
|
||||
/* Disable the selected I2Cx Peripheral */
|
||||
LL_I2C_Disable(I2Cx);
|
||||
|
||||
/*---------------------------- I2Cx CR1 Configuration ------------------------
|
||||
* Configure the analog and digital noise filters with parameters :
|
||||
* - AnalogFilter: I2C_CR1_ANFOFF bit
|
||||
* - DigitalFilter: I2C_CR1_DNF[3:0] bits
|
||||
*/
|
||||
LL_I2C_ConfigFilters(I2Cx, I2C_InitStruct->AnalogFilter, I2C_InitStruct->DigitalFilter);
|
||||
|
||||
/*---------------------------- I2Cx TIMINGR Configuration --------------------
|
||||
* Configure the SDA setup, hold time and the SCL high, low period with parameter :
|
||||
* - Timing: I2C_TIMINGR_PRESC[3:0], I2C_TIMINGR_SCLDEL[3:0], I2C_TIMINGR_SDADEL[3:0],
|
||||
* I2C_TIMINGR_SCLH[7:0] and I2C_TIMINGR_SCLL[7:0] bits
|
||||
*/
|
||||
LL_I2C_SetTiming(I2Cx, I2C_InitStruct->Timing);
|
||||
|
||||
/* Enable the selected I2Cx Peripheral */
|
||||
LL_I2C_Enable(I2Cx);
|
||||
|
||||
/*---------------------------- I2Cx OAR1 Configuration -----------------------
|
||||
* Disable, Configure and Enable I2Cx device own address 1 with parameters :
|
||||
* - OwnAddress1: I2C_OAR1_OA1[9:0] bits
|
||||
* - OwnAddrSize: I2C_OAR1_OA1MODE bit
|
||||
*/
|
||||
LL_I2C_DisableOwnAddress1(I2Cx);
|
||||
LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize);
|
||||
|
||||
/* OwnAdress1 == 0 is reserved for General Call address */
|
||||
if (I2C_InitStruct->OwnAddress1 != 0U)
|
||||
{
|
||||
LL_I2C_EnableOwnAddress1(I2Cx);
|
||||
}
|
||||
|
||||
/*---------------------------- I2Cx MODE Configuration -----------------------
|
||||
* Configure I2Cx peripheral mode with parameter :
|
||||
* - PeripheralMode: I2C_CR1_SMBDEN and I2C_CR1_SMBHEN bits
|
||||
*/
|
||||
LL_I2C_SetMode(I2Cx, I2C_InitStruct->PeripheralMode);
|
||||
|
||||
/*---------------------------- I2Cx CR2 Configuration ------------------------
|
||||
* Configure the ACKnowledge or Non ACKnowledge condition
|
||||
* after the address receive match code or next received byte with parameter :
|
||||
* - TypeAcknowledge: I2C_CR2_NACK bit
|
||||
*/
|
||||
LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set each @ref LL_I2C_InitTypeDef field to default value.
|
||||
* @param I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure.
|
||||
* @retval None
|
||||
*/
|
||||
void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct)
|
||||
{
|
||||
/* Set I2C_InitStruct fields to default values */
|
||||
I2C_InitStruct->PeripheralMode = LL_I2C_MODE_I2C;
|
||||
I2C_InitStruct->Timing = 0U;
|
||||
I2C_InitStruct->AnalogFilter = LL_I2C_ANALOGFILTER_ENABLE;
|
||||
I2C_InitStruct->DigitalFilter = 0U;
|
||||
I2C_InitStruct->OwnAddress1 = 0U;
|
||||
I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK;
|
||||
I2C_InitStruct->OwnAddrSize = LL_I2C_OWNADDRESS1_7BIT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* I2C1 || I2C2 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
83
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c
Normal file
83
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c
Normal file
@@ -0,0 +1,83 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_ll_pwr.c
|
||||
* @author MCD Application Team
|
||||
* @brief PWR LL module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_ll_pwr.h"
|
||||
#include "stm32f0xx_ll_bus.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(PWR)
|
||||
|
||||
/** @defgroup PWR_LL PWR
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup PWR_LL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR_LL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief De-initialize the PWR registers to their default reset values.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: PWR registers are de-initialized
|
||||
* - ERROR: not applicable
|
||||
*/
|
||||
ErrorStatus LL_PWR_DeInit(void)
|
||||
{
|
||||
/* Force reset of PWR clock */
|
||||
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR);
|
||||
|
||||
/* Release reset of PWR clock */
|
||||
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* defined(PWR) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
606
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c
Normal file
606
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c
Normal file
@@ -0,0 +1,606 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_ll_rcc.c
|
||||
* @author MCD Application Team
|
||||
* @brief RCC LL module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_ll_rcc.h"
|
||||
#ifdef USE_FULL_ASSERT
|
||||
#include "stm32_assert.h"
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
/** @addtogroup STM32F0xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(RCC)
|
||||
|
||||
/** @defgroup RCC_LL RCC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup RCC_LL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#if defined(RCC_CFGR3_USART2SW) && defined(RCC_CFGR3_USART3SW)
|
||||
#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
|
||||
|| ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
|
||||
|| ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
|
||||
#elif defined(RCC_CFGR3_USART2SW) && !defined(RCC_CFGR3_USART3SW)
|
||||
#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
|
||||
|| ((__VALUE__) == LL_RCC_USART2_CLKSOURCE))
|
||||
#elif defined(RCC_CFGR3_USART3SW) && !defined(RCC_CFGR3_USART2SW)
|
||||
#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
|
||||
|| ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
|
||||
#else
|
||||
#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE))
|
||||
#endif /* RCC_CFGR3_USART2SW && RCC_CFGR3_USART3SW */
|
||||
|
||||
#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE)
|
||||
|
||||
#if defined(USB)
|
||||
#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
|
||||
#endif /* USB */
|
||||
|
||||
#if defined(CEC)
|
||||
#define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))
|
||||
#endif /* CEC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup RCC_LL_Private_Functions RCC Private functions
|
||||
* @{
|
||||
*/
|
||||
uint32_t RCC_GetSystemClockFreq(void);
|
||||
uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
|
||||
uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
|
||||
uint32_t RCC_PLL_GetFreqDomain_SYS(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup RCC_LL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RCC_LL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Reset the RCC clock configuration to the default reset state.
|
||||
* @note The default reset state of the clock configuration is given below:
|
||||
* - HSI ON and used as system clock source
|
||||
* - HSE and PLL OFF
|
||||
* - AHB and APB1 prescaler set to 1.
|
||||
* - CSS, MCO OFF
|
||||
* - All interrupts disabled
|
||||
* @note This function doesn't modify the configuration of the
|
||||
* - Peripheral clocks
|
||||
* - LSI, LSE and RTC clocks
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: RCC registers are de-initialized
|
||||
* - ERROR: not applicable
|
||||
*/
|
||||
ErrorStatus LL_RCC_DeInit(void)
|
||||
{
|
||||
__IO uint32_t vl_mask;
|
||||
|
||||
/* Set HSION bit */
|
||||
LL_RCC_HSI_Enable();
|
||||
|
||||
/* Wait for HSI READY bit */
|
||||
while(LL_RCC_HSI_IsReady() != 1U)
|
||||
{}
|
||||
|
||||
/* Set HSITRIM bits to the reset value*/
|
||||
LL_RCC_HSI_SetCalibTrimming(0x10U);
|
||||
|
||||
/* Reset SW, HPRE, PPRE and MCOSEL bits */
|
||||
vl_mask = 0xFFFFFFFFU;
|
||||
CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE | RCC_CFGR_MCOSEL));
|
||||
|
||||
/* Write new value in CFGR register */
|
||||
LL_RCC_WriteReg(CFGR, vl_mask);
|
||||
|
||||
/* Wait till system clock source is ready */
|
||||
while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
|
||||
{}
|
||||
|
||||
/* Read CR register */
|
||||
vl_mask = LL_RCC_ReadReg(CR);
|
||||
|
||||
/* Reset HSEON, CSSON, PLLON bits */
|
||||
CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON));
|
||||
|
||||
/* Write new value in CR register */
|
||||
LL_RCC_WriteReg(CR, vl_mask);
|
||||
|
||||
/* Wait for PLL READY bit to be reset */
|
||||
while(LL_RCC_PLL_IsReady() != 0U)
|
||||
{}
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
LL_RCC_HSE_DisableBypass();
|
||||
|
||||
/* Reset CFGR register */
|
||||
LL_RCC_WriteReg(CFGR, 0x00000000U);
|
||||
|
||||
#if defined(RCC_HSI48_SUPPORT)
|
||||
/* Reset CR2 register */
|
||||
LL_RCC_WriteReg(CR2, 0x00000000U);
|
||||
|
||||
/* Disable HSI48 */
|
||||
LL_RCC_HSI48_Disable();
|
||||
|
||||
#endif /*RCC_HSI48_SUPPORT*/
|
||||
/* Set HSI14TRIM/HSI14ON/HSI14DIS bits to the reset value*/
|
||||
LL_RCC_HSI14_SetCalibTrimming(0x10U);
|
||||
LL_RCC_HSI14_Disable();
|
||||
LL_RCC_HSI14_EnableADCControl();
|
||||
|
||||
/* Reset CFGR2 register */
|
||||
LL_RCC_WriteReg(CFGR2, 0x00000000U);
|
||||
|
||||
/* Reset CFGR3 register */
|
||||
LL_RCC_WriteReg(CFGR3, 0x00000000U);
|
||||
|
||||
/* Clear pending flags */
|
||||
#if defined(RCC_HSI48_SUPPORT)
|
||||
vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC |\
|
||||
LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_HSI14RDYC | LL_RCC_CIR_HSI48RDYC | LL_RCC_CIR_CSSC);
|
||||
#else
|
||||
vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC |\
|
||||
LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_HSI14RDYC | LL_RCC_CIR_CSSC);
|
||||
#endif /* RCC_HSI48_SUPPORT */
|
||||
|
||||
/* Write new value in CIR register */
|
||||
LL_RCC_WriteReg(CIR, vl_mask);
|
||||
|
||||
/* Disable all interrupts */
|
||||
LL_RCC_WriteReg(CIR, 0x00000000U);
|
||||
|
||||
/* Clear reset flags */
|
||||
LL_RCC_ClearResetFlags();
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RCC_LL_EF_Get_Freq
|
||||
* @brief Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks
|
||||
* and different peripheral clocks available on the device.
|
||||
* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
|
||||
* @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
|
||||
* @note If SYSCLK source is PLL, function returns values based on
|
||||
* HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
|
||||
* @note (**) HSI_VALUE is a defined constant but the real value may vary
|
||||
* depending on the variations in voltage and temperature.
|
||||
* @note (***) HSE_VALUE is a defined constant, user has to ensure that
|
||||
* HSE_VALUE is same as the real frequency of the crystal used.
|
||||
* Otherwise, this function may have wrong result.
|
||||
* @note The result of this function could be incorrect when using fractional
|
||||
* value for HSE crystal.
|
||||
* @note This function can be used by the user application to compute the
|
||||
* baud-rate for the communication peripherals or configure other parameters.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks
|
||||
* @note Each time SYSCLK, HCLK and/or PCLK1 clock changes, this function
|
||||
* must be called to update structure fields. Otherwise, any
|
||||
* configuration based on this function will be incorrect.
|
||||
* @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
|
||||
* @retval None
|
||||
*/
|
||||
void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
|
||||
{
|
||||
/* Get SYSCLK frequency */
|
||||
RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
|
||||
|
||||
/* HCLK clock frequency */
|
||||
RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
|
||||
|
||||
/* PCLK1 clock frequency */
|
||||
RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return USARTx clock frequency
|
||||
* @param USARTxSource This parameter can be one of the following values:
|
||||
* @arg @ref LL_RCC_USART1_CLKSOURCE
|
||||
* @arg @ref LL_RCC_USART2_CLKSOURCE (*)
|
||||
* @arg @ref LL_RCC_USART3_CLKSOURCE (*)
|
||||
*
|
||||
* (*) value not defined in all devices.
|
||||
* @retval USART clock frequency (in Hz)
|
||||
* @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
|
||||
*/
|
||||
uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
|
||||
{
|
||||
uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
|
||||
|
||||
/* Check parameter */
|
||||
assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
|
||||
#if defined(RCC_CFGR3_USART1SW)
|
||||
if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
|
||||
{
|
||||
/* USART1CLK clock frequency */
|
||||
switch (LL_RCC_GetUSARTClockSource(USARTxSource))
|
||||
{
|
||||
case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
|
||||
usart_frequency = RCC_GetSystemClockFreq();
|
||||
break;
|
||||
|
||||
case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */
|
||||
if (LL_RCC_HSI_IsReady())
|
||||
{
|
||||
usart_frequency = HSI_VALUE;
|
||||
}
|
||||
break;
|
||||
|
||||
case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */
|
||||
if (LL_RCC_LSE_IsReady())
|
||||
{
|
||||
usart_frequency = LSE_VALUE;
|
||||
}
|
||||
break;
|
||||
|
||||
case LL_RCC_USART1_CLKSOURCE_PCLK1: /* USART1 Clock is PCLK1 */
|
||||
default:
|
||||
usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif /* RCC_CFGR3_USART1SW */
|
||||
|
||||
#if defined(RCC_CFGR3_USART2SW)
|
||||
if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
|
||||
{
|
||||
/* USART2CLK clock frequency */
|
||||
switch (LL_RCC_GetUSARTClockSource(USARTxSource))
|
||||
{
|
||||
case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
|
||||
usart_frequency = RCC_GetSystemClockFreq();
|
||||
break;
|
||||
|
||||
case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */
|
||||
if (LL_RCC_HSI_IsReady())
|
||||
{
|
||||
usart_frequency = HSI_VALUE;
|
||||
}
|
||||
break;
|
||||
|
||||
case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */
|
||||
if (LL_RCC_LSE_IsReady())
|
||||
{
|
||||
usart_frequency = LSE_VALUE;
|
||||
}
|
||||
break;
|
||||
|
||||
case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */
|
||||
default:
|
||||
usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif /* RCC_CFGR3_USART2SW */
|
||||
|
||||
#if defined(RCC_CFGR3_USART3SW)
|
||||
if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
|
||||
{
|
||||
/* USART3CLK clock frequency */
|
||||
switch (LL_RCC_GetUSARTClockSource(USARTxSource))
|
||||
{
|
||||
case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */
|
||||
usart_frequency = RCC_GetSystemClockFreq();
|
||||
break;
|
||||
|
||||
case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */
|
||||
if (LL_RCC_HSI_IsReady())
|
||||
{
|
||||
usart_frequency = HSI_VALUE;
|
||||
}
|
||||
break;
|
||||
|
||||
case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */
|
||||
if (LL_RCC_LSE_IsReady())
|
||||
{
|
||||
usart_frequency = LSE_VALUE;
|
||||
}
|
||||
break;
|
||||
|
||||
case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */
|
||||
default:
|
||||
usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* RCC_CFGR3_USART3SW */
|
||||
return usart_frequency;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return I2Cx clock frequency
|
||||
* @param I2CxSource This parameter can be one of the following values:
|
||||
* @arg @ref LL_RCC_I2C1_CLKSOURCE
|
||||
* @retval I2C clock frequency (in Hz)
|
||||
* @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
|
||||
*/
|
||||
uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
|
||||
{
|
||||
uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
|
||||
|
||||
/* Check parameter */
|
||||
assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
|
||||
|
||||
/* I2C1 CLK clock frequency */
|
||||
if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
|
||||
{
|
||||
switch (LL_RCC_GetI2CClockSource(I2CxSource))
|
||||
{
|
||||
case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
|
||||
i2c_frequency = RCC_GetSystemClockFreq();
|
||||
break;
|
||||
|
||||
case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */
|
||||
default:
|
||||
if (LL_RCC_HSI_IsReady())
|
||||
{
|
||||
i2c_frequency = HSI_VALUE;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return i2c_frequency;
|
||||
}
|
||||
|
||||
#if defined(USB)
|
||||
/**
|
||||
* @brief Return USBx clock frequency
|
||||
* @param USBxSource This parameter can be one of the following values:
|
||||
* @arg @ref LL_RCC_USB_CLKSOURCE
|
||||
* @retval USB clock frequency (in Hz)
|
||||
* @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready
|
||||
* @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
|
||||
*/
|
||||
uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
|
||||
{
|
||||
uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
|
||||
|
||||
/* Check parameter */
|
||||
assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
|
||||
|
||||
/* USBCLK clock frequency */
|
||||
switch (LL_RCC_GetUSBClockSource(USBxSource))
|
||||
{
|
||||
case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
|
||||
if (LL_RCC_PLL_IsReady())
|
||||
{
|
||||
usb_frequency = RCC_PLL_GetFreqDomain_SYS();
|
||||
}
|
||||
break;
|
||||
|
||||
#if defined(RCC_CFGR3_USBSW_HSI48)
|
||||
case LL_RCC_USB_CLKSOURCE_HSI48: /* HSI48 clock used as USB clock source */
|
||||
default:
|
||||
if (LL_RCC_HSI48_IsReady())
|
||||
{
|
||||
usb_frequency = HSI48_VALUE;
|
||||
}
|
||||
break;
|
||||
#else
|
||||
case LL_RCC_USB_CLKSOURCE_NONE: /* No clock used as USB clock source */
|
||||
default:
|
||||
usb_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
|
||||
break;
|
||||
#endif /* RCC_CFGR3_USBSW_HSI48 */
|
||||
}
|
||||
|
||||
return usb_frequency;
|
||||
}
|
||||
#endif /* USB */
|
||||
|
||||
#if defined(CEC)
|
||||
/**
|
||||
* @brief Return CECx clock frequency
|
||||
* @param CECxSource This parameter can be one of the following values:
|
||||
* @arg @ref LL_RCC_CEC_CLKSOURCE
|
||||
* @retval CEC clock frequency (in Hz)
|
||||
* @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (HSI or LSE) are not ready
|
||||
*/
|
||||
uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
|
||||
{
|
||||
uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
|
||||
|
||||
/* Check parameter */
|
||||
assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource));
|
||||
|
||||
/* CECCLK clock frequency */
|
||||
switch (LL_RCC_GetCECClockSource(CECxSource))
|
||||
{
|
||||
case LL_RCC_CEC_CLKSOURCE_HSI_DIV244: /* HSI / 244 clock used as CEC clock source */
|
||||
if (LL_RCC_HSI_IsReady())
|
||||
{
|
||||
cec_frequency = HSI_VALUE / 244U;
|
||||
}
|
||||
break;
|
||||
|
||||
case LL_RCC_CEC_CLKSOURCE_LSE: /* LSE clock used as CEC clock source */
|
||||
default:
|
||||
if (LL_RCC_LSE_IsReady())
|
||||
{
|
||||
cec_frequency = LSE_VALUE;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
return cec_frequency;
|
||||
}
|
||||
#endif /* CEC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RCC_LL_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Return SYSTEM clock frequency
|
||||
* @retval SYSTEM clock frequency (in Hz)
|
||||
*/
|
||||
uint32_t RCC_GetSystemClockFreq(void)
|
||||
{
|
||||
uint32_t frequency = 0U;
|
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
switch (LL_RCC_GetSysClkSource())
|
||||
{
|
||||
case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
|
||||
frequency = HSI_VALUE;
|
||||
break;
|
||||
|
||||
case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
|
||||
frequency = HSE_VALUE;
|
||||
break;
|
||||
|
||||
case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
|
||||
frequency = RCC_PLL_GetFreqDomain_SYS();
|
||||
break;
|
||||
|
||||
#if defined(RCC_HSI48_SUPPORT)
|
||||
case LL_RCC_SYS_CLKSOURCE_STATUS_HSI48:/* HSI48 used as system clock source */
|
||||
frequency = HSI48_VALUE;
|
||||
break;
|
||||
#endif /* RCC_HSI48_SUPPORT */
|
||||
|
||||
default:
|
||||
frequency = HSI_VALUE;
|
||||
break;
|
||||
}
|
||||
|
||||
return frequency;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return HCLK clock frequency
|
||||
* @param SYSCLK_Frequency SYSCLK clock frequency
|
||||
* @retval HCLK clock frequency (in Hz)
|
||||
*/
|
||||
uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
|
||||
{
|
||||
/* HCLK clock frequency */
|
||||
return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return PCLK1 clock frequency
|
||||
* @param HCLK_Frequency HCLK clock frequency
|
||||
* @retval PCLK1 clock frequency (in Hz)
|
||||
*/
|
||||
uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
|
||||
{
|
||||
/* PCLK1 clock frequency */
|
||||
return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
|
||||
}
|
||||
/**
|
||||
* @brief Return PLL clock frequency used for system domain
|
||||
* @retval PLL clock frequency (in Hz)
|
||||
*/
|
||||
uint32_t RCC_PLL_GetFreqDomain_SYS(void)
|
||||
{
|
||||
uint32_t pllinputfreq = 0U, pllsource = 0U;
|
||||
|
||||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */
|
||||
|
||||
/* Get PLL source */
|
||||
pllsource = LL_RCC_PLL_GetMainSource();
|
||||
|
||||
switch (pllsource)
|
||||
{
|
||||
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
|
||||
case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
|
||||
pllinputfreq = HSI_VALUE;
|
||||
#else
|
||||
case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */
|
||||
pllinputfreq = HSI_VALUE / 2U;
|
||||
#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
|
||||
break;
|
||||
|
||||
#if defined(RCC_HSI48_SUPPORT)
|
||||
case LL_RCC_PLLSOURCE_HSI48: /* HSI48 used as PLL clock source */
|
||||
pllinputfreq = HSI48_VALUE;
|
||||
break;
|
||||
#endif /* RCC_HSI48_SUPPORT */
|
||||
|
||||
case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
|
||||
pllinputfreq = HSE_VALUE;
|
||||
break;
|
||||
|
||||
default:
|
||||
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
|
||||
pllinputfreq = HSI_VALUE;
|
||||
#else
|
||||
pllinputfreq = HSI_VALUE / 2U;
|
||||
#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
|
||||
break;
|
||||
}
|
||||
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
|
||||
return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetPrediv());
|
||||
#else
|
||||
return __LL_RCC_CALC_PLLCLK_FREQ((pllinputfreq / (LL_RCC_PLL_GetPrediv() + 1U)), LL_RCC_PLL_GetMultiplicator());
|
||||
#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined(RCC) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
692
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rtc.c
Normal file
692
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rtc.c
Normal file
@@ -0,0 +1,692 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_ll_rtc.c
|
||||
* @author MCD Application Team
|
||||
* @brief RTC LL module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_ll_rtc.h"
|
||||
#include "stm32f0xx_ll_cortex.h"
|
||||
#ifdef USE_FULL_ASSERT
|
||||
#include "stm32_assert.h"
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32F0xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(RTC)
|
||||
|
||||
/** @addtogroup RTC_LL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @addtogroup RTC_LL_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
/* Default values used for prescaler */
|
||||
#define RTC_ASYNCH_PRESC_DEFAULT 0x0000007FU
|
||||
#define RTC_SYNCH_PRESC_DEFAULT 0x000000FFU
|
||||
|
||||
/* Values used for timeout */
|
||||
#define RTC_INITMODE_TIMEOUT 1000U /* 1s when tick set to 1ms */
|
||||
#define RTC_SYNCHRO_TIMEOUT 1000U /* 1s when tick set to 1ms */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup RTC_LL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_LL_RTC_HOURFORMAT(__VALUE__) (((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \
|
||||
|| ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM))
|
||||
|
||||
#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FU)
|
||||
|
||||
#define IS_LL_RTC_SYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FFFU)
|
||||
|
||||
#define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \
|
||||
|| ((__VALUE__) == LL_RTC_FORMAT_BCD))
|
||||
|
||||
#define IS_LL_RTC_TIME_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_TIME_FORMAT_AM_OR_24) \
|
||||
|| ((__VALUE__) == LL_RTC_TIME_FORMAT_PM))
|
||||
|
||||
#define IS_LL_RTC_HOUR12(__HOUR__) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))
|
||||
#define IS_LL_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U)
|
||||
#define IS_LL_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U)
|
||||
#define IS_LL_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U)
|
||||
|
||||
#define IS_LL_RTC_WEEKDAY(__VALUE__) (((__VALUE__) == LL_RTC_WEEKDAY_MONDAY) \
|
||||
|| ((__VALUE__) == LL_RTC_WEEKDAY_TUESDAY) \
|
||||
|| ((__VALUE__) == LL_RTC_WEEKDAY_WEDNESDAY) \
|
||||
|| ((__VALUE__) == LL_RTC_WEEKDAY_THURSDAY) \
|
||||
|| ((__VALUE__) == LL_RTC_WEEKDAY_FRIDAY) \
|
||||
|| ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \
|
||||
|| ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY))
|
||||
|
||||
#define IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= 1U) && ((__DAY__) <= 31U))
|
||||
|
||||
#define IS_LL_RTC_MONTH(__MONTH__) (((__MONTH__) >= 1U) && ((__MONTH__) <= 12U))
|
||||
|
||||
#define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
|
||||
|
||||
#define IS_LL_RTC_ALMA_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \
|
||||
|| ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \
|
||||
|| ((__VALUE__) == LL_RTC_ALMA_MASK_HOURS) \
|
||||
|| ((__VALUE__) == LL_RTC_ALMA_MASK_MINUTES) \
|
||||
|| ((__VALUE__) == LL_RTC_ALMA_MASK_SECONDS) \
|
||||
|| ((__VALUE__) == LL_RTC_ALMA_MASK_ALL))
|
||||
|
||||
#define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || \
|
||||
((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup RTC_LL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_LL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief De-Initializes the RTC registers to their default reset values.
|
||||
* @note This function does not reset the RTC Clock source and RTC Backup Data
|
||||
* registers.
|
||||
* @param RTCx RTC Instance
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: RTC registers are de-initialized
|
||||
* - ERROR: RTC registers are not de-initialized
|
||||
*/
|
||||
ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx)
|
||||
{
|
||||
ErrorStatus status = ERROR;
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_RTC_ALL_INSTANCE(RTCx));
|
||||
|
||||
/* Disable the write protection for RTC registers */
|
||||
LL_RTC_DisableWriteProtection(RTCx);
|
||||
|
||||
/* Set Initialization mode */
|
||||
if (LL_RTC_EnterInitMode(RTCx) != ERROR)
|
||||
{
|
||||
/* Reset TR, DR and CR registers */
|
||||
LL_RTC_WriteReg(RTCx, TR, 0x00000000U);
|
||||
#if defined(RTC_WAKEUP_SUPPORT)
|
||||
LL_RTC_WriteReg(RTCx, WUTR, RTC_WUTR_WUT);
|
||||
#endif /* RTC_WAKEUP_SUPPORT */
|
||||
LL_RTC_WriteReg(RTCx, DR, (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
|
||||
|
||||
/* Reset All CR bits except CR[2:0] */
|
||||
#if defined(RTC_WAKEUP_SUPPORT)
|
||||
LL_RTC_WriteReg(RTCx, CR, (LL_RTC_ReadReg(RTCx, CR) & RTC_CR_WUCKSEL));
|
||||
#else /* RTC_WAKEUP_SUPPORT */
|
||||
LL_RTC_WriteReg(RTCx, CR, 0x00000000U);
|
||||
#endif /* RTC_WAKEUP_SUPPORT */
|
||||
|
||||
LL_RTC_WriteReg(RTCx, PRER, (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT));
|
||||
LL_RTC_WriteReg(RTCx, ALRMAR, 0x00000000U);
|
||||
LL_RTC_WriteReg(RTCx, CALR, 0x00000000U);
|
||||
LL_RTC_WriteReg(RTCx, SHIFTR, 0x00000000U);
|
||||
LL_RTC_WriteReg(RTCx, ALRMASSR, 0x00000000U);
|
||||
|
||||
/* Reset ISR register and exit initialization mode */
|
||||
LL_RTC_WriteReg(RTCx, ISR, 0x00000000U);
|
||||
|
||||
/* Reset Tamper and alternate functions configuration register */
|
||||
LL_RTC_WriteReg(RTCx, TAFCR, 0x00000000U);
|
||||
|
||||
/* Wait till the RTC RSF flag is set */
|
||||
status = LL_RTC_WaitForSynchro(RTCx);
|
||||
}
|
||||
|
||||
/* Enable the write protection for RTC registers */
|
||||
LL_RTC_EnableWriteProtection(RTCx);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the RTC registers according to the specified parameters
|
||||
* in RTC_InitStruct.
|
||||
* @param RTCx RTC Instance
|
||||
* @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure that contains
|
||||
* the configuration information for the RTC peripheral.
|
||||
* @note The RTC Prescaler register is write protected and can be written in
|
||||
* initialization mode only.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: RTC registers are initialized
|
||||
* - ERROR: RTC registers are not initialized
|
||||
*/
|
||||
ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
|
||||
{
|
||||
ErrorStatus status = ERROR;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RTC_ALL_INSTANCE(RTCx));
|
||||
assert_param(IS_LL_RTC_HOURFORMAT(RTC_InitStruct->HourFormat));
|
||||
assert_param(IS_LL_RTC_ASYNCH_PREDIV(RTC_InitStruct->AsynchPrescaler));
|
||||
assert_param(IS_LL_RTC_SYNCH_PREDIV(RTC_InitStruct->SynchPrescaler));
|
||||
|
||||
/* Disable the write protection for RTC registers */
|
||||
LL_RTC_DisableWriteProtection(RTCx);
|
||||
|
||||
/* Set Initialization mode */
|
||||
if (LL_RTC_EnterInitMode(RTCx) != ERROR)
|
||||
{
|
||||
/* Set Hour Format */
|
||||
LL_RTC_SetHourFormat(RTCx, RTC_InitStruct->HourFormat);
|
||||
|
||||
/* Configure Synchronous and Asynchronous prescaler factor */
|
||||
LL_RTC_SetSynchPrescaler(RTCx, RTC_InitStruct->SynchPrescaler);
|
||||
LL_RTC_SetAsynchPrescaler(RTCx, RTC_InitStruct->AsynchPrescaler);
|
||||
|
||||
/* Exit Initialization mode */
|
||||
LL_RTC_DisableInitMode(RTCx);
|
||||
|
||||
status = SUCCESS;
|
||||
}
|
||||
/* Enable the write protection for RTC registers */
|
||||
LL_RTC_EnableWriteProtection(RTCx);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set each @ref LL_RTC_InitTypeDef field to default value.
|
||||
* @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure which will be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct)
|
||||
{
|
||||
/* Set RTC_InitStruct fields to default values */
|
||||
RTC_InitStruct->HourFormat = LL_RTC_HOURFORMAT_24HOUR;
|
||||
RTC_InitStruct->AsynchPrescaler = RTC_ASYNCH_PRESC_DEFAULT;
|
||||
RTC_InitStruct->SynchPrescaler = RTC_SYNCH_PRESC_DEFAULT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the RTC current time.
|
||||
* @param RTCx RTC Instance
|
||||
* @param RTC_Format This parameter can be one of the following values:
|
||||
* @arg @ref LL_RTC_FORMAT_BIN
|
||||
* @arg @ref LL_RTC_FORMAT_BCD
|
||||
* @param RTC_TimeStruct pointer to a RTC_TimeTypeDef structure that contains
|
||||
* the time configuration information for the RTC.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: RTC Time register is configured
|
||||
* - ERROR: RTC Time register is not configured
|
||||
*/
|
||||
ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
|
||||
{
|
||||
ErrorStatus status = ERROR;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RTC_ALL_INSTANCE(RTCx));
|
||||
assert_param(IS_LL_RTC_FORMAT(RTC_Format));
|
||||
|
||||
if (RTC_Format == LL_RTC_FORMAT_BIN)
|
||||
{
|
||||
if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
|
||||
{
|
||||
assert_param(IS_LL_RTC_HOUR12(RTC_TimeStruct->Hours));
|
||||
assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
|
||||
}
|
||||
else
|
||||
{
|
||||
RTC_TimeStruct->TimeFormat = 0x00U;
|
||||
assert_param(IS_LL_RTC_HOUR24(RTC_TimeStruct->Hours));
|
||||
}
|
||||
assert_param(IS_LL_RTC_MINUTES(RTC_TimeStruct->Minutes));
|
||||
assert_param(IS_LL_RTC_SECONDS(RTC_TimeStruct->Seconds));
|
||||
}
|
||||
else
|
||||
{
|
||||
if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
|
||||
{
|
||||
assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
|
||||
assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
|
||||
}
|
||||
else
|
||||
{
|
||||
RTC_TimeStruct->TimeFormat = 0x00U;
|
||||
assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
|
||||
}
|
||||
assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes)));
|
||||
assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds)));
|
||||
}
|
||||
|
||||
/* Disable the write protection for RTC registers */
|
||||
LL_RTC_DisableWriteProtection(RTCx);
|
||||
|
||||
/* Set Initialization mode */
|
||||
if (LL_RTC_EnterInitMode(RTCx) != ERROR)
|
||||
{
|
||||
/* Check the input parameters format */
|
||||
if (RTC_Format != LL_RTC_FORMAT_BIN)
|
||||
{
|
||||
LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, RTC_TimeStruct->Hours,
|
||||
RTC_TimeStruct->Minutes, RTC_TimeStruct->Seconds);
|
||||
}
|
||||
else
|
||||
{
|
||||
LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Hours),
|
||||
__LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Minutes),
|
||||
__LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Seconds));
|
||||
}
|
||||
|
||||
/* Exit Initialization mode */
|
||||
LL_RTC_DisableInitMode(RTCx);
|
||||
|
||||
/* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
|
||||
if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
|
||||
{
|
||||
status = LL_RTC_WaitForSynchro(RTCx);
|
||||
}
|
||||
else
|
||||
{
|
||||
status = SUCCESS;
|
||||
}
|
||||
}
|
||||
/* Enable the write protection for RTC registers */
|
||||
LL_RTC_EnableWriteProtection(RTCx);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set each @ref LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
|
||||
* @param RTC_TimeStruct pointer to a @ref LL_RTC_TimeTypeDef structure which will be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct)
|
||||
{
|
||||
/* Time = 00h:00min:00sec */
|
||||
RTC_TimeStruct->TimeFormat = LL_RTC_TIME_FORMAT_AM_OR_24;
|
||||
RTC_TimeStruct->Hours = 0U;
|
||||
RTC_TimeStruct->Minutes = 0U;
|
||||
RTC_TimeStruct->Seconds = 0U;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the RTC current date.
|
||||
* @param RTCx RTC Instance
|
||||
* @param RTC_Format This parameter can be one of the following values:
|
||||
* @arg @ref LL_RTC_FORMAT_BIN
|
||||
* @arg @ref LL_RTC_FORMAT_BCD
|
||||
* @param RTC_DateStruct pointer to a RTC_DateTypeDef structure that contains
|
||||
* the date configuration information for the RTC.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: RTC Day register is configured
|
||||
* - ERROR: RTC Day register is not configured
|
||||
*/
|
||||
ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
|
||||
{
|
||||
ErrorStatus status = ERROR;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RTC_ALL_INSTANCE(RTCx));
|
||||
assert_param(IS_LL_RTC_FORMAT(RTC_Format));
|
||||
|
||||
if ((RTC_Format == LL_RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10U) == 0x10U))
|
||||
{
|
||||
RTC_DateStruct->Month = (uint8_t)(RTC_DateStruct->Month & (uint8_t)~(0x10U)) + 0x0AU;
|
||||
}
|
||||
if (RTC_Format == LL_RTC_FORMAT_BIN)
|
||||
{
|
||||
assert_param(IS_LL_RTC_YEAR(RTC_DateStruct->Year));
|
||||
assert_param(IS_LL_RTC_MONTH(RTC_DateStruct->Month));
|
||||
assert_param(IS_LL_RTC_DAY(RTC_DateStruct->Day));
|
||||
}
|
||||
else
|
||||
{
|
||||
assert_param(IS_LL_RTC_YEAR(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Year)));
|
||||
assert_param(IS_LL_RTC_MONTH(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Month)));
|
||||
assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Day)));
|
||||
}
|
||||
assert_param(IS_LL_RTC_WEEKDAY(RTC_DateStruct->WeekDay));
|
||||
|
||||
/* Disable the write protection for RTC registers */
|
||||
LL_RTC_DisableWriteProtection(RTCx);
|
||||
|
||||
/* Set Initialization mode */
|
||||
if (LL_RTC_EnterInitMode(RTCx) != ERROR)
|
||||
{
|
||||
/* Check the input parameters format */
|
||||
if (RTC_Format != LL_RTC_FORMAT_BIN)
|
||||
{
|
||||
LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, RTC_DateStruct->Day, RTC_DateStruct->Month, RTC_DateStruct->Year);
|
||||
}
|
||||
else
|
||||
{
|
||||
LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Day),
|
||||
__LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Month), __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Year));
|
||||
}
|
||||
|
||||
/* Exit Initialization mode */
|
||||
LL_RTC_DisableInitMode(RTCx);
|
||||
|
||||
/* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
|
||||
if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
|
||||
{
|
||||
status = LL_RTC_WaitForSynchro(RTCx);
|
||||
}
|
||||
else
|
||||
{
|
||||
status = SUCCESS;
|
||||
}
|
||||
}
|
||||
/* Enable the write protection for RTC registers */
|
||||
LL_RTC_EnableWriteProtection(RTCx);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set each @ref LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
|
||||
* @param RTC_DateStruct pointer to a @ref LL_RTC_DateTypeDef structure which will be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct)
|
||||
{
|
||||
/* Monday, January 01 xx00 */
|
||||
RTC_DateStruct->WeekDay = LL_RTC_WEEKDAY_MONDAY;
|
||||
RTC_DateStruct->Day = 1U;
|
||||
RTC_DateStruct->Month = LL_RTC_MONTH_JANUARY;
|
||||
RTC_DateStruct->Year = 0U;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the RTC Alarm A.
|
||||
* @note The Alarm register can only be written when the corresponding Alarm
|
||||
* is disabled (Use @ref LL_RTC_ALMA_Disable function).
|
||||
* @param RTCx RTC Instance
|
||||
* @param RTC_Format This parameter can be one of the following values:
|
||||
* @arg @ref LL_RTC_FORMAT_BIN
|
||||
* @arg @ref LL_RTC_FORMAT_BCD
|
||||
* @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
|
||||
* contains the alarm configuration parameters.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: ALARMA registers are configured
|
||||
* - ERROR: ALARMA registers are not configured
|
||||
*/
|
||||
ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RTC_ALL_INSTANCE(RTCx));
|
||||
assert_param(IS_LL_RTC_FORMAT(RTC_Format));
|
||||
assert_param(IS_LL_RTC_ALMA_MASK(RTC_AlarmStruct->AlarmMask));
|
||||
assert_param(IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
|
||||
|
||||
if (RTC_Format == LL_RTC_FORMAT_BIN)
|
||||
{
|
||||
if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
|
||||
{
|
||||
assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
|
||||
assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
|
||||
}
|
||||
else
|
||||
{
|
||||
RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
|
||||
assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
|
||||
}
|
||||
assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
|
||||
assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
|
||||
|
||||
if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
|
||||
{
|
||||
assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
|
||||
}
|
||||
else
|
||||
{
|
||||
assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
|
||||
{
|
||||
assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
|
||||
assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
|
||||
}
|
||||
else
|
||||
{
|
||||
RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
|
||||
assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
|
||||
}
|
||||
|
||||
assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
|
||||
assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
|
||||
|
||||
if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
|
||||
{
|
||||
assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
|
||||
}
|
||||
else
|
||||
{
|
||||
assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
|
||||
}
|
||||
}
|
||||
|
||||
/* Disable the write protection for RTC registers */
|
||||
LL_RTC_DisableWriteProtection(RTCx);
|
||||
|
||||
/* Select weekday selection */
|
||||
if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
|
||||
{
|
||||
/* Set the date for ALARM */
|
||||
LL_RTC_ALMA_DisableWeekday(RTCx);
|
||||
if (RTC_Format != LL_RTC_FORMAT_BIN)
|
||||
{
|
||||
LL_RTC_ALMA_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
|
||||
}
|
||||
else
|
||||
{
|
||||
LL_RTC_ALMA_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set the week day for ALARM */
|
||||
LL_RTC_ALMA_EnableWeekday(RTCx);
|
||||
LL_RTC_ALMA_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
|
||||
}
|
||||
|
||||
/* Configure the Alarm register */
|
||||
if (RTC_Format != LL_RTC_FORMAT_BIN)
|
||||
{
|
||||
LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
|
||||
RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
|
||||
}
|
||||
else
|
||||
{
|
||||
LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
|
||||
__LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
|
||||
__LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
|
||||
__LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
|
||||
}
|
||||
/* Set ALARM mask */
|
||||
LL_RTC_ALMA_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
|
||||
|
||||
/* Enable the write protection for RTC registers */
|
||||
LL_RTC_EnableWriteProtection(RTCx);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
|
||||
* Day = 1st day of the month/Mask = all fields are masked).
|
||||
* @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
|
||||
{
|
||||
/* Alarm Time Settings : Time = 00h:00mn:00sec */
|
||||
RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMA_TIME_FORMAT_AM;
|
||||
RTC_AlarmStruct->AlarmTime.Hours = 0U;
|
||||
RTC_AlarmStruct->AlarmTime.Minutes = 0U;
|
||||
RTC_AlarmStruct->AlarmTime.Seconds = 0U;
|
||||
|
||||
/* Alarm Day Settings : Day = 1st day of the month */
|
||||
RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMA_DATEWEEKDAYSEL_DATE;
|
||||
RTC_AlarmStruct->AlarmDateWeekDay = 1U;
|
||||
|
||||
/* Alarm Masks Settings : Mask = all fields are not masked */
|
||||
RTC_AlarmStruct->AlarmMask = LL_RTC_ALMA_MASK_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters the RTC Initialization mode.
|
||||
* @note The RTC Initialization mode is write protected, use the
|
||||
* @ref LL_RTC_DisableWriteProtection before calling this function.
|
||||
* @param RTCx RTC Instance
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: RTC is in Init mode
|
||||
* - ERROR: RTC is not in Init mode
|
||||
*/
|
||||
ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx)
|
||||
{
|
||||
__IO uint32_t timeout = RTC_INITMODE_TIMEOUT;
|
||||
ErrorStatus status = SUCCESS;
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_RTC_ALL_INSTANCE(RTCx));
|
||||
|
||||
/* Check if the Initialization mode is set */
|
||||
if (LL_RTC_IsActiveFlag_INIT(RTCx) == 0U)
|
||||
{
|
||||
/* Set the Initialization mode */
|
||||
LL_RTC_EnableInitMode(RTCx);
|
||||
|
||||
/* Wait till RTC is in INIT state and if Time out is reached exit */
|
||||
tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
|
||||
while ((timeout != 0U) && (tmp != 1U))
|
||||
{
|
||||
if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
|
||||
{
|
||||
timeout --;
|
||||
}
|
||||
tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
|
||||
if (timeout == 0U)
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Exit the RTC Initialization mode.
|
||||
* @note When the initialization sequence is complete, the calendar restarts
|
||||
* counting after 4 RTCCLK cycles.
|
||||
* @note The RTC Initialization mode is write protected, use the
|
||||
* @ref LL_RTC_DisableWriteProtection before calling this function.
|
||||
* @param RTCx RTC Instance
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: RTC exited from in Init mode
|
||||
* - ERROR: Not applicable
|
||||
*/
|
||||
ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_RTC_ALL_INSTANCE(RTCx));
|
||||
|
||||
/* Disable initialization mode */
|
||||
LL_RTC_DisableInitMode(RTCx);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are
|
||||
* synchronized with RTC APB clock.
|
||||
* @note The RTC Resynchronization mode is write protected, use the
|
||||
* @ref LL_RTC_DisableWriteProtection before calling this function.
|
||||
* @note To read the calendar through the shadow registers after calendar
|
||||
* initialization, calendar update or after wakeup from low power modes
|
||||
* the software must first clear the RSF flag.
|
||||
* The software must then wait until it is set again before reading
|
||||
* the calendar, which means that the calendar registers have been
|
||||
* correctly copied into the RTC_TR and RTC_DR shadow registers.
|
||||
* @param RTCx RTC Instance
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: RTC registers are synchronised
|
||||
* - ERROR: RTC registers are not synchronised
|
||||
*/
|
||||
ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx)
|
||||
{
|
||||
__IO uint32_t timeout = RTC_SYNCHRO_TIMEOUT;
|
||||
ErrorStatus status = SUCCESS;
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_RTC_ALL_INSTANCE(RTCx));
|
||||
|
||||
/* Clear RSF flag */
|
||||
LL_RTC_ClearFlag_RS(RTCx);
|
||||
|
||||
/* Wait the registers to be synchronised */
|
||||
tmp = LL_RTC_IsActiveFlag_RS(RTCx);
|
||||
while ((timeout != 0U) && (tmp != 1U))
|
||||
{
|
||||
if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
|
||||
{
|
||||
timeout--;
|
||||
}
|
||||
tmp = LL_RTC_IsActiveFlag_RS(RTCx);
|
||||
if (timeout == 0U)
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return (status);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined(RTC) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
535
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_spi.c
Normal file
535
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_spi.c
Normal file
@@ -0,0 +1,535 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_ll_spi.c
|
||||
* @author MCD Application Team
|
||||
* @brief SPI LL module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_ll_spi.h"
|
||||
#include "stm32f0xx_ll_bus.h"
|
||||
#include "stm32f0xx_ll_rcc.h"
|
||||
|
||||
#ifdef USE_FULL_ASSERT
|
||||
#include "stm32_assert.h"
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
/** @addtogroup STM32F0xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (SPI1) || defined (SPI2)
|
||||
|
||||
/** @addtogroup SPI_LL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup SPI_LL_Private_Constants SPI Private Constants
|
||||
* @{
|
||||
*/
|
||||
/* SPI registers Masks */
|
||||
#define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
|
||||
SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
|
||||
SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_CRCL | \
|
||||
SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \
|
||||
SPI_CR1_BIDIMODE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup SPI_LL_Private_Macros SPI Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
|
||||
|| ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
|
||||
|| ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
|
||||
|| ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
|
||||
|
||||
#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
|
||||
|| ((__VALUE__) == LL_SPI_MODE_SLAVE))
|
||||
|
||||
#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \
|
||||
|| ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \
|
||||
|| ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \
|
||||
|| ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \
|
||||
|| ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
|
||||
|| ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \
|
||||
|| ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
|
||||
|| ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
|
||||
|| ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
|
||||
|| ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
|
||||
|| ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
|
||||
|| ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
|
||||
|| ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
|
||||
|
||||
#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
|
||||
|| ((__VALUE__) == LL_SPI_POLARITY_HIGH))
|
||||
|
||||
#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
|
||||
|| ((__VALUE__) == LL_SPI_PHASE_2EDGE))
|
||||
|
||||
#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
|
||||
|| ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
|
||||
|| ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
|
||||
|
||||
#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
|
||||
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
|
||||
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
|
||||
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
|
||||
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
|
||||
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
|
||||
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
|
||||
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
|
||||
|
||||
#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
|
||||
|| ((__VALUE__) == LL_SPI_MSB_FIRST))
|
||||
|
||||
#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
|
||||
|| ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
|
||||
|
||||
#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup SPI_LL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_LL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief De-initialize the SPI registers to their default reset values.
|
||||
* @param SPIx SPI Instance
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: SPI registers are de-initialized
|
||||
* - ERROR: SPI registers are not de-initialized
|
||||
*/
|
||||
ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
|
||||
{
|
||||
ErrorStatus status = ERROR;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_ALL_INSTANCE(SPIx));
|
||||
|
||||
#if defined(SPI1)
|
||||
if (SPIx == SPI1)
|
||||
{
|
||||
/* Force reset of SPI clock */
|
||||
LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_SPI1);
|
||||
|
||||
/* Release reset of SPI clock */
|
||||
LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_SPI1);
|
||||
|
||||
status = SUCCESS;
|
||||
}
|
||||
#endif /* SPI1 */
|
||||
#if defined(SPI2)
|
||||
if (SPIx == SPI2)
|
||||
{
|
||||
/* Force reset of SPI clock */
|
||||
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
|
||||
|
||||
/* Release reset of SPI clock */
|
||||
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
|
||||
|
||||
status = SUCCESS;
|
||||
}
|
||||
#endif /* SPI2 */
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
|
||||
* @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
|
||||
* SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
|
||||
* @param SPIx SPI Instance
|
||||
* @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
|
||||
* @retval An ErrorStatus enumeration value. (Return always SUCCESS)
|
||||
*/
|
||||
ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
|
||||
{
|
||||
ErrorStatus status = ERROR;
|
||||
|
||||
/* Check the SPI Instance SPIx*/
|
||||
assert_param(IS_SPI_ALL_INSTANCE(SPIx));
|
||||
|
||||
/* Check the SPI parameters from SPI_InitStruct*/
|
||||
assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
|
||||
assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
|
||||
assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
|
||||
assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
|
||||
assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
|
||||
assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
|
||||
assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
|
||||
assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
|
||||
assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
|
||||
|
||||
if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
|
||||
{
|
||||
/*---------------------------- SPIx CR1 Configuration ------------------------
|
||||
* Configure SPIx CR1 with parameters:
|
||||
* - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
|
||||
* - Master/Slave Mode: SPI_CR1_MSTR bit
|
||||
* - ClockPolarity: SPI_CR1_CPOL bit
|
||||
* - ClockPhase: SPI_CR1_CPHA bit
|
||||
* - NSS management: SPI_CR1_SSM bit
|
||||
* - BaudRate prescaler: SPI_CR1_BR[2:0] bits
|
||||
* - BitOrder: SPI_CR1_LSBFIRST bit
|
||||
* - CRCCalculation: SPI_CR1_CRCEN bit
|
||||
*/
|
||||
MODIFY_REG(SPIx->CR1,
|
||||
SPI_CR1_CLEAR_MASK,
|
||||
SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
|
||||
SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
|
||||
SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
|
||||
SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
|
||||
|
||||
/*---------------------------- SPIx CR2 Configuration ------------------------
|
||||
* Configure SPIx CR2 with parameters:
|
||||
* - DataWidth: DS[3:0] bits
|
||||
* - NSS management: SSOE bit
|
||||
*/
|
||||
MODIFY_REG(SPIx->CR2,
|
||||
SPI_CR2_DS | SPI_CR2_SSOE,
|
||||
SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
|
||||
|
||||
/* Set Rx FIFO to Quarter (1 Byte) in case of 8 Bits mode. No DataPacking by default */
|
||||
if (SPI_InitStruct->DataWidth < LL_SPI_DATAWIDTH_9BIT)
|
||||
{
|
||||
LL_SPI_SetRxFIFOThreshold(SPIx, LL_SPI_RX_FIFO_TH_QUARTER);
|
||||
}
|
||||
|
||||
/*---------------------------- SPIx CRCPR Configuration ----------------------
|
||||
* Configure SPIx CRCPR with parameters:
|
||||
* - CRCPoly: CRCPOLY[15:0] bits
|
||||
*/
|
||||
if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
|
||||
{
|
||||
assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
|
||||
LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
|
||||
}
|
||||
status = SUCCESS;
|
||||
}
|
||||
|
||||
#if defined (SPI_I2S_SUPPORT)
|
||||
/* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
|
||||
CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
|
||||
#endif /* SPI_I2S_SUPPORT */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set each @ref LL_SPI_InitTypeDef field to default value.
|
||||
* @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
|
||||
* whose fields will be set to default values.
|
||||
* @retval None
|
||||
*/
|
||||
void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
|
||||
{
|
||||
/* Set SPI_InitStruct fields to default values */
|
||||
SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
|
||||
SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
|
||||
SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
|
||||
SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
|
||||
SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
|
||||
SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
|
||||
SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
|
||||
SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
|
||||
SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
|
||||
SPI_InitStruct->CRCPoly = 7U;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(SPI_I2S_SUPPORT)
|
||||
/** @addtogroup I2S_LL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup I2S_LL_Private_Constants I2S Private Constants
|
||||
* @{
|
||||
*/
|
||||
/* I2S registers Masks */
|
||||
#define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
|
||||
SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
|
||||
SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
|
||||
|
||||
#define I2S_I2SPR_CLEAR_MASK 0x0002U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup I2S_LL_Private_Macros I2S Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
|
||||
|| ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
|
||||
|| ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
|
||||
|| ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
|
||||
|
||||
#define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
|
||||
|| ((__VALUE__) == LL_I2S_POLARITY_HIGH))
|
||||
|
||||
#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
|
||||
|| ((__VALUE__) == LL_I2S_STANDARD_MSB) \
|
||||
|| ((__VALUE__) == LL_I2S_STANDARD_LSB) \
|
||||
|| ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
|
||||
|| ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
|
||||
|
||||
#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
|
||||
|| ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
|
||||
|| ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
|
||||
|| ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
|
||||
|
||||
#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
|
||||
|| ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
|
||||
|
||||
#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
|
||||
&& ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
|
||||
|| ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
|
||||
|
||||
#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
|
||||
|
||||
#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
|
||||
|| ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup I2S_LL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2S_LL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief De-initialize the SPI/I2S registers to their default reset values.
|
||||
* @param SPIx SPI Instance
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: SPI registers are de-initialized
|
||||
* - ERROR: SPI registers are not de-initialized
|
||||
*/
|
||||
ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
|
||||
{
|
||||
return LL_SPI_DeInit(SPIx);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
|
||||
* @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
|
||||
* SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
|
||||
* @param SPIx SPI Instance
|
||||
* @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: SPI registers are Initialized
|
||||
* - ERROR: SPI registers are not Initialized
|
||||
*/
|
||||
ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
|
||||
{
|
||||
uint32_t i2sdiv = 2U;
|
||||
uint32_t i2sodd = 0U;
|
||||
uint32_t packetlength = 1U;
|
||||
uint32_t tmp;
|
||||
LL_RCC_ClocksTypeDef rcc_clocks;
|
||||
uint32_t sourceclock;
|
||||
ErrorStatus status = ERROR;
|
||||
|
||||
/* Check the I2S parameters */
|
||||
assert_param(IS_I2S_ALL_INSTANCE(SPIx));
|
||||
assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
|
||||
assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
|
||||
assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
|
||||
assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
|
||||
assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
|
||||
assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
|
||||
|
||||
if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
|
||||
{
|
||||
/*---------------------------- SPIx I2SCFGR Configuration --------------------
|
||||
* Configure SPIx I2SCFGR with parameters:
|
||||
* - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
|
||||
* - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
|
||||
* - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
|
||||
* - ClockPolarity: SPI_I2SCFGR_CKPOL bit
|
||||
*/
|
||||
|
||||
/* Write to SPIx I2SCFGR */
|
||||
MODIFY_REG(SPIx->I2SCFGR,
|
||||
I2S_I2SCFGR_CLEAR_MASK,
|
||||
I2S_InitStruct->Mode | I2S_InitStruct->Standard |
|
||||
I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
|
||||
SPI_I2SCFGR_I2SMOD);
|
||||
|
||||
/*---------------------------- SPIx I2SPR Configuration ----------------------
|
||||
* Configure SPIx I2SPR with parameters:
|
||||
* - MCLKOutput: SPI_I2SPR_MCKOE bit
|
||||
* - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
|
||||
*/
|
||||
|
||||
/* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
|
||||
* else, default values are used: i2sodd = 0U, i2sdiv = 2U.
|
||||
*/
|
||||
if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
|
||||
{
|
||||
/* Check the frame length (For the Prescaler computing)
|
||||
* Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
|
||||
*/
|
||||
if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
|
||||
{
|
||||
/* Packet length is 32 bits */
|
||||
packetlength = 2U;
|
||||
}
|
||||
|
||||
/* I2S Clock source is System clock: Get System Clock frequency */
|
||||
LL_RCC_GetSystemClocksFreq(&rcc_clocks);
|
||||
|
||||
/* Get the source clock value: based on System Clock value */
|
||||
sourceclock = rcc_clocks.SYSCLK_Frequency;
|
||||
|
||||
/* Compute the Real divider depending on the MCLK output state with a floating point */
|
||||
if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
|
||||
{
|
||||
/* MCLK output is enabled */
|
||||
tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* MCLK output is disabled */
|
||||
tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
|
||||
}
|
||||
|
||||
/* Remove the floating point */
|
||||
tmp = tmp / 10U;
|
||||
|
||||
/* Check the parity of the divider */
|
||||
i2sodd = (tmp & (uint16_t)0x0001U);
|
||||
|
||||
/* Compute the i2sdiv prescaler */
|
||||
i2sdiv = ((tmp - i2sodd) / 2U);
|
||||
|
||||
/* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
|
||||
i2sodd = (i2sodd << 8U);
|
||||
}
|
||||
|
||||
/* Test if the divider is 1 or 0 or greater than 0xFF */
|
||||
if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
|
||||
{
|
||||
/* Set the default values */
|
||||
i2sdiv = 2U;
|
||||
i2sodd = 0U;
|
||||
}
|
||||
|
||||
/* Write to SPIx I2SPR register the computed value */
|
||||
WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
|
||||
|
||||
status = SUCCESS;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set each @ref LL_I2S_InitTypeDef field to default value.
|
||||
* @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
|
||||
* whose fields will be set to default values.
|
||||
* @retval None
|
||||
*/
|
||||
void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
|
||||
{
|
||||
/*--------------- Reset I2S init structure parameters values -----------------*/
|
||||
I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
|
||||
I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
|
||||
I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
|
||||
I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
|
||||
I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
|
||||
I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set linear and parity prescaler.
|
||||
* @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
|
||||
* Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
|
||||
* @param SPIx SPI Instance
|
||||
* @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF.
|
||||
* @param PrescalerParity This parameter can be one of the following values:
|
||||
* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
|
||||
* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
|
||||
* @retval None
|
||||
*/
|
||||
void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
|
||||
{
|
||||
/* Check the I2S parameters */
|
||||
assert_param(IS_I2S_ALL_INSTANCE(SPIx));
|
||||
assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
|
||||
assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
|
||||
|
||||
/* Write to SPIx I2SPR */
|
||||
MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* SPI_I2S_SUPPORT */
|
||||
|
||||
#endif /* defined (SPI1) || defined (SPI2) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
1163
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_tim.c
Normal file
1163
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_tim.c
Normal file
File diff suppressed because it is too large
Load Diff
514
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_usart.c
Normal file
514
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_usart.c
Normal file
@@ -0,0 +1,514 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_ll_usart.c
|
||||
* @author MCD Application Team
|
||||
* @brief USART LL module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_ll_usart.h"
|
||||
#include "stm32f0xx_ll_rcc.h"
|
||||
#include "stm32f0xx_ll_bus.h"
|
||||
#ifdef USE_FULL_ASSERT
|
||||
#include "stm32_assert.h"
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
/** @addtogroup STM32F0xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(USART1) || defined(USART2) || defined(USART3) || defined(UART4) || defined(UART5) \
|
||||
|| defined(USART6) || defined(USART7) || defined(USART8)
|
||||
|
||||
/** @addtogroup USART_LL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @addtogroup USART_LL_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Definition of default baudrate value used for USART initialisation */
|
||||
#define USART_DEFAULT_BAUDRATE (9600U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup USART_LL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
|
||||
* divided by the smallest oversampling used on the USART (i.e. 8) */
|
||||
#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 6000000U)
|
||||
|
||||
/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
|
||||
#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
|
||||
|
||||
#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
|
||||
|| ((__VALUE__) == LL_USART_DIRECTION_RX) \
|
||||
|| ((__VALUE__) == LL_USART_DIRECTION_TX) \
|
||||
|| ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
|
||||
|
||||
#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
|
||||
|| ((__VALUE__) == LL_USART_PARITY_EVEN) \
|
||||
|| ((__VALUE__) == LL_USART_PARITY_ODD))
|
||||
|
||||
#if defined(USART_7BITS_SUPPORT)
|
||||
#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
|
||||
|| ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
|
||||
|| ((__VALUE__) == LL_USART_DATAWIDTH_9B))
|
||||
#else
|
||||
#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \
|
||||
|| ((__VALUE__) == LL_USART_DATAWIDTH_9B))
|
||||
#endif /* USART_7BITS_SUPPORT */
|
||||
|
||||
#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
|
||||
|| ((__VALUE__) == LL_USART_OVERSAMPLING_8))
|
||||
|
||||
#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
|
||||
|| ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
|
||||
|
||||
#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
|
||||
|| ((__VALUE__) == LL_USART_PHASE_2EDGE))
|
||||
|
||||
#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
|
||||
|| ((__VALUE__) == LL_USART_POLARITY_HIGH))
|
||||
|
||||
#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
|
||||
|| ((__VALUE__) == LL_USART_CLOCK_ENABLE))
|
||||
|
||||
#if defined(USART_SMARTCARD_SUPPORT)
|
||||
#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
|
||||
|| ((__VALUE__) == LL_USART_STOPBITS_1) \
|
||||
|| ((__VALUE__) == LL_USART_STOPBITS_1_5) \
|
||||
|| ((__VALUE__) == LL_USART_STOPBITS_2))
|
||||
#else
|
||||
#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_1) \
|
||||
|| ((__VALUE__) == LL_USART_STOPBITS_2))
|
||||
#endif /* USART_SMARTCARD_SUPPORT */
|
||||
|
||||
#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
|
||||
|| ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
|
||||
|| ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
|
||||
|| ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup USART_LL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USART_LL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief De-initialize USART registers (Registers restored to their default values).
|
||||
* @param USARTx USART Instance
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: USART registers are de-initialized
|
||||
* - ERROR: USART registers are not de-initialized
|
||||
*/
|
||||
ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_UART_INSTANCE(USARTx));
|
||||
|
||||
if (USARTx == USART1)
|
||||
{
|
||||
/* Force reset of USART clock */
|
||||
LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_USART1);
|
||||
|
||||
/* Release reset of USART clock */
|
||||
LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_USART1);
|
||||
}
|
||||
#if defined(USART2)
|
||||
else if (USARTx == USART2)
|
||||
{
|
||||
/* Force reset of USART clock */
|
||||
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
|
||||
|
||||
/* Release reset of USART clock */
|
||||
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
|
||||
}
|
||||
#endif /* USART2 */
|
||||
#if defined(USART3)
|
||||
else if (USARTx == USART3)
|
||||
{
|
||||
/* Force reset of USART clock */
|
||||
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
|
||||
|
||||
/* Release reset of USART clock */
|
||||
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
|
||||
}
|
||||
#endif /* USART3 */
|
||||
#if defined(USART4)
|
||||
else if (USARTx == USART4)
|
||||
{
|
||||
/* Force reset of USART clock */
|
||||
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART4);
|
||||
|
||||
/* Release reset of USART clock */
|
||||
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART4);
|
||||
}
|
||||
#endif /* USART4 */
|
||||
#if defined(USART5)
|
||||
else if (USARTx == USART5)
|
||||
{
|
||||
/* Force reset of USART clock */
|
||||
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART5);
|
||||
|
||||
/* Release reset of USART clock */
|
||||
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART5);
|
||||
}
|
||||
#endif /* USART5 */
|
||||
#if defined(USART6)
|
||||
else if (USARTx == USART6)
|
||||
{
|
||||
/* Force reset of USART clock */
|
||||
LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_USART6);
|
||||
|
||||
/* Release reset of USART clock */
|
||||
LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_USART6);
|
||||
}
|
||||
#endif /* USART6 */
|
||||
#if defined(USART7)
|
||||
else if (USARTx == USART7)
|
||||
{
|
||||
/* Force reset of USART clock */
|
||||
LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_USART7);
|
||||
|
||||
/* Release reset of USART clock */
|
||||
LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_USART7);
|
||||
}
|
||||
#endif /* USART7 */
|
||||
#if defined(USART8)
|
||||
else if (USARTx == USART8)
|
||||
{
|
||||
/* Force reset of USART clock */
|
||||
LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_USART8);
|
||||
|
||||
/* Release reset of USART clock */
|
||||
LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_USART8);
|
||||
}
|
||||
#endif /* USART8 */
|
||||
else
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
|
||||
return (status);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize USART registers according to the specified
|
||||
* parameters in USART_InitStruct.
|
||||
* @note As some bits in USART configuration registers can only be written when
|
||||
* the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
|
||||
* this function. Otherwise, ERROR result will be returned.
|
||||
* @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
|
||||
* @param USARTx USART Instance
|
||||
* @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure
|
||||
* that contains the configuration information for the specified USART peripheral.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: USART registers are initialized according to USART_InitStruct content
|
||||
* - ERROR: Problem occurred during USART Registers initialization
|
||||
*/
|
||||
ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct)
|
||||
{
|
||||
ErrorStatus status = ERROR;
|
||||
uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
|
||||
#if defined(USART2)||defined(USART3)||defined(USART4)
|
||||
LL_RCC_ClocksTypeDef RCC_Clocks;
|
||||
#endif /* USART2 ||USART3 || USART4 */
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_UART_INSTANCE(USARTx));
|
||||
assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
|
||||
assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
|
||||
assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
|
||||
assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
|
||||
assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
|
||||
assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
|
||||
assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
|
||||
|
||||
/* USART needs to be in disabled state, in order to be able to configure some bits in
|
||||
CRx registers */
|
||||
if (LL_USART_IsEnabled(USARTx) == 0U)
|
||||
{
|
||||
/*---------------------------- USART CR1 Configuration ---------------------
|
||||
* Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
|
||||
* - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value
|
||||
* - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
|
||||
* - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
|
||||
* - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
|
||||
*/
|
||||
MODIFY_REG(USARTx->CR1,
|
||||
(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
|
||||
USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
|
||||
(USART_InitStruct->DataWidth | USART_InitStruct->Parity |
|
||||
USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
|
||||
|
||||
/*---------------------------- USART CR2 Configuration ---------------------
|
||||
* Configure USARTx CR2 (Stop bits) with parameters:
|
||||
* - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
|
||||
* - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
|
||||
*/
|
||||
LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
|
||||
|
||||
/*---------------------------- USART CR3 Configuration ---------------------
|
||||
* Configure USARTx CR3 (Hardware Flow Control) with parameters:
|
||||
* - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to
|
||||
* USART_InitStruct->HardwareFlowControl value.
|
||||
*/
|
||||
LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
|
||||
|
||||
/*---------------------------- USART BRR Configuration ---------------------
|
||||
* Retrieve Clock frequency used for USART Peripheral
|
||||
*/
|
||||
if (USARTx == USART1)
|
||||
{
|
||||
periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE);
|
||||
}
|
||||
#if defined(USART2)
|
||||
else if (USARTx == USART2)
|
||||
{
|
||||
#if defined(RCC_CFGR3_USART2SW)
|
||||
periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE);
|
||||
#else
|
||||
/* USART2 clock is PCLK */
|
||||
LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
|
||||
periphclk = RCC_Clocks.PCLK1_Frequency;
|
||||
#endif /* USART2 Clock selector flag */
|
||||
}
|
||||
#endif /* USART2 */
|
||||
#if defined(USART3)
|
||||
else if (USARTx == USART3)
|
||||
{
|
||||
#if defined(RCC_CFGR3_USART3SW)
|
||||
periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART3_CLKSOURCE);
|
||||
#else
|
||||
/* USART3 clock is PCLK */
|
||||
LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
|
||||
periphclk = RCC_Clocks.PCLK1_Frequency;
|
||||
#endif /* USART3 Clock selector flag */
|
||||
}
|
||||
#endif /* USART3 */
|
||||
#if defined(USART4)
|
||||
else if (USARTx == USART4)
|
||||
{
|
||||
/* USART4 clock is PCLK1 */
|
||||
LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
|
||||
periphclk = RCC_Clocks.PCLK1_Frequency;
|
||||
}
|
||||
#endif /* USART4 */
|
||||
#if defined(USART5)
|
||||
else if (USARTx == USART5)
|
||||
{
|
||||
/* USART5 clock is PCLK1 */
|
||||
LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
|
||||
periphclk = RCC_Clocks.PCLK1_Frequency;
|
||||
}
|
||||
#endif /* USART5 */
|
||||
#if defined(USART6)
|
||||
else if (USARTx == USART6)
|
||||
{
|
||||
/* USART6 clock is PCLK1 */
|
||||
LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
|
||||
periphclk = RCC_Clocks.PCLK1_Frequency;
|
||||
}
|
||||
#endif /* USART6 */
|
||||
#if defined(USART7)
|
||||
else if (USARTx == USART7)
|
||||
{
|
||||
/* USART7 clock is PCLK */
|
||||
LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
|
||||
periphclk = RCC_Clocks.PCLK1_Frequency;
|
||||
}
|
||||
#endif /* USART7 */
|
||||
#if defined(USART8)
|
||||
else if (USARTx == USART8)
|
||||
{
|
||||
/* USART8 clock is PCLK */
|
||||
LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
|
||||
periphclk = RCC_Clocks.PCLK1_Frequency;
|
||||
}
|
||||
#endif /* USART8 */
|
||||
else
|
||||
{
|
||||
/* Nothing to do, as error code is already assigned to ERROR value */
|
||||
}
|
||||
|
||||
/* Configure the USART Baud Rate :
|
||||
- valid baud rate value (different from 0) is required
|
||||
- Peripheral clock as returned by RCC service, should be valid (different from 0).
|
||||
*/
|
||||
if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
|
||||
&& (USART_InitStruct->BaudRate != 0U))
|
||||
{
|
||||
status = SUCCESS;
|
||||
LL_USART_SetBaudRate(USARTx,
|
||||
periphclk,
|
||||
USART_InitStruct->OverSampling,
|
||||
USART_InitStruct->BaudRate);
|
||||
|
||||
/* Check BRR is greater than or equal to 16d */
|
||||
assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
|
||||
}
|
||||
}
|
||||
/* Endif (=> USART not in Disabled state => return ERROR) */
|
||||
|
||||
return (status);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set each @ref LL_USART_InitTypeDef field to default value.
|
||||
* @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
|
||||
* whose fields will be set to default values.
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
|
||||
{
|
||||
/* Set USART_InitStruct fields to default values */
|
||||
USART_InitStruct->BaudRate = USART_DEFAULT_BAUDRATE;
|
||||
USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B;
|
||||
USART_InitStruct->StopBits = LL_USART_STOPBITS_1;
|
||||
USART_InitStruct->Parity = LL_USART_PARITY_NONE ;
|
||||
USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX;
|
||||
USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
|
||||
USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize USART Clock related settings according to the
|
||||
* specified parameters in the USART_ClockInitStruct.
|
||||
* @note As some bits in USART configuration registers can only be written when
|
||||
* the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
|
||||
* this function. Otherwise, ERROR result will be returned.
|
||||
* @param USARTx USART Instance
|
||||
* @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
|
||||
* that contains the Clock configuration information for the specified USART peripheral.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: USART registers related to Clock settings are initialized according
|
||||
* to USART_ClockInitStruct content
|
||||
* - ERROR: Problem occurred during USART Registers initialization
|
||||
*/
|
||||
ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
|
||||
/* Check USART Instance and Clock signal output parameters */
|
||||
assert_param(IS_UART_INSTANCE(USARTx));
|
||||
assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
|
||||
|
||||
/* USART needs to be in disabled state, in order to be able to configure some bits in
|
||||
CRx registers */
|
||||
if (LL_USART_IsEnabled(USARTx) == 0U)
|
||||
{
|
||||
/* If USART Clock signal is disabled */
|
||||
if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
|
||||
{
|
||||
/* Deactivate Clock signal delivery :
|
||||
* - Disable Clock Output: USART_CR2_CLKEN cleared
|
||||
*/
|
||||
LL_USART_DisableSCLKOutput(USARTx);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Ensure USART instance is USART capable */
|
||||
assert_param(IS_USART_INSTANCE(USARTx));
|
||||
|
||||
/* Check clock related parameters */
|
||||
assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
|
||||
assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
|
||||
assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
|
||||
|
||||
/*---------------------------- USART CR2 Configuration -----------------------
|
||||
* Configure USARTx CR2 (Clock signal related bits) with parameters:
|
||||
* - Enable Clock Output: USART_CR2_CLKEN set
|
||||
* - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
|
||||
* - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
|
||||
* - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
|
||||
*/
|
||||
MODIFY_REG(USARTx->CR2,
|
||||
USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
|
||||
USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
|
||||
USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
|
||||
}
|
||||
}
|
||||
/* Else (USART not in Disabled state => return ERROR */
|
||||
else
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
|
||||
return (status);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
|
||||
* @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
|
||||
* whose fields will be set to default values.
|
||||
* @retval None
|
||||
*/
|
||||
void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
|
||||
{
|
||||
/* Set LL_USART_ClockInitStruct fields with default values */
|
||||
USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE;
|
||||
USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput =
|
||||
LL_USART_CLOCK_DISABLE */
|
||||
USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput =
|
||||
LL_USART_CLOCK_DISABLE */
|
||||
USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput =
|
||||
LL_USART_CLOCK_DISABLE */
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* USART1 || USART2 || USART3 || UART4 || UART5 || USART6 || USART7 || USART8 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
|
||||
915
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_usb.c
Normal file
915
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_usb.c
Normal file
@@ -0,0 +1,915 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_ll_usb.c
|
||||
* @author MCD Application Team
|
||||
* @brief USB Low Layer HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the USB Peripheral Controller:
|
||||
* + Initialization/de-initialization functions
|
||||
* + I/O operation functions
|
||||
* + Peripheral Control functions
|
||||
* + Peripheral State functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) Fill parameters of Init structure in USB_CfgTypeDef structure.
|
||||
|
||||
(#) Call USB_CoreInit() API to initialize the USB Core peripheral.
|
||||
|
||||
(#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
|
||||
|
||||
@endverbatim
|
||||
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_LL_USB_DRIVER
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)
|
||||
#if defined (USB)
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the USB Core
|
||||
* @param USBx USB Instance
|
||||
* @param cfg pointer to a USB_CfgTypeDef structure that contains
|
||||
* the configuration information for the specified USBx peripheral.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(USBx);
|
||||
UNUSED(cfg);
|
||||
|
||||
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
|
||||
only by USB OTG FS peripheral.
|
||||
- This function is added to ensure compatibility across platforms.
|
||||
*/
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_EnableGlobalInt
|
||||
* Enables the controller's Global Int in the AHB Config reg
|
||||
* @param USBx Selected device
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx)
|
||||
{
|
||||
uint32_t winterruptmask;
|
||||
|
||||
/* Clear pending interrupts */
|
||||
USBx->ISTR = 0U;
|
||||
|
||||
/* Set winterruptmask variable */
|
||||
winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
|
||||
USB_CNTR_SUSPM | USB_CNTR_ERRM |
|
||||
USB_CNTR_SOFM | USB_CNTR_ESOFM |
|
||||
USB_CNTR_RESETM | USB_CNTR_L1REQM;
|
||||
|
||||
/* Set interrupt mask */
|
||||
USBx->CNTR = (uint16_t)winterruptmask;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_DisableGlobalInt
|
||||
* Disable the controller's Global Int in the AHB Config reg
|
||||
* @param USBx Selected device
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx)
|
||||
{
|
||||
uint32_t winterruptmask;
|
||||
|
||||
/* Set winterruptmask variable */
|
||||
winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
|
||||
USB_CNTR_SUSPM | USB_CNTR_ERRM |
|
||||
USB_CNTR_SOFM | USB_CNTR_ESOFM |
|
||||
USB_CNTR_RESETM | USB_CNTR_L1REQM;
|
||||
|
||||
/* Clear interrupt mask */
|
||||
USBx->CNTR &= (uint16_t)(~winterruptmask);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_SetCurrentMode Set functional mode
|
||||
* @param USBx Selected device
|
||||
* @param mode current core mode
|
||||
* This parameter can be one of the these values:
|
||||
* @arg USB_DEVICE_MODE Peripheral mode
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(USBx);
|
||||
UNUSED(mode);
|
||||
|
||||
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
|
||||
only by USB OTG FS peripheral.
|
||||
- This function is added to ensure compatibility across platforms.
|
||||
*/
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_DevInit Initializes the USB controller registers
|
||||
* for device mode
|
||||
* @param USBx Selected device
|
||||
* @param cfg pointer to a USB_CfgTypeDef structure that contains
|
||||
* the configuration information for the specified USBx peripheral.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(cfg);
|
||||
|
||||
/* Init Device */
|
||||
/* CNTR_FRES = 1 */
|
||||
USBx->CNTR = (uint16_t)USB_CNTR_FRES;
|
||||
|
||||
/* CNTR_FRES = 0 */
|
||||
USBx->CNTR = 0U;
|
||||
|
||||
/* Clear pending interrupts */
|
||||
USBx->ISTR = 0U;
|
||||
|
||||
/*Set Btable Address*/
|
||||
USBx->BTABLE = BTABLE_ADDRESS;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_FlushTxFifo : Flush a Tx FIFO
|
||||
* @param USBx : Selected device
|
||||
* @param num : FIFO number
|
||||
* This parameter can be a value from 1 to 15
|
||||
15 means Flush all Tx FIFOs
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef const *USBx, uint32_t num)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(USBx);
|
||||
UNUSED(num);
|
||||
|
||||
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
|
||||
only by USB OTG FS peripheral.
|
||||
- This function is added to ensure compatibility across platforms.
|
||||
*/
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_FlushRxFifo : Flush Rx FIFO
|
||||
* @param USBx : Selected device
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef const *USBx)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(USBx);
|
||||
|
||||
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
|
||||
only by USB OTG FS peripheral.
|
||||
- This function is added to ensure compatibility across platforms.
|
||||
*/
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
#if defined (HAL_PCD_MODULE_ENABLED)
|
||||
/**
|
||||
* @brief Activate and configure an endpoint
|
||||
* @param USBx Selected device
|
||||
* @param ep pointer to endpoint structure
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
|
||||
{
|
||||
HAL_StatusTypeDef ret = HAL_OK;
|
||||
uint16_t wEpRegVal;
|
||||
|
||||
wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK;
|
||||
|
||||
/* initialize Endpoint */
|
||||
switch (ep->type)
|
||||
{
|
||||
case EP_TYPE_CTRL:
|
||||
wEpRegVal |= USB_EP_CONTROL;
|
||||
break;
|
||||
|
||||
case EP_TYPE_BULK:
|
||||
wEpRegVal |= USB_EP_BULK;
|
||||
break;
|
||||
|
||||
case EP_TYPE_INTR:
|
||||
wEpRegVal |= USB_EP_INTERRUPT;
|
||||
break;
|
||||
|
||||
case EP_TYPE_ISOC:
|
||||
wEpRegVal |= USB_EP_ISOCHRONOUS;
|
||||
break;
|
||||
|
||||
default:
|
||||
ret = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
PCD_SET_ENDPOINT(USBx, ep->num, (wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX));
|
||||
|
||||
PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num);
|
||||
|
||||
if (ep->doublebuffer == 0U)
|
||||
{
|
||||
if (ep->is_in != 0U)
|
||||
{
|
||||
/*Set the endpoint Transmit buffer address */
|
||||
PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress);
|
||||
PCD_CLEAR_TX_DTOG(USBx, ep->num);
|
||||
|
||||
if (ep->type != EP_TYPE_ISOC)
|
||||
{
|
||||
/* Configure NAK status for the Endpoint */
|
||||
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Configure TX Endpoint to disabled state */
|
||||
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set the endpoint Receive buffer address */
|
||||
PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress);
|
||||
|
||||
/* Set the endpoint Receive buffer counter */
|
||||
PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket);
|
||||
PCD_CLEAR_RX_DTOG(USBx, ep->num);
|
||||
|
||||
if (ep->num == 0U)
|
||||
{
|
||||
/* Configure VALID status for EP0 */
|
||||
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Configure NAK status for OUT Endpoint */
|
||||
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_NAK);
|
||||
}
|
||||
}
|
||||
}
|
||||
#if (USE_USB_DOUBLE_BUFFER == 1U)
|
||||
/* Double Buffer */
|
||||
else
|
||||
{
|
||||
if (ep->type == EP_TYPE_BULK)
|
||||
{
|
||||
/* Set bulk endpoint as double buffered */
|
||||
PCD_SET_BULK_EP_DBUF(USBx, ep->num);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set the ISOC endpoint in double buffer mode */
|
||||
PCD_CLEAR_EP_KIND(USBx, ep->num);
|
||||
}
|
||||
|
||||
/* Set buffer address for double buffered mode */
|
||||
PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1);
|
||||
|
||||
if (ep->is_in == 0U)
|
||||
{
|
||||
/* Clear the data toggle bits for the endpoint IN/OUT */
|
||||
PCD_CLEAR_RX_DTOG(USBx, ep->num);
|
||||
PCD_CLEAR_TX_DTOG(USBx, ep->num);
|
||||
|
||||
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
|
||||
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear the data toggle bits for the endpoint IN/OUT */
|
||||
PCD_CLEAR_RX_DTOG(USBx, ep->num);
|
||||
PCD_CLEAR_TX_DTOG(USBx, ep->num);
|
||||
|
||||
if (ep->type != EP_TYPE_ISOC)
|
||||
{
|
||||
/* Configure NAK status for the Endpoint */
|
||||
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Configure TX Endpoint to disabled state */
|
||||
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
|
||||
}
|
||||
|
||||
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
|
||||
}
|
||||
}
|
||||
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief De-activate and de-initialize an endpoint
|
||||
* @param USBx Selected device
|
||||
* @param ep pointer to endpoint structure
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
|
||||
{
|
||||
if (ep->doublebuffer == 0U)
|
||||
{
|
||||
if (ep->is_in != 0U)
|
||||
{
|
||||
PCD_CLEAR_TX_DTOG(USBx, ep->num);
|
||||
|
||||
/* Configure DISABLE status for the Endpoint */
|
||||
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
PCD_CLEAR_RX_DTOG(USBx, ep->num);
|
||||
|
||||
/* Configure DISABLE status for the Endpoint */
|
||||
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
|
||||
}
|
||||
}
|
||||
#if (USE_USB_DOUBLE_BUFFER == 1U)
|
||||
/* Double Buffer */
|
||||
else
|
||||
{
|
||||
if (ep->is_in == 0U)
|
||||
{
|
||||
/* Clear the data toggle bits for the endpoint IN/OUT*/
|
||||
PCD_CLEAR_RX_DTOG(USBx, ep->num);
|
||||
PCD_CLEAR_TX_DTOG(USBx, ep->num);
|
||||
|
||||
/* Reset value of the data toggle bits for the endpoint out*/
|
||||
PCD_TX_DTOG(USBx, ep->num);
|
||||
|
||||
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
|
||||
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear the data toggle bits for the endpoint IN/OUT*/
|
||||
PCD_CLEAR_RX_DTOG(USBx, ep->num);
|
||||
PCD_CLEAR_TX_DTOG(USBx, ep->num);
|
||||
PCD_RX_DTOG(USBx, ep->num);
|
||||
|
||||
/* Configure DISABLE status for the Endpoint*/
|
||||
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
|
||||
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
|
||||
}
|
||||
}
|
||||
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_EPStartXfer setup and starts a transfer over an EP
|
||||
* @param USBx Selected device
|
||||
* @param ep pointer to endpoint structure
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
|
||||
{
|
||||
uint32_t len;
|
||||
#if (USE_USB_DOUBLE_BUFFER == 1U)
|
||||
uint16_t pmabuffer;
|
||||
uint16_t wEPVal;
|
||||
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
|
||||
|
||||
/* IN endpoint */
|
||||
if (ep->is_in == 1U)
|
||||
{
|
||||
/*Multi packet transfer*/
|
||||
if (ep->xfer_len > ep->maxpacket)
|
||||
{
|
||||
len = ep->maxpacket;
|
||||
}
|
||||
else
|
||||
{
|
||||
len = ep->xfer_len;
|
||||
}
|
||||
|
||||
/* configure and validate Tx endpoint */
|
||||
if (ep->doublebuffer == 0U)
|
||||
{
|
||||
USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len);
|
||||
PCD_SET_EP_TX_CNT(USBx, ep->num, len);
|
||||
}
|
||||
#if (USE_USB_DOUBLE_BUFFER == 1U)
|
||||
else
|
||||
{
|
||||
/* double buffer bulk management */
|
||||
if (ep->type == EP_TYPE_BULK)
|
||||
{
|
||||
if (ep->xfer_len_db > ep->maxpacket)
|
||||
{
|
||||
/* enable double buffer */
|
||||
PCD_SET_BULK_EP_DBUF(USBx, ep->num);
|
||||
|
||||
/* each Time to write in PMA xfer_len_db will */
|
||||
ep->xfer_len_db -= len;
|
||||
|
||||
/* Fill the two first buffer in the Buffer0 & Buffer1 */
|
||||
if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
|
||||
{
|
||||
/* Set the Double buffer counter for pmabuffer1 */
|
||||
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
|
||||
pmabuffer = ep->pmaaddr1;
|
||||
|
||||
/* Write the user buffer to USB PMA */
|
||||
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
|
||||
ep->xfer_buff += len;
|
||||
|
||||
if (ep->xfer_len_db > ep->maxpacket)
|
||||
{
|
||||
ep->xfer_len_db -= len;
|
||||
}
|
||||
else
|
||||
{
|
||||
len = ep->xfer_len_db;
|
||||
ep->xfer_len_db = 0U;
|
||||
}
|
||||
|
||||
/* Set the Double buffer counter for pmabuffer0 */
|
||||
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
|
||||
pmabuffer = ep->pmaaddr0;
|
||||
|
||||
/* Write the user buffer to USB PMA */
|
||||
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set the Double buffer counter for pmabuffer0 */
|
||||
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
|
||||
pmabuffer = ep->pmaaddr0;
|
||||
|
||||
/* Write the user buffer to USB PMA */
|
||||
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
|
||||
ep->xfer_buff += len;
|
||||
|
||||
if (ep->xfer_len_db > ep->maxpacket)
|
||||
{
|
||||
ep->xfer_len_db -= len;
|
||||
}
|
||||
else
|
||||
{
|
||||
len = ep->xfer_len_db;
|
||||
ep->xfer_len_db = 0U;
|
||||
}
|
||||
|
||||
/* Set the Double buffer counter for pmabuffer1 */
|
||||
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
|
||||
pmabuffer = ep->pmaaddr1;
|
||||
|
||||
/* Write the user buffer to USB PMA */
|
||||
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
|
||||
}
|
||||
}
|
||||
/* auto Switch to single buffer mode when transfer <Mps no need to manage in double buffer */
|
||||
else
|
||||
{
|
||||
len = ep->xfer_len_db;
|
||||
|
||||
/* disable double buffer mode for Bulk endpoint */
|
||||
PCD_CLEAR_BULK_EP_DBUF(USBx, ep->num);
|
||||
|
||||
/* Set Tx count with nbre of byte to be transmitted */
|
||||
PCD_SET_EP_TX_CNT(USBx, ep->num, len);
|
||||
pmabuffer = ep->pmaaddr0;
|
||||
|
||||
/* Write the user buffer to USB PMA */
|
||||
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
|
||||
}
|
||||
}
|
||||
else /* manage isochronous double buffer IN mode */
|
||||
{
|
||||
/* each Time to write in PMA xfer_len_db will */
|
||||
ep->xfer_len_db -= len;
|
||||
|
||||
/* Fill the data buffer */
|
||||
if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
|
||||
{
|
||||
/* Set the Double buffer counter for pmabuffer1 */
|
||||
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
|
||||
pmabuffer = ep->pmaaddr1;
|
||||
|
||||
/* Write the user buffer to USB PMA */
|
||||
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set the Double buffer counter for pmabuffer0 */
|
||||
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
|
||||
pmabuffer = ep->pmaaddr0;
|
||||
|
||||
/* Write the user buffer to USB PMA */
|
||||
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
|
||||
|
||||
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID);
|
||||
}
|
||||
else /* OUT endpoint */
|
||||
{
|
||||
if (ep->doublebuffer == 0U)
|
||||
{
|
||||
/* Multi packet transfer */
|
||||
if (ep->xfer_len > ep->maxpacket)
|
||||
{
|
||||
len = ep->maxpacket;
|
||||
ep->xfer_len -= len;
|
||||
}
|
||||
else
|
||||
{
|
||||
len = ep->xfer_len;
|
||||
ep->xfer_len = 0U;
|
||||
}
|
||||
/* configure and validate Rx endpoint */
|
||||
PCD_SET_EP_RX_CNT(USBx, ep->num, len);
|
||||
}
|
||||
#if (USE_USB_DOUBLE_BUFFER == 1U)
|
||||
else
|
||||
{
|
||||
/* First Transfer Coming From HAL_PCD_EP_Receive & From ISR */
|
||||
/* Set the Double buffer counter */
|
||||
if (ep->type == EP_TYPE_BULK)
|
||||
{
|
||||
PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket);
|
||||
|
||||
/* Coming from ISR */
|
||||
if (ep->xfer_count != 0U)
|
||||
{
|
||||
/* update last value to check if there is blocking state */
|
||||
wEPVal = PCD_GET_ENDPOINT(USBx, ep->num);
|
||||
|
||||
/*Blocking State */
|
||||
if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) ||
|
||||
(((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U)))
|
||||
{
|
||||
PCD_FREE_USER_BUFFER(USBx, ep->num, 0U);
|
||||
}
|
||||
}
|
||||
}
|
||||
/* iso out double */
|
||||
else if (ep->type == EP_TYPE_ISOC)
|
||||
{
|
||||
/* Multi packet transfer */
|
||||
if (ep->xfer_len > ep->maxpacket)
|
||||
{
|
||||
len = ep->maxpacket;
|
||||
ep->xfer_len -= len;
|
||||
}
|
||||
else
|
||||
{
|
||||
len = ep->xfer_len;
|
||||
ep->xfer_len = 0U;
|
||||
}
|
||||
PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len);
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
|
||||
|
||||
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief USB_EPSetStall set a stall condition over an EP
|
||||
* @param USBx Selected device
|
||||
* @param ep pointer to endpoint structure
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
|
||||
{
|
||||
if (ep->is_in != 0U)
|
||||
{
|
||||
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL);
|
||||
}
|
||||
else
|
||||
{
|
||||
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL);
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_EPClearStall Clear a stall condition over an EP
|
||||
* @param USBx Selected device
|
||||
* @param ep pointer to endpoint structure
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
|
||||
{
|
||||
if (ep->doublebuffer == 0U)
|
||||
{
|
||||
if (ep->is_in != 0U)
|
||||
{
|
||||
PCD_CLEAR_TX_DTOG(USBx, ep->num);
|
||||
|
||||
if (ep->type != EP_TYPE_ISOC)
|
||||
{
|
||||
/* Configure NAK status for the Endpoint */
|
||||
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
PCD_CLEAR_RX_DTOG(USBx, ep->num);
|
||||
|
||||
/* Configure VALID status for the Endpoint */
|
||||
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
|
||||
}
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_EPStoptXfer Stop transfer on an EP
|
||||
* @param USBx usb device instance
|
||||
* @param ep pointer to endpoint structure
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef USB_EPStopXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
|
||||
{
|
||||
/* IN endpoint */
|
||||
if (ep->is_in == 1U)
|
||||
{
|
||||
if (ep->doublebuffer == 0U)
|
||||
{
|
||||
if (ep->type != EP_TYPE_ISOC)
|
||||
{
|
||||
/* Configure NAK status for the Endpoint */
|
||||
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Configure TX Endpoint to disabled state */
|
||||
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
|
||||
}
|
||||
}
|
||||
}
|
||||
else /* OUT endpoint */
|
||||
{
|
||||
if (ep->doublebuffer == 0U)
|
||||
{
|
||||
if (ep->type != EP_TYPE_ISOC)
|
||||
{
|
||||
/* Configure NAK status for the Endpoint */
|
||||
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_NAK);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Configure RX Endpoint to disabled state */
|
||||
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
#endif /* defined (HAL_PCD_MODULE_ENABLED) */
|
||||
|
||||
/**
|
||||
* @brief USB_StopDevice Stop the usb device mode
|
||||
* @param USBx Selected device
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx)
|
||||
{
|
||||
/* disable all interrupts and force USB reset */
|
||||
USBx->CNTR = (uint16_t)USB_CNTR_FRES;
|
||||
|
||||
/* clear interrupt status register */
|
||||
USBx->ISTR = 0U;
|
||||
|
||||
/* switch-off device */
|
||||
USBx->CNTR = (uint16_t)(USB_CNTR_FRES | USB_CNTR_PDWN);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_SetDevAddress Stop the usb device mode
|
||||
* @param USBx Selected device
|
||||
* @param address new device address to be assigned
|
||||
* This parameter can be a value from 0 to 255
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address)
|
||||
{
|
||||
if (address == 0U)
|
||||
{
|
||||
/* set device address and enable function */
|
||||
USBx->DADDR = (uint16_t)USB_DADDR_EF;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_DevConnect Connect the USB device by enabling the pull-up/pull-down
|
||||
* @param USBx Selected device
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx)
|
||||
{
|
||||
/* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */
|
||||
USBx->BCDR |= (uint16_t)USB_BCDR_DPPU;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_DevDisconnect Disconnect the USB device by disabling the pull-up/pull-down
|
||||
* @param USBx Selected device
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx)
|
||||
{
|
||||
/* Disable DP Pull-Up bit to disconnect the Internal PU resistor on USB DP line */
|
||||
USBx->BCDR &= (uint16_t)(~(USB_BCDR_DPPU));
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_ReadInterrupts return the global USB interrupt status
|
||||
* @param USBx Selected device
|
||||
* @retval USB Global Interrupt status
|
||||
*/
|
||||
uint32_t USB_ReadInterrupts(USB_TypeDef const *USBx)
|
||||
{
|
||||
uint32_t tmpreg;
|
||||
|
||||
tmpreg = USBx->ISTR;
|
||||
return tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_ActivateRemoteWakeup : active remote wakeup signalling
|
||||
* @param USBx Selected device
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx)
|
||||
{
|
||||
USBx->CNTR |= (uint16_t)USB_CNTR_RESUME;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling
|
||||
* @param USBx Selected device
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx)
|
||||
{
|
||||
USBx->CNTR &= (uint16_t)(~USB_CNTR_RESUME);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Copy a buffer from user memory area to packet memory area (PMA)
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param pbUsrBuf pointer to user memory area.
|
||||
* @param wPMABufAddr address into PMA.
|
||||
* @param wNBytes no. of bytes to be copied.
|
||||
* @retval None
|
||||
*/
|
||||
void USB_WritePMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
|
||||
{
|
||||
uint32_t n = ((uint32_t)wNBytes + 1U) >> 1;
|
||||
uint32_t BaseAddr = (uint32_t)USBx;
|
||||
uint32_t count;
|
||||
uint16_t WrVal;
|
||||
__IO uint16_t *pdwVal;
|
||||
uint8_t *pBuf = pbUsrBuf;
|
||||
|
||||
pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
|
||||
|
||||
for (count = n; count != 0U; count--)
|
||||
{
|
||||
WrVal = pBuf[0];
|
||||
WrVal |= (uint16_t)pBuf[1] << 8;
|
||||
*pdwVal = (WrVal & 0xFFFFU);
|
||||
pdwVal++;
|
||||
|
||||
#if PMA_ACCESS > 1U
|
||||
pdwVal++;
|
||||
#endif /* PMA_ACCESS */
|
||||
|
||||
pBuf++;
|
||||
pBuf++;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Copy data from packet memory area (PMA) to user memory buffer
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param pbUsrBuf pointer to user memory area.
|
||||
* @param wPMABufAddr address into PMA.
|
||||
* @param wNBytes no. of bytes to be copied.
|
||||
* @retval None
|
||||
*/
|
||||
void USB_ReadPMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
|
||||
{
|
||||
uint32_t n = (uint32_t)wNBytes >> 1;
|
||||
uint32_t BaseAddr = (uint32_t)USBx;
|
||||
uint32_t count;
|
||||
uint32_t RdVal;
|
||||
__IO uint16_t *pdwVal;
|
||||
uint8_t *pBuf = pbUsrBuf;
|
||||
|
||||
pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
|
||||
|
||||
for (count = n; count != 0U; count--)
|
||||
{
|
||||
RdVal = *(__IO uint16_t *)pdwVal;
|
||||
pdwVal++;
|
||||
*pBuf = (uint8_t)((RdVal >> 0) & 0xFFU);
|
||||
pBuf++;
|
||||
*pBuf = (uint8_t)((RdVal >> 8) & 0xFFU);
|
||||
pBuf++;
|
||||
|
||||
#if PMA_ACCESS > 1U
|
||||
pdwVal++;
|
||||
#endif /* PMA_ACCESS */
|
||||
}
|
||||
|
||||
if ((wNBytes % 2U) != 0U)
|
||||
{
|
||||
RdVal = *pdwVal;
|
||||
*pBuf = (uint8_t)((RdVal >> 0) & 0xFFU);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* defined (USB) */
|
||||
#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
616
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c
Normal file
616
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c
Normal file
@@ -0,0 +1,616 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_ll_utils.c
|
||||
* @author MCD Application Team
|
||||
* @brief UTILS LL module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_ll_rcc.h"
|
||||
#include "stm32f0xx_ll_utils.h"
|
||||
#include "stm32f0xx_ll_system.h"
|
||||
#ifdef USE_FULL_ASSERT
|
||||
#include "stm32_assert.h"
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32F0xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup UTILS_LL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @addtogroup UTILS_LL_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Defines used for PLL range */
|
||||
#define UTILS_PLL_OUTPUT_MIN 16000000U /*!< Frequency min for PLL output, in Hz */
|
||||
#define UTILS_PLL_OUTPUT_MAX 48000000U /*!< Frequency max for PLL output, in Hz */
|
||||
|
||||
/* Defines used for HSE range */
|
||||
#define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */
|
||||
#define UTILS_HSE_FREQUENCY_MAX 32000000U /*!< Frequency max for HSE frequency, in Hz */
|
||||
|
||||
/* Defines used for FLASH latency according to SYSCLK Frequency */
|
||||
#define UTILS_LATENCY1_FREQ 24000000U /*!< SYSCLK frequency to set FLASH latency 1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup UTILS_LL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
|
||||
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
|
||||
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
|
||||
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
|
||||
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
|
||||
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
|
||||
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
|
||||
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
|
||||
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
|
||||
|
||||
#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
|
||||
|| ((__VALUE__) == LL_RCC_APB1_DIV_2) \
|
||||
|| ((__VALUE__) == LL_RCC_APB1_DIV_4) \
|
||||
|| ((__VALUE__) == LL_RCC_APB1_DIV_8) \
|
||||
|| ((__VALUE__) == LL_RCC_APB1_DIV_16))
|
||||
|
||||
#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_2) \
|
||||
|| ((__VALUE__) == LL_RCC_PLL_MUL_3) \
|
||||
|| ((__VALUE__) == LL_RCC_PLL_MUL_4) \
|
||||
|| ((__VALUE__) == LL_RCC_PLL_MUL_5) \
|
||||
|| ((__VALUE__) == LL_RCC_PLL_MUL_6) \
|
||||
|| ((__VALUE__) == LL_RCC_PLL_MUL_7) \
|
||||
|| ((__VALUE__) == LL_RCC_PLL_MUL_8) \
|
||||
|| ((__VALUE__) == LL_RCC_PLL_MUL_9) \
|
||||
|| ((__VALUE__) == LL_RCC_PLL_MUL_10) \
|
||||
|| ((__VALUE__) == LL_RCC_PLL_MUL_11) \
|
||||
|| ((__VALUE__) == LL_RCC_PLL_MUL_12) \
|
||||
|| ((__VALUE__) == LL_RCC_PLL_MUL_13) \
|
||||
|| ((__VALUE__) == LL_RCC_PLL_MUL_14) \
|
||||
|| ((__VALUE__) == LL_RCC_PLL_MUL_15) \
|
||||
|| ((__VALUE__) == LL_RCC_PLL_MUL_16))
|
||||
|
||||
#define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2) || \
|
||||
((__VALUE__) == LL_RCC_PREDIV_DIV_3) || ((__VALUE__) == LL_RCC_PREDIV_DIV_4) || \
|
||||
((__VALUE__) == LL_RCC_PREDIV_DIV_5) || ((__VALUE__) == LL_RCC_PREDIV_DIV_6) || \
|
||||
((__VALUE__) == LL_RCC_PREDIV_DIV_7) || ((__VALUE__) == LL_RCC_PREDIV_DIV_8) || \
|
||||
((__VALUE__) == LL_RCC_PREDIV_DIV_9) || ((__VALUE__) == LL_RCC_PREDIV_DIV_10) || \
|
||||
((__VALUE__) == LL_RCC_PREDIV_DIV_11) || ((__VALUE__) == LL_RCC_PREDIV_DIV_12) || \
|
||||
((__VALUE__) == LL_RCC_PREDIV_DIV_13) || ((__VALUE__) == LL_RCC_PREDIV_DIV_14) || \
|
||||
((__VALUE__) == LL_RCC_PREDIV_DIV_15) || ((__VALUE__) == LL_RCC_PREDIV_DIV_16))
|
||||
|
||||
#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((UTILS_PLL_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLL_OUTPUT_MAX))
|
||||
|
||||
|
||||
#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
|
||||
|| ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
|
||||
|
||||
#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_Private_Functions UTILS Private functions
|
||||
* @{
|
||||
*/
|
||||
static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
|
||||
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
|
||||
static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
|
||||
static ErrorStatus UTILS_PLL_IsBusy(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup UTILS_LL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup UTILS_LL_EF_DELAY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function configures the Cortex-M SysTick source to have 1ms time base.
|
||||
* @note When a RTOS is used, it is recommended to avoid changing the Systick
|
||||
* configuration by calling this function, for a delay use rather osDelay RTOS service.
|
||||
* @param HCLKFrequency HCLK frequency in Hz
|
||||
* @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
|
||||
* @retval None
|
||||
*/
|
||||
void LL_Init1msTick(uint32_t HCLKFrequency)
|
||||
{
|
||||
/* Use frequency provided in argument */
|
||||
LL_InitTick(HCLKFrequency, 1000U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function provides accurate delay (in milliseconds) based
|
||||
* on SysTick counter flag
|
||||
* @note When a RTOS is used, it is recommended to avoid using blocking delay
|
||||
* and use rather osDelay service.
|
||||
* @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
|
||||
* will configure Systick to 1ms
|
||||
* @param Delay specifies the delay time length, in milliseconds.
|
||||
* @retval None
|
||||
*/
|
||||
void LL_mDelay(uint32_t Delay)
|
||||
{
|
||||
__IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
|
||||
/* Add this code to indicate that local variable is not used */
|
||||
((void)tmp);
|
||||
|
||||
/* Add a period to guaranty minimum wait */
|
||||
if (Delay < LL_MAX_DELAY)
|
||||
{
|
||||
Delay++;
|
||||
}
|
||||
|
||||
while (Delay)
|
||||
{
|
||||
if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
|
||||
{
|
||||
Delay--;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup UTILS_EF_SYSTEM
|
||||
* @brief System Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### System Configuration functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
System, AHB and APB buses clocks configuration
|
||||
|
||||
(+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 48000000 Hz.
|
||||
@endverbatim
|
||||
@internal
|
||||
Depending on the SYSCLK frequency, the flash latency should be adapted accordingly:
|
||||
(++) +-----------------------------------------------+
|
||||
(++) | Latency | SYSCLK clock frequency (MHz) |
|
||||
(++) |---------------|-------------------------------|
|
||||
(++) |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
|
||||
(++) |---------------|-------------------------------|
|
||||
(++) |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
|
||||
(++) +-----------------------------------------------+
|
||||
@endinternal
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function sets directly SystemCoreClock CMSIS variable.
|
||||
* @note Variable can be calculated also through SystemCoreClockUpdate function.
|
||||
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
|
||||
* @retval None
|
||||
*/
|
||||
void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
|
||||
{
|
||||
/* HCLK clock frequency */
|
||||
SystemCoreClock = HCLKFrequency;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update number of Flash wait states in line with new frequency and current
|
||||
voltage range.
|
||||
* @param Frequency SYSCLK frequency
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: Latency has been modified
|
||||
* - ERROR: Latency cannot be modified
|
||||
*/
|
||||
#if defined(FLASH_ACR_LATENCY)
|
||||
ErrorStatus LL_SetFlashLatency(uint32_t Frequency)
|
||||
{
|
||||
uint32_t timeout;
|
||||
uint32_t getlatency;
|
||||
uint32_t latency;
|
||||
ErrorStatus status = SUCCESS;
|
||||
|
||||
/* Frequency cannot be equal to 0 */
|
||||
if (Frequency == 0U)
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (Frequency > UTILS_LATENCY1_FREQ)
|
||||
{
|
||||
/* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */
|
||||
latency = LL_FLASH_LATENCY_1;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */
|
||||
latency = LL_FLASH_LATENCY_0;
|
||||
}
|
||||
LL_FLASH_SetLatency(latency);
|
||||
|
||||
/* Check that the new number of wait states is taken into account to access the Flash
|
||||
memory by reading the FLASH_ACR register */
|
||||
timeout = 2;
|
||||
do
|
||||
{
|
||||
/* Wait for Flash latency to be updated */
|
||||
getlatency = LL_FLASH_GetLatency();
|
||||
timeout--;
|
||||
} while ((getlatency != latency) && (timeout > 0));
|
||||
|
||||
if(getlatency != latency)
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* No thing to do */
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
#endif /* FLASH_ACR_LATENCY */
|
||||
|
||||
/**
|
||||
* @brief This function configures system clock with HSI as clock source of the PLL
|
||||
* @note The application need to ensure that PLL is disabled.
|
||||
* @note Function is based on the following formula:
|
||||
* - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
|
||||
* - PREDIV: Set to 2 for few devices
|
||||
* - PLLMUL: The application software must set correctly the PLL multiplication factor to
|
||||
* be in the range 16-48MHz
|
||||
* @note FLASH latency can be modified through this function.
|
||||
* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
|
||||
* the configuration information for the PLL.
|
||||
* @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
|
||||
* the configuration information for the BUS prescalers.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: Max frequency configuration done
|
||||
* - ERROR: Max frequency configuration not done
|
||||
*/
|
||||
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
|
||||
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
uint32_t pllfreq = 0U;
|
||||
|
||||
/* Check if one of the PLL is enabled */
|
||||
if (UTILS_PLL_IsBusy() == SUCCESS)
|
||||
{
|
||||
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
|
||||
/* Check PREDIV value */
|
||||
assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
|
||||
#else
|
||||
/* Force PREDIV value to 2 */
|
||||
UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2;
|
||||
#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
|
||||
/* Calculate the new PLL output frequency */
|
||||
pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
|
||||
|
||||
/* Enable HSI if not enabled */
|
||||
if (LL_RCC_HSI_IsReady() != 1U)
|
||||
{
|
||||
LL_RCC_HSI_Enable();
|
||||
while (LL_RCC_HSI_IsReady() != 1U)
|
||||
{
|
||||
/* Wait for HSI ready */
|
||||
}
|
||||
}
|
||||
|
||||
/* Configure PLL */
|
||||
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
|
||||
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
|
||||
#else
|
||||
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, UTILS_PLLInitStruct->PLLMul);
|
||||
#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
|
||||
|
||||
/* Enable PLL and switch system clock to PLL */
|
||||
status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Current PLL configuration cannot be modified */
|
||||
status = ERROR;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
#if defined(RCC_CFGR_SW_HSI48)
|
||||
/**
|
||||
* @brief This function configures system clock with HSI48 as clock source of the PLL
|
||||
* @note The application need to ensure that PLL is disabled.
|
||||
* @note Function is based on the following formula:
|
||||
* - PLL output frequency = ((HSI48 frequency / PREDIV) * PLLMUL)
|
||||
* - PLLMUL: The application software must set correctly the PLL multiplication factor to
|
||||
* be in the range 16-48MHz
|
||||
* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
|
||||
* the configuration information for the PLL.
|
||||
* @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
|
||||
* the configuration information for the BUS prescalers.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: Max frequency configuration done
|
||||
* - ERROR: Max frequency configuration not done
|
||||
*/
|
||||
ErrorStatus LL_PLL_ConfigSystemClock_HSI48(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
|
||||
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
uint32_t pllfreq = 0U;
|
||||
|
||||
/* Check if one of the PLL is enabled */
|
||||
if (UTILS_PLL_IsBusy() == SUCCESS)
|
||||
{
|
||||
/* Check PREDIV value */
|
||||
assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
|
||||
|
||||
/* Calculate the new PLL output frequency */
|
||||
pllfreq = UTILS_GetPLLOutputFrequency(HSI48_VALUE, UTILS_PLLInitStruct);
|
||||
|
||||
/* Enable HSI48 if not enabled */
|
||||
if (LL_RCC_HSI48_IsReady() != 1U)
|
||||
{
|
||||
LL_RCC_HSI48_Enable();
|
||||
while (LL_RCC_HSI48_IsReady() != 1U)
|
||||
{
|
||||
/* Wait for HSI48 ready */
|
||||
}
|
||||
}
|
||||
|
||||
/* Configure PLL */
|
||||
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI48, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
|
||||
|
||||
/* Enable PLL and switch system clock to PLL */
|
||||
status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Current PLL configuration cannot be modified */
|
||||
status = ERROR;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
#endif /*RCC_CFGR_SW_HSI48*/
|
||||
/**
|
||||
* @brief This function configures system clock with HSE as clock source of the PLL
|
||||
* @note The application need to ensure that PLL is disabled.
|
||||
* @note Function is based on the following formula:
|
||||
* - PLL output frequency = ((HSE frequency / PREDIV) * PLLMUL)
|
||||
* - PLLMUL: The application software must set correctly the PLL multiplication factor to
|
||||
* be in the range 16-48MHz
|
||||
* @note FLASH latency can be modified through this function.
|
||||
* @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 32000000
|
||||
* @param HSEBypass This parameter can be one of the following values:
|
||||
* @arg @ref LL_UTILS_HSEBYPASS_ON
|
||||
* @arg @ref LL_UTILS_HSEBYPASS_OFF
|
||||
* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
|
||||
* the configuration information for the PLL.
|
||||
* @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
|
||||
* the configuration information for the BUS prescalers.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: Max frequency configuration done
|
||||
* - ERROR: Max frequency configuration not done
|
||||
*/
|
||||
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
|
||||
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
uint32_t pllfreq = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
|
||||
assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
|
||||
|
||||
/* Check if one of the PLL is enabled */
|
||||
if (UTILS_PLL_IsBusy() == SUCCESS)
|
||||
{
|
||||
/* Check PREDIV value */
|
||||
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
|
||||
assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
|
||||
#else
|
||||
assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv));
|
||||
#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
|
||||
|
||||
/* Calculate the new PLL output frequency */
|
||||
pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
|
||||
|
||||
/* Enable HSE if not enabled */
|
||||
if (LL_RCC_HSE_IsReady() != 1U)
|
||||
{
|
||||
/* Check if need to enable HSE bypass feature or not */
|
||||
if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
|
||||
{
|
||||
LL_RCC_HSE_EnableBypass();
|
||||
}
|
||||
else
|
||||
{
|
||||
LL_RCC_HSE_DisableBypass();
|
||||
}
|
||||
|
||||
/* Enable HSE */
|
||||
LL_RCC_HSE_Enable();
|
||||
while (LL_RCC_HSE_IsReady() != 1U)
|
||||
{
|
||||
/* Wait for HSE ready */
|
||||
}
|
||||
}
|
||||
|
||||
/* Configure PLL */
|
||||
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
|
||||
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
|
||||
#else
|
||||
LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC_HSE_PREDIV | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul);
|
||||
#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
|
||||
|
||||
/* Enable PLL and switch system clock to PLL */
|
||||
status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Current PLL configuration cannot be modified */
|
||||
status = ERROR;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup UTILS_LL_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Function to check that PLL can be modified
|
||||
* @param PLL_InputFrequency PLL input frequency (in Hz)
|
||||
* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
|
||||
* the configuration information for the PLL.
|
||||
* @retval PLL output frequency (in Hz)
|
||||
*/
|
||||
static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
|
||||
{
|
||||
uint32_t pllfreq = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul));
|
||||
|
||||
/* Check different PLL parameters according to RM */
|
||||
/* The application software must set correctly the PLL multiplication factor to
|
||||
be in the range 16-48MHz */
|
||||
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
|
||||
pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
|
||||
#else
|
||||
pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTILS_PLLInitStruct->PLLMul);
|
||||
#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
|
||||
assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
|
||||
|
||||
return pllfreq;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function to check that PLL can be modified
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: PLL modification can be done
|
||||
* - ERROR: PLL is busy
|
||||
*/
|
||||
static ErrorStatus UTILS_PLL_IsBusy(void)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
|
||||
/* Check if PLL is busy*/
|
||||
if (LL_RCC_PLL_IsReady() != 0U)
|
||||
{
|
||||
/* PLL configuration cannot be modified */
|
||||
status = ERROR;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function to enable PLL and switch system clock to PLL
|
||||
* @param SYSCLK_Frequency SYSCLK frequency
|
||||
* @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
|
||||
* the configuration information for the BUS prescalers.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: No problem to switch system to PLL
|
||||
* - ERROR: Problem to switch system to PLL
|
||||
*/
|
||||
static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
uint32_t sysclk_frequency_current = 0U;
|
||||
|
||||
assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
|
||||
assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
|
||||
|
||||
/* Calculate current SYSCLK frequency */
|
||||
sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[LL_RCC_GetAHBPrescaler() >> RCC_POSITION_HPRE]);
|
||||
|
||||
/* Increasing the number of wait states because of higher CPU frequency */
|
||||
if (sysclk_frequency_current < SYSCLK_Frequency)
|
||||
{
|
||||
/* Set FLASH latency to highest latency */
|
||||
status = LL_SetFlashLatency(SYSCLK_Frequency);
|
||||
}
|
||||
|
||||
/* Update system clock configuration */
|
||||
if (status == SUCCESS)
|
||||
{
|
||||
/* Enable PLL */
|
||||
LL_RCC_PLL_Enable();
|
||||
while (LL_RCC_PLL_IsReady() != 1U)
|
||||
{
|
||||
/* Wait for PLL ready */
|
||||
}
|
||||
|
||||
/* Sysclk activation on the main PLL */
|
||||
LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
|
||||
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
|
||||
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
|
||||
{
|
||||
/* Wait for system clock switch to PLL */
|
||||
}
|
||||
|
||||
/* Set APB1 & APB2 prescaler*/
|
||||
LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
|
||||
}
|
||||
|
||||
/* Decreasing the number of wait states because of lower CPU frequency */
|
||||
if (sysclk_frequency_current > SYSCLK_Frequency)
|
||||
{
|
||||
/* Set FLASH latency to lowest latency */
|
||||
status = LL_SetFlashLatency(SYSCLK_Frequency);
|
||||
}
|
||||
|
||||
/* Update SystemCoreClock variable */
|
||||
if (status == SUCCESS)
|
||||
{
|
||||
LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider));
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
Reference in New Issue
Block a user