PWM working, reading input voltage signal.
This commit is contained in:
4360
Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
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4360
Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
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File diff suppressed because it is too large
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@@ -0,0 +1,790 @@
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/**
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******************************************************************************
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* @file stm32f0xx_hal_can_legacy.h
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* @author MCD Application Team
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* @brief Header file of CAN HAL Legacy module.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F0xx_HAL_CAN_LEGACY_H
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#define __STM32F0xx_HAL_CAN_LEGACY_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined(STM32F072xB) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f0xx_hal_def.h"
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/** @addtogroup STM32F0xx_HAL_Driver
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* @{
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*/
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/** @addtogroup CAN
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/** @defgroup CAN_Exported_Types CAN Exported Types
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* @{
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*/
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/**
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* @brief HAL State structures definition
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*/
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typedef enum
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{
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HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */
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HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
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HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */
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HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */
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HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */
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HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */
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HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */
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HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */
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HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */
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HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */
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HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */
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HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */
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}HAL_CAN_StateTypeDef;
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/**
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* @brief CAN init structure definition
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*/
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typedef struct
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{
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uint32_t Prescaler; /*!< Specifies the length of a time quantum.
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This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */
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uint32_t Mode; /*!< Specifies the CAN operating mode.
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This parameter can be a value of @ref CAN_operating_mode */
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uint32_t SJW; /*!< Specifies the maximum number of time quanta
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the CAN hardware is allowed to lengthen or
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shorten a bit to perform resynchronization.
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This parameter can be a value of @ref CAN_synchronisation_jump_width */
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uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
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This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
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uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
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This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
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uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
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This parameter can be set to ENABLE or DISABLE. */
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uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
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This parameter can be set to ENABLE or DISABLE. */
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uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
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This parameter can be set to ENABLE or DISABLE. */
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uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
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This parameter can be set to ENABLE or DISABLE. */
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uint32_t RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
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This parameter can be set to ENABLE or DISABLE. */
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uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.
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This parameter can be set to ENABLE or DISABLE. */
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}CAN_InitTypeDef;
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/**
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* @brief CAN filter configuration structure definition
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*/
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typedef struct
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{
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uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
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configuration, first one for a 16-bit configuration).
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This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
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uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
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configuration, second one for a 16-bit configuration).
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This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
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uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
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according to the mode (MSBs for a 32-bit configuration,
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first one for a 16-bit configuration).
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This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
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uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
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according to the mode (LSBs for a 32-bit configuration,
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second one for a 16-bit configuration).
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This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
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uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter.
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This parameter can be a value of @ref CAN_filter_FIFO */
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uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
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This parameter must be a number between Min_Data = 0 and Max_Data = 27. */
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uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
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This parameter can be a value of @ref CAN_filter_mode */
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uint32_t FilterScale; /*!< Specifies the filter scale.
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This parameter can be a value of @ref CAN_filter_scale */
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uint32_t FilterActivation; /*!< Enable or disable the filter.
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This parameter can be set to ENABLE or DISABLE. */
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uint32_t BankNumber; /*!< Select the start slave bank filter
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This parameter must be a number between Min_Data = 0 and Max_Data = 28. */
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}CAN_FilterConfTypeDef;
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/**
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* @brief CAN Tx message structure definition
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*/
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typedef struct
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{
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uint32_t StdId; /*!< Specifies the standard identifier.
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This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
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uint32_t ExtId; /*!< Specifies the extended identifier.
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This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
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uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
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This parameter can be a value of @ref CAN_identifier_type */
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uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
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This parameter can be a value of @ref CAN_remote_transmission_request */
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uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
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This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
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uint8_t Data[8]; /*!< Contains the data to be transmitted.
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This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
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}CanTxMsgTypeDef;
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/**
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* @brief CAN Rx message structure definition
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*/
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typedef struct
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{
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uint32_t StdId; /*!< Specifies the standard identifier.
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This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
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uint32_t ExtId; /*!< Specifies the extended identifier.
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This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
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uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
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This parameter can be a value of @ref CAN_identifier_type */
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uint32_t RTR; /*!< Specifies the type of frame for the received message.
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This parameter can be a value of @ref CAN_remote_transmission_request */
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uint32_t DLC; /*!< Specifies the length of the frame that will be received.
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This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
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uint8_t Data[8]; /*!< Contains the data to be received.
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This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
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uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
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This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
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uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
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This parameter can be CAN_FIFO0 or CAN_FIFO1 */
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}CanRxMsgTypeDef;
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/**
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* @brief CAN handle Structure definition
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*/
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typedef struct
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{
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CAN_TypeDef *Instance; /*!< Register base address */
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CAN_InitTypeDef Init; /*!< CAN required parameters */
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CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
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CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */
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CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */
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HAL_LockTypeDef Lock; /*!< CAN locking object */
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__IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
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__IO uint32_t ErrorCode; /*!< CAN Error code
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This parameter can be a value of @ref CAN_Error_Code */
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}CAN_HandleTypeDef;
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup CAN_Exported_Constants CAN Exported Constants
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* @{
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*/
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/** @defgroup CAN_Error_Code CAN Error Code
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* @{
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*/
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#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */
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#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< EWG error */
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#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< EPV error */
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#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< BOF error */
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#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */
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#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */
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#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */
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#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive */
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#define HAL_CAN_ERROR_BD (0x00000080U) /*!< LEC dominant */
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#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< LEC transfer error */
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#define HAL_CAN_ERROR_FOV0 (0x00000200U) /*!< FIFO0 overrun error */
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#define HAL_CAN_ERROR_FOV1 (0x00000400U) /*!< FIFO1 overrun error */
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#define HAL_CAN_ERROR_TXFAIL (0x00000800U) /*!< Transmit failure */
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/**
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* @}
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*/
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/** @defgroup CAN_InitStatus CAN InitStatus
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* @{
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*/
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#define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */
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#define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */
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/**
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* @}
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*/
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/** @defgroup CAN_operating_mode CAN Operating Mode
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* @{
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*/
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#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */
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#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
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#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
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#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
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/**
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* @}
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*/
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/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
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* @{
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*/
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#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */
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#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
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#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
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#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
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/**
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* @}
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*/
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/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
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* @{
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*/
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#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */
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#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
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#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
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#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
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#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
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#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
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#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
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#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
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#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
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#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
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#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
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#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
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#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
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#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
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#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
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#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
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/**
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* @}
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*/
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/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2
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* @{
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*/
|
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#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */
|
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#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
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#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
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#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
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#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
|
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#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
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#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
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#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
|
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/**
|
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* @}
|
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*/
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|
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/** @defgroup CAN_filter_mode CAN Filter Mode
|
||||
* @{
|
||||
*/
|
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#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00U) /*!< Identifier mask mode */
|
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#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01U) /*!< Identifier list mode */
|
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/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_scale CAN Filter Scale
|
||||
* @{
|
||||
*/
|
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#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00U) /*!< Two 16-bit filters */
|
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#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01U) /*!< One 32-bit filter */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_FIFO CAN Filter FIFO
|
||||
* @{
|
||||
*/
|
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#define CAN_FILTER_FIFO0 ((uint8_t)0x00U) /*!< Filter FIFO 0 assignment for filter x */
|
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#define CAN_FILTER_FIFO1 ((uint8_t)0x01U) /*!< Filter FIFO 1 assignment for filter x */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_identifier_type CAN Identifier Type
|
||||
* @{
|
||||
*/
|
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#define CAN_ID_STD (0x00000000U) /*!< Standard Id */
|
||||
#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */
|
||||
/**
|
||||
* @}
|
||||
*/
|
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|
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/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
|
||||
* @{
|
||||
*/
|
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#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */
|
||||
#define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FIFO0 ((uint8_t)0x00U) /*!< CAN FIFO 0 used to receive */
|
||||
#define CAN_FIFO1 ((uint8_t)0x01U) /*!< CAN FIFO 1 used to receive */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_flags CAN Flags
|
||||
* @{
|
||||
*/
|
||||
/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
|
||||
and CAN_ClearFlag() functions. */
|
||||
/* If the flag is 0x1XXXXXXX, it means that it can only be used with
|
||||
CAN_GetFlagStatus() function. */
|
||||
|
||||
/* Transmit Flags */
|
||||
#define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request MailBox0 flag */
|
||||
#define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request MailBox1 flag */
|
||||
#define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request MailBox2 flag */
|
||||
#define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox0 flag */
|
||||
#define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox1 flag */
|
||||
#define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox2 flag */
|
||||
#define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */
|
||||
#define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 0 empty flag */
|
||||
#define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 0 empty flag */
|
||||
|
||||
/* Receive Flags */
|
||||
#define CAN_FLAG_FF0 (0x00000203U) /*!< FIFO 0 Full flag */
|
||||
#define CAN_FLAG_FOV0 (0x00000204U) /*!< FIFO 0 Overrun flag */
|
||||
|
||||
#define CAN_FLAG_FF1 (0x00000403U) /*!< FIFO 1 Full flag */
|
||||
#define CAN_FLAG_FOV1 (0x00000404U) /*!< FIFO 1 Overrun flag */
|
||||
|
||||
/* Operating Mode Flags */
|
||||
#define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */
|
||||
#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */
|
||||
#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */
|
||||
#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up flag */
|
||||
#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge flag */
|
||||
/* @note When SLAK interrupt is disabled (SLKIE=0U), no polling on SLAKI is possible.
|
||||
In this case the SLAK bit can be polled.*/
|
||||
|
||||
/* Error Flags */
|
||||
#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */
|
||||
#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */
|
||||
#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CAN_interrupts CAN Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
|
||||
|
||||
/* Receive Interrupts */
|
||||
#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
|
||||
#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
|
||||
#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
|
||||
#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
|
||||
#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
|
||||
#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
|
||||
|
||||
/* Operating Mode Interrupts */
|
||||
#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
|
||||
#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
|
||||
|
||||
/* Error Interrupts */
|
||||
#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
|
||||
#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
|
||||
#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
|
||||
#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
|
||||
#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Mailboxes CAN Mailboxes
|
||||
* @{
|
||||
*/
|
||||
/* Mailboxes definition */
|
||||
#define CAN_TXMAILBOX_0 ((uint8_t)0x00U)
|
||||
#define CAN_TXMAILBOX_1 ((uint8_t)0x01U)
|
||||
#define CAN_TXMAILBOX_2 ((uint8_t)0x02U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup CAN_Exported_Macros CAN Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset CAN handle state
|
||||
* @param __HANDLE__ CAN handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Enable the specified CAN interrupts.
|
||||
* @param __HANDLE__ CAN handle.
|
||||
* @param __INTERRUPT__ CAN Interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified CAN interrupts.
|
||||
* @param __HANDLE__ CAN handle.
|
||||
* @param __INTERRUPT__ CAN Interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Return the number of pending received messages.
|
||||
* @param __HANDLE__ CAN handle.
|
||||
* @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
|
||||
* @retval The number of pending message.
|
||||
*/
|
||||
#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
|
||||
((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&0x03U)))
|
||||
|
||||
/** @brief Check whether the specified CAN flag is set or not.
|
||||
* @param __HANDLE__ specifies the CAN Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CAN_TSR_RQCP0: Request MailBox0 Flag
|
||||
* @arg CAN_TSR_RQCP1: Request MailBox1 Flag
|
||||
* @arg CAN_TSR_RQCP2: Request MailBox2 Flag
|
||||
* @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
|
||||
* @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
|
||||
* @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
|
||||
* @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
|
||||
* @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
|
||||
* @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
|
||||
* @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
|
||||
* @arg CAN_FLAG_FF0: FIFO 0 Full Flag
|
||||
* @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
|
||||
* @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
|
||||
* @arg CAN_FLAG_FF1: FIFO 1 Full Flag
|
||||
* @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
|
||||
* @arg CAN_FLAG_WKU: Wake up Flag
|
||||
* @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
|
||||
* @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
|
||||
* @arg CAN_FLAG_EWG: Error Warning Flag
|
||||
* @arg CAN_FLAG_EPV: Error Passive Flag
|
||||
* @arg CAN_FLAG_BOF: Bus-Off Flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
|
||||
((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
|
||||
|
||||
/** @brief Clear the specified CAN pending flag.
|
||||
* @param __HANDLE__ specifies the CAN Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CAN_TSR_RQCP0: Request MailBox0 Flag
|
||||
* @arg CAN_TSR_RQCP1: Request MailBox1 Flag
|
||||
* @arg CAN_TSR_RQCP2: Request MailBox2 Flag
|
||||
* @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
|
||||
* @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
|
||||
* @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
|
||||
* @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
|
||||
* @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
|
||||
* @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
|
||||
* @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
|
||||
* @arg CAN_FLAG_FF0: FIFO 0 Full Flag
|
||||
* @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
|
||||
* @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
|
||||
* @arg CAN_FLAG_FF1: FIFO 1 Full Flag
|
||||
* @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
|
||||
* @arg CAN_FLAG_WKU: Wake up Flag
|
||||
* @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
|
||||
* @arg CAN_FLAG_EWG: Error Warning Flag
|
||||
* @arg CAN_FLAG_EPV: Error Passive Flag
|
||||
* @arg CAN_FLAG_BOF: Bus-Off Flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
|
||||
((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
|
||||
|
||||
|
||||
/** @brief Check if the specified CAN interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__ specifies the CAN Handle.
|
||||
* @param __INTERRUPT__ specifies the CAN interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
|
||||
* @arg CAN_IT_FMP0: FIFO0 message pending interrupt enablev
|
||||
* @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Check the transmission status of a CAN Frame.
|
||||
* @param __HANDLE__ CAN handle.
|
||||
* @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission.
|
||||
* @retval The new status of transmission (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
|
||||
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TME0)) :\
|
||||
((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TME1)) :\
|
||||
((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TME2)))
|
||||
|
||||
/**
|
||||
* @brief Release the specified receive FIFO.
|
||||
* @param __HANDLE__ CAN handle.
|
||||
* @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
|
||||
((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1))
|
||||
|
||||
/**
|
||||
* @brief Cancel a transmit request.
|
||||
* @param __HANDLE__ specifies the CAN Handle.
|
||||
* @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
|
||||
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\
|
||||
((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\
|
||||
((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2))
|
||||
|
||||
/**
|
||||
* @brief Enable or disables the DBG Freeze for CAN.
|
||||
* @param __HANDLE__ specifies the CAN Handle.
|
||||
* @param __NEWSTATE__ new state of the CAN peripheral.
|
||||
* This parameter can be: ENABLE (CAN reception/transmission is frozen
|
||||
* during debug. Reception FIFOs can still be accessed/controlled normally)
|
||||
* or DISABLE (CAN is working during debug).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
|
||||
((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup CAN_Exported_Functions CAN Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
|
||||
HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
|
||||
void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
|
||||
void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @brief I/O operation functions
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
|
||||
HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
|
||||
void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
|
||||
void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
|
||||
void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
|
||||
* @brief CAN Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
|
||||
HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup CAN_Private_Types CAN Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup CAN_Private_Variables CAN Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup CAN_Private_Constants CAN Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04U) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
|
||||
#define CAN_FLAG_MASK (0x000000FFU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Macros -----------------------------------------------------------*/
|
||||
/** @defgroup CAN_Private_Macros CAN Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
|
||||
((MODE) == CAN_MODE_LOOPBACK)|| \
|
||||
((MODE) == CAN_MODE_SILENT) || \
|
||||
((MODE) == CAN_MODE_SILENT_LOOPBACK))
|
||||
|
||||
#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
|
||||
((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
|
||||
|
||||
#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
|
||||
|
||||
#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
|
||||
|
||||
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
|
||||
|
||||
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U)
|
||||
|
||||
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
|
||||
((MODE) == CAN_FILTERMODE_IDLIST))
|
||||
|
||||
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
|
||||
((SCALE) == CAN_FILTERSCALE_32BIT))
|
||||
|
||||
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
|
||||
((FIFO) == CAN_FILTER_FIFO1))
|
||||
|
||||
#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
|
||||
|
||||
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02U))
|
||||
#define IS_CAN_STDID(STDID) ((STDID) <= (0x7FFU))
|
||||
#define IS_CAN_EXTID(EXTID) ((EXTID) <= (0x1FFFFFFFU))
|
||||
#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08U))
|
||||
|
||||
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
|
||||
((IDTYPE) == CAN_ID_EXT))
|
||||
|
||||
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
|
||||
|
||||
#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
|
||||
|
||||
#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
|
||||
((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
|
||||
((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
|
||||
((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
|
||||
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
|
||||
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
|
||||
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
|
||||
|
||||
#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
|
||||
((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
|
||||
((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
|
||||
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
|
||||
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
|
||||
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of private macros -----------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* STM32F072xB || STM32F042x6 || STM32F048xx || STM32F078xx || STM32F091xC || STM32F098xx */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0xx_HAL_CAN_LEGACY_H */
|
||||
56
Drivers/STM32F0xx_HAL_Driver/Inc/stm32_assert_template.h
Normal file
56
Drivers/STM32F0xx_HAL_Driver/Inc/stm32_assert_template.h
Normal file
@@ -0,0 +1,56 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32_assert.h
|
||||
* @author MCD Application Team
|
||||
* @brief STM32 assert template file.
|
||||
* This file should be copied to the application folder and renamed
|
||||
* to stm32_assert.h.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32_ASSERT_H
|
||||
#define __STM32_ASSERT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32_ASSERT_H */
|
||||
|
||||
|
||||
|
||||
584
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h
Normal file
584
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h
Normal file
@@ -0,0 +1,584 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains all the functions prototypes for the HAL
|
||||
* module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0xx_HAL_H
|
||||
#define __STM32F0xx_HAL_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_conf.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup HAL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) || \
|
||||
defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \
|
||||
defined(STM32F070xB) || defined(STM32F030x6)
|
||||
#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PA9) == SYSCFG_FASTMODEPLUS_PA9) || \
|
||||
(((__PIN__) & SYSCFG_FASTMODEPLUS_PA10) == SYSCFG_FASTMODEPLUS_PA10) || \
|
||||
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
|
||||
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
|
||||
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
|
||||
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
|
||||
#else
|
||||
#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
|
||||
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
|
||||
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
|
||||
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
|
||||
#endif
|
||||
#if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
|
||||
#define IS_HAL_REMAP_PIN(RMP) ((RMP) == HAL_REMAP_PA11_PA12)
|
||||
#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
|
||||
#if defined(STM32F091xC) || defined(STM32F098xx)
|
||||
#define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \
|
||||
((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \
|
||||
((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4))
|
||||
#endif /* STM32F091xC || STM32F098xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup HAL_Exported_Constants HAL Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_TICK_FREQ Tick Frequency
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_TICK_FREQ_10HZ = 100U,
|
||||
HAL_TICK_FREQ_100HZ = 10U,
|
||||
HAL_TICK_FREQ_1KHZ = 1U,
|
||||
HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
|
||||
} HAL_TickFreqTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
|
||||
/** @defgroup HAL_Pin_remapping HAL Pin remapping
|
||||
* @{
|
||||
*/
|
||||
#define HAL_REMAP_PA11_PA12 (SYSCFG_CFGR1_PA11_PA12_RMP) /*!< PA11 and PA12 remapping bit for small packages (28 and 20 pins).
|
||||
0: No remap (pin pair PA9/10 mapped on the pins)
|
||||
1: Remap (pin pair PA11/12 mapped instead of PA9/10) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
|
||||
|
||||
#if defined(STM32F091xC) || defined(STM32F098xx)
|
||||
/** @defgroup HAL_IRDA_ENV_SEL HAL IRDA Envelope Selection
|
||||
* @note Applicable on STM32F09x
|
||||
* @{
|
||||
*/
|
||||
#define HAL_SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IRDA_ENV_SEL_0 & SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 00: Timer16 is selected as IRDA Modulation envelope source */
|
||||
#define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IRDA_ENV_SEL_0) /* 01: USART1 is selected as IRDA Modulation envelope source */
|
||||
#define HAL_SYSCFG_IRDA_ENV_SEL_USART4 (SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 10: USART4 is selected as IRDA Modulation envelope source */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F091xC || STM32F098xx */
|
||||
|
||||
|
||||
/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Fast-mode Plus driving capability on a specific GPIO
|
||||
*/
|
||||
#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) || \
|
||||
defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \
|
||||
defined(STM32F070xB) || defined(STM32F030x6)
|
||||
#define SYSCFG_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast-mode Plus on PA9 */
|
||||
#define SYSCFG_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast-mode Plus on PA10 */
|
||||
#endif
|
||||
#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< Enable Fast-mode Plus on PB6 */
|
||||
#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< Enable Fast-mode Plus on PB7 */
|
||||
#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< Enable Fast-mode Plus on PB8 */
|
||||
#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< Enable Fast-mode Plus on PB9 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#if defined(STM32F091xC) || defined (STM32F098xx)
|
||||
/** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper
|
||||
* @brief ISR Wrapper
|
||||
* @note applicable on STM32F09x
|
||||
* @{
|
||||
*/
|
||||
#define HAL_SYSCFG_ITLINE0 ( 0x00000000U) /*!< Internal define for macro handling */
|
||||
#define HAL_SYSCFG_ITLINE1 ( 0x00000001U) /*!< Internal define for macro handling */
|
||||
#define HAL_SYSCFG_ITLINE2 ( 0x00000002U) /*!< Internal define for macro handling */
|
||||
#define HAL_SYSCFG_ITLINE3 ( 0x00000003U) /*!< Internal define for macro handling */
|
||||
#define HAL_SYSCFG_ITLINE4 ( 0x00000004U) /*!< Internal define for macro handling */
|
||||
#define HAL_SYSCFG_ITLINE5 ( 0x00000005U) /*!< Internal define for macro handling */
|
||||
#define HAL_SYSCFG_ITLINE6 ( 0x00000006U) /*!< Internal define for macro handling */
|
||||
#define HAL_SYSCFG_ITLINE7 ( 0x00000007U) /*!< Internal define for macro handling */
|
||||
#define HAL_SYSCFG_ITLINE8 ( 0x00000008U) /*!< Internal define for macro handling */
|
||||
#define HAL_SYSCFG_ITLINE9 ( 0x00000009U) /*!< Internal define for macro handling */
|
||||
#define HAL_SYSCFG_ITLINE10 ( 0x0000000AU) /*!< Internal define for macro handling */
|
||||
#define HAL_SYSCFG_ITLINE11 ( 0x0000000BU) /*!< Internal define for macro handling */
|
||||
#define HAL_SYSCFG_ITLINE12 ( 0x0000000CU) /*!< Internal define for macro handling */
|
||||
#define HAL_SYSCFG_ITLINE13 ( 0x0000000DU) /*!< Internal define for macro handling */
|
||||
#define HAL_SYSCFG_ITLINE14 ( 0x0000000EU) /*!< Internal define for macro handling */
|
||||
#define HAL_SYSCFG_ITLINE15 ( 0x0000000FU) /*!< Internal define for macro handling */
|
||||
#define HAL_SYSCFG_ITLINE16 ( 0x00000010U) /*!< Internal define for macro handling */
|
||||
#define HAL_SYSCFG_ITLINE17 ( 0x00000011U) /*!< Internal define for macro handling */
|
||||
#define HAL_SYSCFG_ITLINE18 ( 0x00000012U) /*!< Internal define for macro handling */
|
||||
#define HAL_SYSCFG_ITLINE19 ( 0x00000013U) /*!< Internal define for macro handling */
|
||||
#define HAL_SYSCFG_ITLINE20 ( 0x00000014U) /*!< Internal define for macro handling */
|
||||
#define HAL_SYSCFG_ITLINE21 ( 0x00000015U) /*!< Internal define for macro handling */
|
||||
#define HAL_SYSCFG_ITLINE22 ( 0x00000016U) /*!< Internal define for macro handling */
|
||||
#define HAL_SYSCFG_ITLINE23 ( 0x00000017U) /*!< Internal define for macro handling */
|
||||
#define HAL_SYSCFG_ITLINE24 ( 0x00000018U) /*!< Internal define for macro handling */
|
||||
#define HAL_SYSCFG_ITLINE25 ( 0x00000019U) /*!< Internal define for macro handling */
|
||||
#define HAL_SYSCFG_ITLINE26 ( 0x0000001AU) /*!< Internal define for macro handling */
|
||||
#define HAL_SYSCFG_ITLINE27 ( 0x0000001BU) /*!< Internal define for macro handling */
|
||||
#define HAL_SYSCFG_ITLINE28 ( 0x0000001CU) /*!< Internal define for macro handling */
|
||||
#define HAL_SYSCFG_ITLINE29 ( 0x0000001DU) /*!< Internal define for macro handling */
|
||||
#define HAL_SYSCFG_ITLINE30 ( 0x0000001EU) /*!< Internal define for macro handling */
|
||||
#define HAL_SYSCFG_ITLINE31 ( 0x0000001FU) /*!< Internal define for macro handling */
|
||||
|
||||
#define HAL_ITLINE_EWDG ((uint32_t) ((HAL_SYSCFG_ITLINE0 << 0x18U) | SYSCFG_ITLINE0_SR_EWDG)) /*!< EWDG has expired .... */
|
||||
#if defined(STM32F091xC)
|
||||
#define HAL_ITLINE_PVDOUT ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_PVDOUT)) /*!< Power voltage detection Interrupt .... */
|
||||
#endif
|
||||
#define HAL_ITLINE_VDDIO2 ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_VDDIO2)) /*!< VDDIO2 Interrupt .... */
|
||||
#define HAL_ITLINE_RTC_WAKEUP ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_WAKEUP)) /*!< RTC WAKEUP -> exti[20] Interrupt */
|
||||
#define HAL_ITLINE_RTC_TSTAMP ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_TSTAMP)) /*!< RTC Time Stamp -> exti[19] interrupt */
|
||||
#define HAL_ITLINE_RTC_ALRA ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_ALRA)) /*!< RTC Alarm -> exti[17] interrupt .... */
|
||||
#define HAL_ITLINE_FLASH_ITF ((uint32_t) ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ITF)) /*!< Flash ITF Interrupt */
|
||||
#define HAL_ITLINE_CRS ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CRS)) /*!< CRS Interrupt */
|
||||
#define HAL_ITLINE_CLK_CTRL ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CLK_CTRL)) /*!< CLK Control Interrupt */
|
||||
#define HAL_ITLINE_EXTI0 ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI0)) /*!< External Interrupt 0 */
|
||||
#define HAL_ITLINE_EXTI1 ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI1)) /*!< External Interrupt 1 */
|
||||
#define HAL_ITLINE_EXTI2 ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI2)) /*!< External Interrupt 2 */
|
||||
#define HAL_ITLINE_EXTI3 ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI3)) /*!< External Interrupt 3 */
|
||||
#define HAL_ITLINE_EXTI4 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI4)) /*!< EXTI4 Interrupt */
|
||||
#define HAL_ITLINE_EXTI5 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI5)) /*!< EXTI5 Interrupt */
|
||||
#define HAL_ITLINE_EXTI6 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI6)) /*!< EXTI6 Interrupt */
|
||||
#define HAL_ITLINE_EXTI7 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI7)) /*!< EXTI7 Interrupt */
|
||||
#define HAL_ITLINE_EXTI8 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI8)) /*!< EXTI8 Interrupt */
|
||||
#define HAL_ITLINE_EXTI9 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI9)) /*!< EXTI9 Interrupt */
|
||||
#define HAL_ITLINE_EXTI10 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI10)) /*!< EXTI10 Interrupt */
|
||||
#define HAL_ITLINE_EXTI11 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI11)) /*!< EXTI11 Interrupt */
|
||||
#define HAL_ITLINE_EXTI12 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI12)) /*!< EXTI12 Interrupt */
|
||||
#define HAL_ITLINE_EXTI13 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI13)) /*!< EXTI13 Interrupt */
|
||||
#define HAL_ITLINE_EXTI14 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI14)) /*!< EXTI14 Interrupt */
|
||||
#define HAL_ITLINE_EXTI15 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI15)) /*!< EXTI15 Interrupt */
|
||||
#define HAL_ITLINE_TSC_EOA ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_TSC_EOA)) /*!< Touch control EOA Interrupt */
|
||||
#define HAL_ITLINE_TSC_MCE ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_TSC_MCE)) /*!< Touch control MCE Interrupt */
|
||||
#define HAL_ITLINE_DMA1_CH1 ((uint32_t) ((HAL_SYSCFG_ITLINE9 << 0x18U) | SYSCFG_ITLINE9_SR_DMA1_CH1)) /*!< DMA1 Channel 1 Interrupt */
|
||||
#define HAL_ITLINE_DMA1_CH2 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH2)) /*!< DMA1 Channel 2 Interrupt */
|
||||
#define HAL_ITLINE_DMA1_CH3 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH3)) /*!< DMA1 Channel 3 Interrupt */
|
||||
#define HAL_ITLINE_DMA2_CH1 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA2_CH1)) /*!< DMA2 Channel 1 Interrupt */
|
||||
#define HAL_ITLINE_DMA2_CH2 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA2_CH2)) /*!< DMA2 Channel 2 Interrupt */
|
||||
#define HAL_ITLINE_DMA1_CH4 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH4)) /*!< DMA1 Channel 4 Interrupt */
|
||||
#define HAL_ITLINE_DMA1_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH5)) /*!< DMA1 Channel 5 Interrupt */
|
||||
#define HAL_ITLINE_DMA1_CH6 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH6)) /*!< DMA1 Channel 6 Interrupt */
|
||||
#define HAL_ITLINE_DMA1_CH7 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH7)) /*!< DMA1 Channel 7 Interrupt */
|
||||
#define HAL_ITLINE_DMA2_CH3 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH3)) /*!< DMA2 Channel 3 Interrupt */
|
||||
#define HAL_ITLINE_DMA2_CH4 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH4)) /*!< DMA2 Channel 4 Interrupt */
|
||||
#define HAL_ITLINE_DMA2_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH5)) /*!< DMA2 Channel 5 Interrupt */
|
||||
#define HAL_ITLINE_ADC ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_ADC)) /*!< ADC Interrupt */
|
||||
#define HAL_ITLINE_COMP1 ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP1)) /*!< COMP1 Interrupt -> exti[21] */
|
||||
#define HAL_ITLINE_COMP2 ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP2)) /*!< COMP2 Interrupt -> exti[21] */
|
||||
#define HAL_ITLINE_TIM1_BRK ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_BRK)) /*!< TIM1 BRK Interrupt */
|
||||
#define HAL_ITLINE_TIM1_UPD ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_UPD)) /*!< TIM1 UPD Interrupt */
|
||||
#define HAL_ITLINE_TIM1_TRG ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_TRG)) /*!< TIM1 TRG Interrupt */
|
||||
#define HAL_ITLINE_TIM1_CCU ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_CCU)) /*!< TIM1 CCU Interrupt */
|
||||
#define HAL_ITLINE_TIM1_CC ((uint32_t) ((HAL_SYSCFG_ITLINE14 << 0x18U) | SYSCFG_ITLINE14_SR_TIM1_CC)) /*!< TIM1 CC Interrupt */
|
||||
#define HAL_ITLINE_TIM2 ((uint32_t) ((HAL_SYSCFG_ITLINE15 << 0x18U) | SYSCFG_ITLINE15_SR_TIM2_GLB)) /*!< TIM2 Interrupt */
|
||||
#define HAL_ITLINE_TIM3 ((uint32_t) ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM3_GLB)) /*!< TIM3 Interrupt */
|
||||
#define HAL_ITLINE_DAC ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_DAC)) /*!< DAC Interrupt */
|
||||
#define HAL_ITLINE_TIM6 ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_TIM6_GLB)) /*!< TIM6 Interrupt */
|
||||
#define HAL_ITLINE_TIM7 ((uint32_t) ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_TIM7_GLB)) /*!< TIM7 Interrupt */
|
||||
#define HAL_ITLINE_TIM14 ((uint32_t) ((HAL_SYSCFG_ITLINE19 << 0x18U) | SYSCFG_ITLINE19_SR_TIM14_GLB)) /*!< TIM14 Interrupt */
|
||||
#define HAL_ITLINE_TIM15 ((uint32_t) ((HAL_SYSCFG_ITLINE20 << 0x18U) | SYSCFG_ITLINE20_SR_TIM15_GLB)) /*!< TIM15 Interrupt */
|
||||
#define HAL_ITLINE_TIM16 ((uint32_t) ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_TIM16_GLB)) /*!< TIM16 Interrupt */
|
||||
#define HAL_ITLINE_TIM17 ((uint32_t) ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_TIM17_GLB)) /*!< TIM17 Interrupt */
|
||||
#define HAL_ITLINE_I2C1 ((uint32_t) ((HAL_SYSCFG_ITLINE23 << 0x18U) | SYSCFG_ITLINE23_SR_I2C1_GLB)) /*!< I2C1 Interrupt -> exti[23] */
|
||||
#define HAL_ITLINE_I2C2 ((uint32_t) ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C2_GLB)) /*!< I2C2 Interrupt */
|
||||
#define HAL_ITLINE_SPI1 ((uint32_t) ((HAL_SYSCFG_ITLINE25 << 0x18U) | SYSCFG_ITLINE25_SR_SPI1)) /*!< I2C1 Interrupt -> exti[23] */
|
||||
#define HAL_ITLINE_SPI2 ((uint32_t) ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE26_SR_SPI2)) /*!< SPI1 Interrupt */
|
||||
#define HAL_ITLINE_USART1 ((uint32_t) ((HAL_SYSCFG_ITLINE27 << 0x18U) | SYSCFG_ITLINE27_SR_USART1_GLB)) /*!< USART1 GLB Interrupt -> exti[25] */
|
||||
#define HAL_ITLINE_USART2 ((uint32_t) ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_USART2_GLB)) /*!< USART2 GLB Interrupt -> exti[26] */
|
||||
#define HAL_ITLINE_USART3 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART3_GLB)) /*!< USART3 Interrupt .... */
|
||||
#define HAL_ITLINE_USART4 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART4_GLB)) /*!< USART4 Interrupt .... */
|
||||
#define HAL_ITLINE_USART5 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART5_GLB)) /*!< USART5 Interrupt .... */
|
||||
#define HAL_ITLINE_USART6 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART6_GLB)) /*!< USART6 Interrupt .... */
|
||||
#define HAL_ITLINE_USART7 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART7_GLB)) /*!< USART7 Interrupt .... */
|
||||
#define HAL_ITLINE_USART8 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART8_GLB)) /*!< USART8 Interrupt .... */
|
||||
#define HAL_ITLINE_CAN ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CAN)) /*!< CAN Interrupt */
|
||||
#define HAL_ITLINE_CEC ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CEC)) /*!< CEC Interrupt -> exti[27] */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F091xC || STM32F098xx */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup HAL_Exported_Macros HAL Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Freeze_Unfreeze_Peripherals HAL Freeze Unfreeze Peripherals
|
||||
* @brief Freeze/Unfreeze Peripherals in Debug mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
|
||||
#define __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP))
|
||||
#define __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
|
||||
#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
|
||||
#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
|
||||
#endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM15() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP))
|
||||
#endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM16() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP))
|
||||
#endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM17() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP))
|
||||
#endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Memory_Mapping_Selection Memory Mapping Selection
|
||||
* @{
|
||||
*/
|
||||
#if defined(SYSCFG_CFGR1_MEM_MODE)
|
||||
/** @brief Main Flash memory mapped at 0x00000000
|
||||
*/
|
||||
#define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE))
|
||||
#endif /* SYSCFG_CFGR1_MEM_MODE */
|
||||
|
||||
#if defined(SYSCFG_CFGR1_MEM_MODE_0)
|
||||
/** @brief System Flash memory mapped at 0x00000000
|
||||
*/
|
||||
#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
|
||||
SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \
|
||||
}while(0)
|
||||
#endif /* SYSCFG_CFGR1_MEM_MODE_0 */
|
||||
|
||||
#if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1)
|
||||
/** @brief Embedded SRAM mapped at 0x00000000
|
||||
*/
|
||||
#define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
|
||||
SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \
|
||||
}while(0)
|
||||
#endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
|
||||
/** @defgroup HAL_Pin_remap HAL Pin remap
|
||||
* @brief Pin remapping enable/disable macros
|
||||
* @param __PIN_REMAP__ This parameter can be a value of @ref HAL_Pin_remapping
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_REMAP_PIN_ENABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \
|
||||
SYSCFG->CFGR1 |= (__PIN_REMAP__); \
|
||||
}while(0)
|
||||
#define __HAL_REMAP_PIN_DISABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \
|
||||
SYSCFG->CFGR1 &= ~(__PIN_REMAP__); \
|
||||
}while(0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
|
||||
|
||||
/** @brief Fast-mode Plus driving capability enable/disable macros
|
||||
* @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values.
|
||||
* That you can find above these macros.
|
||||
*/
|
||||
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
|
||||
SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
|
||||
}while(0)
|
||||
|
||||
#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
|
||||
CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
|
||||
}while(0)
|
||||
#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
|
||||
/** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
|
||||
* @{
|
||||
*/
|
||||
/** @brief SYSCFG Break Lockup lock
|
||||
* Enables and locks the connection of Cortex-M0 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input
|
||||
* @note The selected configuration is locked and can be unlocked by system reset
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
|
||||
SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \
|
||||
}while(0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
|
||||
|
||||
#if defined(SYSCFG_CFGR2_PVD_LOCK)
|
||||
/** @defgroup PVD_Lock_Enable PVD Lock
|
||||
* @{
|
||||
*/
|
||||
/** @brief SYSCFG Break PVD lock
|
||||
* Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
|
||||
* @note The selected configuration is locked and can be unlocked by system reset
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
|
||||
SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \
|
||||
}while(0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* SYSCFG_CFGR2_PVD_LOCK */
|
||||
|
||||
#if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
|
||||
/** @defgroup SRAM_Parity_Lock SRAM Parity Lock
|
||||
* @{
|
||||
*/
|
||||
/** @brief SYSCFG Break SRAM PARITY lock
|
||||
* Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17
|
||||
* @note The selected configuration is locked and can be unlocked by system reset
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \
|
||||
SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \
|
||||
}while(0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */
|
||||
|
||||
#if defined(SYSCFG_CFGR2_SRAM_PEF)
|
||||
/** @defgroup HAL_SYSCFG_Parity_check_on_RAM HAL SYSCFG Parity check on RAM
|
||||
* @brief Parity check on RAM disable macro
|
||||
* @note Disabling the parity check on RAM locks the configuration bit.
|
||||
* To re-enable the parity check on RAM perform a system reset.
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PEF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* SYSCFG_CFGR2_SRAM_PEF */
|
||||
|
||||
|
||||
#if defined(STM32F091xC) || defined (STM32F098xx)
|
||||
/** @defgroup HAL_ISR_wrapper_check HAL ISR wrapper check
|
||||
* @brief ISR wrapper check
|
||||
* @note This feature is applicable on STM32F09x
|
||||
* @note Allow to determine interrupt source per line.
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_GET_PENDING_IT(__SOURCE__) (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFF))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* (STM32F091xC) || defined (STM32F098xx)*/
|
||||
|
||||
#if defined(STM32F091xC) || defined (STM32F098xx)
|
||||
/** @defgroup HAL_SYSCFG_IRDA_modulation_envelope_selection HAL SYSCFG IRDA modulation envelope selection
|
||||
* @brief selection of the modulation envelope signal macro, using bits [7:6] of SYS_CTRL(CFGR1) register
|
||||
* @note This feature is applicable on STM32F09x
|
||||
* @param __SOURCE__ This parameter can be a value of @ref HAL_IRDA_ENV_SEL
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__) do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__))); \
|
||||
SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_IRDA_ENV_SEL); \
|
||||
SYSCFG->CFGR1 |= (__SOURCE__); \
|
||||
}while(0)
|
||||
|
||||
#define __HAL_SYSCFG_GET_IRDA_ENV_SELECTION() ((SYSCFG->CFGR1) & 0x000000C0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* (STM32F091xC) || defined (STM32F098xx)*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Private_Macros HAL Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
|
||||
((FREQ) == HAL_TICK_FREQ_100HZ) || \
|
||||
((FREQ) == HAL_TICK_FREQ_1KHZ))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions ******************************/
|
||||
HAL_StatusTypeDef HAL_Init(void);
|
||||
HAL_StatusTypeDef HAL_DeInit(void);
|
||||
void HAL_MspInit(void);
|
||||
void HAL_MspDeInit(void);
|
||||
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported variables ---------------------------------------------------------*/
|
||||
/** @addtogroup HAL_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
extern __IO uint32_t uwTick;
|
||||
extern uint32_t uwTickPrio;
|
||||
extern HAL_TickFreqTypeDef uwTickFreq;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
void HAL_IncTick(void);
|
||||
void HAL_Delay(uint32_t Delay);
|
||||
uint32_t HAL_GetTick(void);
|
||||
uint32_t HAL_GetTickPrio(void);
|
||||
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
|
||||
HAL_TickFreqTypeDef HAL_GetTickFreq(void);
|
||||
void HAL_SuspendTick(void);
|
||||
void HAL_ResumeTick(void);
|
||||
uint32_t HAL_GetHalVersion(void);
|
||||
uint32_t HAL_GetREVID(void);
|
||||
uint32_t HAL_GetDEVID(void);
|
||||
uint32_t HAL_GetUIDw0(void);
|
||||
uint32_t HAL_GetUIDw1(void);
|
||||
uint32_t HAL_GetUIDw2(void);
|
||||
void HAL_DBGMCU_EnableDBGStopMode(void);
|
||||
void HAL_DBGMCU_DisableDBGStopMode(void);
|
||||
void HAL_DBGMCU_EnableDBGStandbyMode(void);
|
||||
void HAL_DBGMCU_DisableDBGStandbyMode(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0xx_HAL_H */
|
||||
|
||||
|
||||
1017
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h
Normal file
1017
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h
Normal file
File diff suppressed because it is too large
Load Diff
296
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h
Normal file
296
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h
Normal file
@@ -0,0 +1,296 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_adc_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of ADC HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0xx_HAL_ADC_EX_H
|
||||
#define __STM32F0xx_HAL_ADC_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADCEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup ADC_Exported_Constants ADC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
|
||||
#define ADC_CCR_ALL (ADC_CCR_VBATEN | ADC_CCR_TSEN | ADC_CCR_VREFEN)
|
||||
#else
|
||||
#define ADC_CCR_ALL (ADC_CCR_TSEN | ADC_CCR_VREFEN)
|
||||
#endif
|
||||
|
||||
/** @defgroup ADC_External_trigger_source_Regular ADC External trigger source Regular
|
||||
* @{
|
||||
*/
|
||||
/* List of external triggers with generic trigger name, sorted by trigger */
|
||||
/* name: */
|
||||
|
||||
/* External triggers of regular group for ADC1 */
|
||||
#define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO
|
||||
#define ADC_EXTERNALTRIGCONV_T1_CC4 ADC1_2_EXTERNALTRIG_T1_CC4
|
||||
#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
|
||||
#define ADC_SOFTWARE_START (ADC_CFGR1_EXTSEL + 1U)
|
||||
|
||||
#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
|
||||
#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO
|
||||
#endif
|
||||
|
||||
#if !defined(STM32F030x6) && !defined(STM32F070x6) && !defined(STM32F042x6)
|
||||
#define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_channels ADC channels
|
||||
* @{
|
||||
*/
|
||||
/* Note: Depending on devices, some channels may not be available on package */
|
||||
/* pins. Refer to device datasheet for channels availability. */
|
||||
/* Note: Channels are used by bitfields for setting of channel selection */
|
||||
/* (register ADC_CHSELR) and used by number for setting of analog */
|
||||
/* watchdog channel (bits AWDCH in register ADC_CFGR1). */
|
||||
/* Channels are defined with decimal numbers and converted them to */
|
||||
/* bitfields when needed. */
|
||||
#define ADC_CHANNEL_0 ( 0x00000000U)
|
||||
#define ADC_CHANNEL_1 ( 0x00000001U)
|
||||
#define ADC_CHANNEL_2 ( 0x00000002U)
|
||||
#define ADC_CHANNEL_3 ( 0x00000003U)
|
||||
#define ADC_CHANNEL_4 ( 0x00000004U)
|
||||
#define ADC_CHANNEL_5 ( 0x00000005U)
|
||||
#define ADC_CHANNEL_6 ( 0x00000006U)
|
||||
#define ADC_CHANNEL_7 ( 0x00000007U)
|
||||
#define ADC_CHANNEL_8 ( 0x00000008U)
|
||||
#define ADC_CHANNEL_9 ( 0x00000009U)
|
||||
#define ADC_CHANNEL_10 ( 0x0000000AU)
|
||||
#define ADC_CHANNEL_11 ( 0x0000000BU)
|
||||
#define ADC_CHANNEL_12 ( 0x0000000CU)
|
||||
#define ADC_CHANNEL_13 ( 0x0000000DU)
|
||||
#define ADC_CHANNEL_14 ( 0x0000000EU)
|
||||
#define ADC_CHANNEL_15 ( 0x0000000FU)
|
||||
#define ADC_CHANNEL_16 ( 0x00000010U)
|
||||
#define ADC_CHANNEL_17 ( 0x00000011U)
|
||||
|
||||
#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16
|
||||
#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17
|
||||
|
||||
#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
|
||||
#define ADC_CHANNEL_18 ( 0x00000012U)
|
||||
#define ADC_CHANNEL_VBAT ADC_CHANNEL_18
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup ADCEx_Private_Macros ADCEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
/* Macro reserved for internal HAL driver usage, not intended to be used in */
|
||||
/* code of final user. */
|
||||
|
||||
/**
|
||||
* @brief Test if the selected ADC channel is an internal channel
|
||||
* VrefInt/TempSensor/Vbat
|
||||
* Note: On STM32F0, availability of internal channel Vbat depends on
|
||||
* devices lines.
|
||||
* @param __CHANNEL__ ADC channel
|
||||
* @retval None
|
||||
*/
|
||||
#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
|
||||
#define ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
|
||||
(((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_VBAT) \
|
||||
)
|
||||
#else
|
||||
#define ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
|
||||
(((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_VREFINT) \
|
||||
)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Select the internal measurement path to be enabled/disabled
|
||||
* corresponding to the selected ADC internal channel
|
||||
* VrefInt/TempSensor/Vbat.
|
||||
* Note: On STM32F0, availability of internal channel Vbat depends on
|
||||
* devices lines.
|
||||
* @param __CHANNEL__ ADC channel
|
||||
* @retval Bit of register ADC_CCR
|
||||
*/
|
||||
#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
|
||||
#define ADC_CHANNEL_INTERNAL_PATH(__CHANNEL__) \
|
||||
(( (__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR \
|
||||
)? \
|
||||
(ADC_CCR_TSEN) \
|
||||
: \
|
||||
( \
|
||||
( (__CHANNEL__) == ADC_CHANNEL_VREFINT \
|
||||
)? \
|
||||
(ADC_CCR_VREFEN) \
|
||||
: \
|
||||
(ADC_CCR_VBATEN) \
|
||||
) \
|
||||
)
|
||||
#else
|
||||
#define ADC_CHANNEL_INTERNAL_PATH(__CHANNEL__) \
|
||||
(( (__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR \
|
||||
)? \
|
||||
(ADC_CCR_TSEN) \
|
||||
: \
|
||||
(ADC_CCR_VREFEN) \
|
||||
)
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (STM32F030x6) || defined (STM32F070x6)
|
||||
#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC4) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
|
||||
((REGTRIG) == ADC_SOFTWARE_START))
|
||||
#elif defined (STM32F042x6)
|
||||
#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC4) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
|
||||
((REGTRIG) == ADC_SOFTWARE_START))
|
||||
|
||||
#elif defined (STM32F030xC) || defined (STM32F070xB) || defined (STM32F030x8)
|
||||
#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC4) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
|
||||
((REGTRIG) == ADC_SOFTWARE_START))
|
||||
#else
|
||||
#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC4) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
|
||||
((REGTRIG) == ADC_SOFTWARE_START))
|
||||
#endif
|
||||
|
||||
#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
|
||||
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
|
||||
((CHANNEL) == ADC_CHANNEL_1) || \
|
||||
((CHANNEL) == ADC_CHANNEL_2) || \
|
||||
((CHANNEL) == ADC_CHANNEL_3) || \
|
||||
((CHANNEL) == ADC_CHANNEL_4) || \
|
||||
((CHANNEL) == ADC_CHANNEL_5) || \
|
||||
((CHANNEL) == ADC_CHANNEL_6) || \
|
||||
((CHANNEL) == ADC_CHANNEL_7) || \
|
||||
((CHANNEL) == ADC_CHANNEL_8) || \
|
||||
((CHANNEL) == ADC_CHANNEL_9) || \
|
||||
((CHANNEL) == ADC_CHANNEL_10) || \
|
||||
((CHANNEL) == ADC_CHANNEL_11) || \
|
||||
((CHANNEL) == ADC_CHANNEL_12) || \
|
||||
((CHANNEL) == ADC_CHANNEL_13) || \
|
||||
((CHANNEL) == ADC_CHANNEL_14) || \
|
||||
((CHANNEL) == ADC_CHANNEL_15) || \
|
||||
((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \
|
||||
((CHANNEL) == ADC_CHANNEL_VREFINT) || \
|
||||
((CHANNEL) == ADC_CHANNEL_VBAT) )
|
||||
#else
|
||||
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
|
||||
((CHANNEL) == ADC_CHANNEL_1) || \
|
||||
((CHANNEL) == ADC_CHANNEL_2) || \
|
||||
((CHANNEL) == ADC_CHANNEL_3) || \
|
||||
((CHANNEL) == ADC_CHANNEL_4) || \
|
||||
((CHANNEL) == ADC_CHANNEL_5) || \
|
||||
((CHANNEL) == ADC_CHANNEL_6) || \
|
||||
((CHANNEL) == ADC_CHANNEL_7) || \
|
||||
((CHANNEL) == ADC_CHANNEL_8) || \
|
||||
((CHANNEL) == ADC_CHANNEL_9) || \
|
||||
((CHANNEL) == ADC_CHANNEL_10) || \
|
||||
((CHANNEL) == ADC_CHANNEL_11) || \
|
||||
((CHANNEL) == ADC_CHANNEL_12) || \
|
||||
((CHANNEL) == ADC_CHANNEL_13) || \
|
||||
((CHANNEL) == ADC_CHANNEL_14) || \
|
||||
((CHANNEL) == ADC_CHANNEL_15) || \
|
||||
((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \
|
||||
((CHANNEL) == ADC_CHANNEL_VREFINT) )
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup ADCEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
/** @addtogroup ADCEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* ADC calibration */
|
||||
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0xx_HAL_ADC_EX_H */
|
||||
|
||||
|
||||
851
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h
Normal file
851
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h
Normal file
@@ -0,0 +1,851 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_can.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CAN HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F0xx_HAL_CAN_H
|
||||
#define STM32F0xx_HAL_CAN_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (CAN)
|
||||
/** @addtogroup CAN
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CAN_Exported_Types CAN Exported Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */
|
||||
HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
|
||||
HAL_CAN_STATE_LISTENING = 0x02U, /*!< CAN receive process is ongoing */
|
||||
HAL_CAN_STATE_SLEEP_PENDING = 0x03U, /*!< CAN sleep request is pending */
|
||||
HAL_CAN_STATE_SLEEP_ACTIVE = 0x04U, /*!< CAN sleep mode is active */
|
||||
HAL_CAN_STATE_ERROR = 0x05U /*!< CAN error state */
|
||||
|
||||
} HAL_CAN_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Prescaler; /*!< Specifies the length of a time quantum.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the CAN operating mode.
|
||||
This parameter can be a value of @ref CAN_operating_mode */
|
||||
|
||||
uint32_t SyncJumpWidth; /*!< Specifies the maximum number of time quanta the CAN hardware
|
||||
is allowed to lengthen or shorten a bit to perform resynchronization.
|
||||
This parameter can be a value of @ref CAN_synchronisation_jump_width */
|
||||
|
||||
uint32_t TimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1.
|
||||
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
|
||||
|
||||
uint32_t TimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2.
|
||||
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
|
||||
|
||||
FunctionalState TimeTriggeredMode; /*!< Enable or disable the time triggered communication mode.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState AutoBusOff; /*!< Enable or disable the automatic bus-off management.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState AutoWakeUp; /*!< Enable or disable the automatic wake-up mode.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState AutoRetransmission; /*!< Enable or disable the non-automatic retransmission mode.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState ReceiveFifoLocked; /*!< Enable or disable the Receive FIFO Locked mode.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState TransmitFifoPriority;/*!< Enable or disable the transmit FIFO priority.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
} CAN_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN filter configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
|
||||
configuration, first one for a 16-bit configuration).
|
||||
This parameter must be a number between
|
||||
Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||
|
||||
uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
|
||||
configuration, second one for a 16-bit configuration).
|
||||
This parameter must be a number between
|
||||
Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||
|
||||
uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
|
||||
according to the mode (MSBs for a 32-bit configuration,
|
||||
first one for a 16-bit configuration).
|
||||
This parameter must be a number between
|
||||
Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||
|
||||
uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
|
||||
according to the mode (LSBs for a 32-bit configuration,
|
||||
second one for a 16-bit configuration).
|
||||
This parameter must be a number between
|
||||
Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||
|
||||
uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter.
|
||||
This parameter can be a value of @ref CAN_filter_FIFO */
|
||||
|
||||
uint32_t FilterBank; /*!< Specifies the filter bank which will be initialized.
|
||||
This parameter mus be a number between Min_Data = 0 and Max_Data = 13. */
|
||||
|
||||
uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
|
||||
This parameter can be a value of @ref CAN_filter_mode */
|
||||
|
||||
uint32_t FilterScale; /*!< Specifies the filter scale.
|
||||
This parameter can be a value of @ref CAN_filter_scale */
|
||||
|
||||
uint32_t FilterActivation; /*!< Enable or disable the filter.
|
||||
This parameter can be a value of @ref CAN_filter_activation */
|
||||
|
||||
uint32_t SlaveStartFilterBank; /*!< Select the start filter bank for the slave CAN instance.
|
||||
STM32F0xx devices don't support slave CAN instance (dual CAN). Therefore
|
||||
this parameter is meaningless but it has been kept for compatibility across
|
||||
STM32 families. */
|
||||
|
||||
} CAN_FilterTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN Tx message header structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t StdId; /*!< Specifies the standard identifier.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
|
||||
|
||||
uint32_t ExtId; /*!< Specifies the extended identifier.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
|
||||
|
||||
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
|
||||
This parameter can be a value of @ref CAN_identifier_type */
|
||||
|
||||
uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
|
||||
This parameter can be a value of @ref CAN_remote_transmission_request */
|
||||
|
||||
uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
|
||||
|
||||
FunctionalState TransmitGlobalTime; /*!< Specifies whether the timestamp counter value captured on start
|
||||
of frame transmission, is sent in DATA6 and DATA7 replacing pData[6] and pData[7].
|
||||
@note: Time Triggered Communication Mode must be enabled.
|
||||
@note: DLC must be programmed as 8 bytes, in order these 2 bytes are sent.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
} CAN_TxHeaderTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN Rx message header structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t StdId; /*!< Specifies the standard identifier.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
|
||||
|
||||
uint32_t ExtId; /*!< Specifies the extended identifier.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
|
||||
|
||||
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
|
||||
This parameter can be a value of @ref CAN_identifier_type */
|
||||
|
||||
uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
|
||||
This parameter can be a value of @ref CAN_remote_transmission_request */
|
||||
|
||||
uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
|
||||
|
||||
uint32_t Timestamp; /*!< Specifies the timestamp counter value captured on start of frame reception.
|
||||
@note: Time Triggered Communication Mode must be enabled.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF. */
|
||||
|
||||
uint32_t FilterMatchIndex; /*!< Specifies the index of matching acceptance filter element.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
|
||||
|
||||
} CAN_RxHeaderTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN handle Structure definition
|
||||
*/
|
||||
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
||||
typedef struct __CAN_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
|
||||
{
|
||||
CAN_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
CAN_InitTypeDef Init; /*!< CAN required parameters */
|
||||
|
||||
__IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< CAN Error code.
|
||||
This parameter can be a value of @ref CAN_Error_Code */
|
||||
|
||||
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
||||
void (* TxMailbox0CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 0 complete callback */
|
||||
void (* TxMailbox1CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 1 complete callback */
|
||||
void (* TxMailbox2CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 2 complete callback */
|
||||
void (* TxMailbox0AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 0 abort callback */
|
||||
void (* TxMailbox1AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 1 abort callback */
|
||||
void (* TxMailbox2AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 2 abort callback */
|
||||
void (* RxFifo0MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 msg pending callback */
|
||||
void (* RxFifo0FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 full callback */
|
||||
void (* RxFifo1MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 msg pending callback */
|
||||
void (* RxFifo1FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 full callback */
|
||||
void (* SleepCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Sleep callback */
|
||||
void (* WakeUpFromRxMsgCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Wake Up from Rx msg callback */
|
||||
void (* ErrorCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Error callback */
|
||||
|
||||
void (* MspInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp DeInit callback */
|
||||
|
||||
#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
|
||||
} CAN_HandleTypeDef;
|
||||
|
||||
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
||||
/**
|
||||
* @brief HAL CAN common Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID = 0x00U, /*!< CAN Tx Mailbox 0 complete callback ID */
|
||||
HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID = 0x01U, /*!< CAN Tx Mailbox 1 complete callback ID */
|
||||
HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID = 0x02U, /*!< CAN Tx Mailbox 2 complete callback ID */
|
||||
HAL_CAN_TX_MAILBOX0_ABORT_CB_ID = 0x03U, /*!< CAN Tx Mailbox 0 abort callback ID */
|
||||
HAL_CAN_TX_MAILBOX1_ABORT_CB_ID = 0x04U, /*!< CAN Tx Mailbox 1 abort callback ID */
|
||||
HAL_CAN_TX_MAILBOX2_ABORT_CB_ID = 0x05U, /*!< CAN Tx Mailbox 2 abort callback ID */
|
||||
HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID = 0x06U, /*!< CAN Rx FIFO 0 message pending callback ID */
|
||||
HAL_CAN_RX_FIFO0_FULL_CB_ID = 0x07U, /*!< CAN Rx FIFO 0 full callback ID */
|
||||
HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID = 0x08U, /*!< CAN Rx FIFO 1 message pending callback ID */
|
||||
HAL_CAN_RX_FIFO1_FULL_CB_ID = 0x09U, /*!< CAN Rx FIFO 1 full callback ID */
|
||||
HAL_CAN_SLEEP_CB_ID = 0x0AU, /*!< CAN Sleep callback ID */
|
||||
HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID = 0x0BU, /*!< CAN Wake Up from Rx msg callback ID */
|
||||
HAL_CAN_ERROR_CB_ID = 0x0CU, /*!< CAN Error callback ID */
|
||||
|
||||
HAL_CAN_MSPINIT_CB_ID = 0x0DU, /*!< CAN MspInit callback ID */
|
||||
HAL_CAN_MSPDEINIT_CB_ID = 0x0EU, /*!< CAN MspDeInit callback ID */
|
||||
|
||||
} HAL_CAN_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL CAN Callback pointer definition
|
||||
*/
|
||||
typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to a CAN callback function */
|
||||
|
||||
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CAN_Exported_Constants CAN Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Error_Code CAN Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< Protocol Error Warning */
|
||||
#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< Error Passive */
|
||||
#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< Bus-off error */
|
||||
#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */
|
||||
#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */
|
||||
#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */
|
||||
#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive error */
|
||||
#define HAL_CAN_ERROR_BD (0x00000080U) /*!< Bit dominant error */
|
||||
#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< CRC error */
|
||||
#define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */
|
||||
#define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */
|
||||
#define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
|
||||
#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 0 transmit failure due to transmit error */
|
||||
#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 1 transmit failure due to arbitration lost */
|
||||
#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to transmit error */
|
||||
#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 2 transmit failure due to arbitration lost */
|
||||
#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 2 transmit failure due to transmit error */
|
||||
#define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */
|
||||
#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */
|
||||
#define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */
|
||||
#define HAL_CAN_ERROR_NOT_STARTED (0x00100000U) /*!< Peripheral not started */
|
||||
#define HAL_CAN_ERROR_PARAM (0x00200000U) /*!< Parameter error */
|
||||
|
||||
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
||||
#define HAL_CAN_ERROR_INVALID_CALLBACK (0x00400000U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
|
||||
#define HAL_CAN_ERROR_INTERNAL (0x00800000U) /*!< Internal error */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_InitStatus CAN InitStatus
|
||||
* @{
|
||||
*/
|
||||
#define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */
|
||||
#define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_operating_mode CAN Operating Mode
|
||||
* @{
|
||||
*/
|
||||
#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */
|
||||
#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
|
||||
#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
|
||||
#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with
|
||||
silent mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
|
||||
* @{
|
||||
*/
|
||||
#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */
|
||||
#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
|
||||
#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
|
||||
#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
|
||||
* @{
|
||||
*/
|
||||
#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */
|
||||
#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
|
||||
#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
|
||||
#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
|
||||
#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
|
||||
#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
|
||||
#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
|
||||
#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
|
||||
#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
|
||||
#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
|
||||
#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
|
||||
#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
|
||||
#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
|
||||
#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
|
||||
#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
|
||||
#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2
|
||||
* @{
|
||||
*/
|
||||
#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */
|
||||
#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
|
||||
#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
|
||||
#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
|
||||
#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
|
||||
#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
|
||||
#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
|
||||
#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_mode CAN Filter Mode
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FILTERMODE_IDMASK (0x00000000U) /*!< Identifier mask mode */
|
||||
#define CAN_FILTERMODE_IDLIST (0x00000001U) /*!< Identifier list mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_scale CAN Filter Scale
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FILTERSCALE_16BIT (0x00000000U) /*!< Two 16-bit filters */
|
||||
#define CAN_FILTERSCALE_32BIT (0x00000001U) /*!< One 32-bit filter */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_activation CAN Filter Activation
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FILTER_DISABLE (0x00000000U) /*!< Disable filter */
|
||||
#define CAN_FILTER_ENABLE (0x00000001U) /*!< Enable filter */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_FIFO CAN Filter FIFO
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FILTER_FIFO0 (0x00000000U) /*!< Filter FIFO 0 assignment for filter x */
|
||||
#define CAN_FILTER_FIFO1 (0x00000001U) /*!< Filter FIFO 1 assignment for filter x */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_identifier_type CAN Identifier Type
|
||||
* @{
|
||||
*/
|
||||
#define CAN_ID_STD (0x00000000U) /*!< Standard Id */
|
||||
#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
|
||||
* @{
|
||||
*/
|
||||
#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */
|
||||
#define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number
|
||||
* @{
|
||||
*/
|
||||
#define CAN_RX_FIFO0 (0x00000000U) /*!< CAN receive FIFO 0 */
|
||||
#define CAN_RX_FIFO1 (0x00000001U) /*!< CAN receive FIFO 1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Tx_Mailboxes CAN Tx Mailboxes
|
||||
* @{
|
||||
*/
|
||||
#define CAN_TX_MAILBOX0 (0x00000001U) /*!< Tx Mailbox 0 */
|
||||
#define CAN_TX_MAILBOX1 (0x00000002U) /*!< Tx Mailbox 1 */
|
||||
#define CAN_TX_MAILBOX2 (0x00000004U) /*!< Tx Mailbox 2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_flags CAN Flags
|
||||
* @{
|
||||
*/
|
||||
/* Transmit Flags */
|
||||
#define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request complete MailBox 0 flag */
|
||||
#define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox 0 flag */
|
||||
#define CAN_FLAG_ALST0 (0x00000502U) /*!< Arbitration Lost MailBox 0 flag */
|
||||
#define CAN_FLAG_TERR0 (0x00000503U) /*!< Transmission error MailBox 0 flag */
|
||||
#define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request complete MailBox1 flag */
|
||||
#define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox 1 flag */
|
||||
#define CAN_FLAG_ALST1 (0x0000050AU) /*!< Arbitration Lost MailBox 1 flag */
|
||||
#define CAN_FLAG_TERR1 (0x0000050BU) /*!< Transmission error MailBox 1 flag */
|
||||
#define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request complete MailBox2 flag */
|
||||
#define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox 2 flag */
|
||||
#define CAN_FLAG_ALST2 (0x00000512U) /*!< Arbitration Lost MailBox 2 flag */
|
||||
#define CAN_FLAG_TERR2 (0x00000513U) /*!< Transmission error MailBox 2 flag */
|
||||
#define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */
|
||||
#define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 1 empty flag */
|
||||
#define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 2 empty flag */
|
||||
#define CAN_FLAG_LOW0 (0x0000051DU) /*!< Lowest priority mailbox 0 flag */
|
||||
#define CAN_FLAG_LOW1 (0x0000051EU) /*!< Lowest priority mailbox 1 flag */
|
||||
#define CAN_FLAG_LOW2 (0x0000051FU) /*!< Lowest priority mailbox 2 flag */
|
||||
|
||||
/* Receive Flags */
|
||||
#define CAN_FLAG_FF0 (0x00000203U) /*!< RX FIFO 0 Full flag */
|
||||
#define CAN_FLAG_FOV0 (0x00000204U) /*!< RX FIFO 0 Overrun flag */
|
||||
#define CAN_FLAG_FF1 (0x00000403U) /*!< RX FIFO 1 Full flag */
|
||||
#define CAN_FLAG_FOV1 (0x00000404U) /*!< RX FIFO 1 Overrun flag */
|
||||
|
||||
/* Operating Mode Flags */
|
||||
#define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */
|
||||
#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */
|
||||
#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */
|
||||
#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up interrupt flag */
|
||||
#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge interrupt flag */
|
||||
|
||||
/* Error Flags */
|
||||
#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */
|
||||
#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */
|
||||
#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CAN_Interrupts CAN Interrupts
|
||||
* @{
|
||||
*/
|
||||
/* Transmit Interrupt */
|
||||
#define CAN_IT_TX_MAILBOX_EMPTY ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
|
||||
|
||||
/* Receive Interrupts */
|
||||
#define CAN_IT_RX_FIFO0_MSG_PENDING ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
|
||||
#define CAN_IT_RX_FIFO0_FULL ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
|
||||
#define CAN_IT_RX_FIFO0_OVERRUN ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
|
||||
#define CAN_IT_RX_FIFO1_MSG_PENDING ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
|
||||
#define CAN_IT_RX_FIFO1_FULL ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
|
||||
#define CAN_IT_RX_FIFO1_OVERRUN ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
|
||||
|
||||
/* Operating Mode Interrupts */
|
||||
#define CAN_IT_WAKEUP ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
|
||||
#define CAN_IT_SLEEP_ACK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
|
||||
|
||||
/* Error Interrupts */
|
||||
#define CAN_IT_ERROR_WARNING ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
|
||||
#define CAN_IT_ERROR_PASSIVE ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
|
||||
#define CAN_IT_BUSOFF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
|
||||
#define CAN_IT_LAST_ERROR_CODE ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
|
||||
#define CAN_IT_ERROR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup CAN_Exported_Macros CAN Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset CAN handle state
|
||||
* @param __HANDLE__ CAN handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
||||
#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_CAN_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
|
||||
#endif /*USE_HAL_CAN_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Enable the specified CAN interrupts.
|
||||
* @param __HANDLE__ CAN handle.
|
||||
* @param __INTERRUPT__ CAN Interrupt sources to enable.
|
||||
* This parameter can be any combination of @arg CAN_Interrupts
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified CAN interrupts.
|
||||
* @param __HANDLE__ CAN handle.
|
||||
* @param __INTERRUPT__ CAN Interrupt sources to disable.
|
||||
* This parameter can be any combination of @arg CAN_Interrupts
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
|
||||
|
||||
/** @brief Check if the specified CAN interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__ specifies the CAN Handle.
|
||||
* @param __INTERRUPT__ specifies the CAN interrupt source to check.
|
||||
* This parameter can be a value of @arg CAN_Interrupts
|
||||
* @retval The state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) & (__INTERRUPT__))
|
||||
|
||||
/** @brief Check whether the specified CAN flag is set or not.
|
||||
* @param __HANDLE__ specifies the CAN Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of @arg CAN_flags
|
||||
* @retval The state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
|
||||
((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 3U)? ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
|
||||
|
||||
/** @brief Clear the specified CAN pending flag.
|
||||
* @param __HANDLE__ specifies the CAN Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CAN_FLAG_RQCP0: Request complete MailBox 0 Flag
|
||||
* @arg CAN_FLAG_TXOK0: Transmission OK MailBox 0 Flag
|
||||
* @arg CAN_FLAG_ALST0: Arbitration Lost MailBox 0 Flag
|
||||
* @arg CAN_FLAG_TERR0: Transmission error MailBox 0 Flag
|
||||
* @arg CAN_FLAG_RQCP1: Request complete MailBox 1 Flag
|
||||
* @arg CAN_FLAG_TXOK1: Transmission OK MailBox 1 Flag
|
||||
* @arg CAN_FLAG_ALST1: Arbitration Lost MailBox 1 Flag
|
||||
* @arg CAN_FLAG_TERR1: Transmission error MailBox 1 Flag
|
||||
* @arg CAN_FLAG_RQCP2: Request complete MailBox 2 Flag
|
||||
* @arg CAN_FLAG_TXOK2: Transmission OK MailBox 2 Flag
|
||||
* @arg CAN_FLAG_ALST2: Arbitration Lost MailBox 2 Flag
|
||||
* @arg CAN_FLAG_TERR2: Transmission error MailBox 2 Flag
|
||||
* @arg CAN_FLAG_FF0: RX FIFO 0 Full Flag
|
||||
* @arg CAN_FLAG_FOV0: RX FIFO 0 Overrun Flag
|
||||
* @arg CAN_FLAG_FF1: RX FIFO 1 Full Flag
|
||||
* @arg CAN_FLAG_FOV1: RX FIFO 1 Overrun Flag
|
||||
* @arg CAN_FLAG_WKUI: Wake up Interrupt Flag
|
||||
* @arg CAN_FLAG_SLAKI: Sleep acknowledge Interrupt Flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
|
||||
((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup CAN_Exported_Functions CAN Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan);
|
||||
|
||||
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID,
|
||||
void (* pCallback)(CAN_HandleTypeDef *_hcan));
|
||||
HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID);
|
||||
|
||||
#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_Exported_Functions_Group2 Configuration functions
|
||||
* @brief Configuration functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Configuration functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_Exported_Functions_Group3 Control functions
|
||||
* @brief Control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Control functions **********************************************************/
|
||||
HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
|
||||
uint32_t HAL_CAN_IsSleepActive(const CAN_HandleTypeDef *hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader,
|
||||
const uint8_t aData[], uint32_t *pTxMailbox);
|
||||
HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
|
||||
uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan);
|
||||
uint32_t HAL_CAN_IsTxMessagePending(const CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
|
||||
uint32_t HAL_CAN_GetTxTimestamp(const CAN_HandleTypeDef *hcan, uint32_t TxMailbox);
|
||||
HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo,
|
||||
CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]);
|
||||
uint32_t HAL_CAN_GetRxFifoFillLevel(const CAN_HandleTypeDef *hcan, uint32_t RxFifo);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_Exported_Functions_Group4 Interrupts management
|
||||
* @brief Interrupts management
|
||||
* @{
|
||||
*/
|
||||
/* Interrupts management ******************************************************/
|
||||
HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs);
|
||||
HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs);
|
||||
void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_Exported_Functions_Group5 Callback functions
|
||||
* @brief Callback functions
|
||||
* @{
|
||||
*/
|
||||
/* Callbacks functions ********************************************************/
|
||||
|
||||
void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_Exported_Functions_Group6 Peripheral State and Error functions
|
||||
* @brief CAN Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_CAN_StateTypeDef HAL_CAN_GetState(const CAN_HandleTypeDef *hcan);
|
||||
uint32_t HAL_CAN_GetError(const CAN_HandleTypeDef *hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup CAN_Private_Types CAN Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup CAN_Private_Variables CAN Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup CAN_Private_Constants CAN Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FLAG_MASK (0x000000FFU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Macros -----------------------------------------------------------*/
|
||||
/** @defgroup CAN_Private_Macros CAN Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
|
||||
((MODE) == CAN_MODE_LOOPBACK)|| \
|
||||
((MODE) == CAN_MODE_SILENT) || \
|
||||
((MODE) == CAN_MODE_SILENT_LOOPBACK))
|
||||
#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ) || \
|
||||
((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
|
||||
#define IS_CAN_BS1(BS1) (((BS1) == CAN_BS1_1TQ) || ((BS1) == CAN_BS1_2TQ) || \
|
||||
((BS1) == CAN_BS1_3TQ) || ((BS1) == CAN_BS1_4TQ) || \
|
||||
((BS1) == CAN_BS1_5TQ) || ((BS1) == CAN_BS1_6TQ) || \
|
||||
((BS1) == CAN_BS1_7TQ) || ((BS1) == CAN_BS1_8TQ) || \
|
||||
((BS1) == CAN_BS1_9TQ) || ((BS1) == CAN_BS1_10TQ)|| \
|
||||
((BS1) == CAN_BS1_11TQ)|| ((BS1) == CAN_BS1_12TQ)|| \
|
||||
((BS1) == CAN_BS1_13TQ)|| ((BS1) == CAN_BS1_14TQ)|| \
|
||||
((BS1) == CAN_BS1_15TQ)|| ((BS1) == CAN_BS1_16TQ))
|
||||
#define IS_CAN_BS2(BS2) (((BS2) == CAN_BS2_1TQ) || ((BS2) == CAN_BS2_2TQ) || \
|
||||
((BS2) == CAN_BS2_3TQ) || ((BS2) == CAN_BS2_4TQ) || \
|
||||
((BS2) == CAN_BS2_5TQ) || ((BS2) == CAN_BS2_6TQ) || \
|
||||
((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ))
|
||||
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
|
||||
#define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU)
|
||||
#define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U)
|
||||
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
|
||||
((MODE) == CAN_FILTERMODE_IDLIST))
|
||||
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
|
||||
((SCALE) == CAN_FILTERSCALE_32BIT))
|
||||
#define IS_CAN_FILTER_ACTIVATION(ACTIVATION) (((ACTIVATION) == CAN_FILTER_DISABLE) || \
|
||||
((ACTIVATION) == CAN_FILTER_ENABLE))
|
||||
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
|
||||
((FIFO) == CAN_FILTER_FIFO1))
|
||||
#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \
|
||||
((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \
|
||||
((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 ))
|
||||
#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | \
|
||||
CAN_TX_MAILBOX2))
|
||||
#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU)
|
||||
#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU)
|
||||
#define IS_CAN_DLC(DLC) ((DLC) <= 8U)
|
||||
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
|
||||
((IDTYPE) == CAN_ID_EXT))
|
||||
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
|
||||
#define IS_CAN_RX_FIFO(FIFO) (((FIFO) == CAN_RX_FIFO0) || ((FIFO) == CAN_RX_FIFO1))
|
||||
#define IS_CAN_IT(IT) ((IT) <= (CAN_IT_TX_MAILBOX_EMPTY | CAN_IT_RX_FIFO0_MSG_PENDING | \
|
||||
CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO0_OVERRUN | \
|
||||
CAN_IT_RX_FIFO1_MSG_PENDING | CAN_IT_RX_FIFO1_FULL | \
|
||||
CAN_IT_RX_FIFO1_OVERRUN | CAN_IT_WAKEUP | \
|
||||
CAN_IT_SLEEP_ACK | CAN_IT_ERROR_WARNING | \
|
||||
CAN_IT_ERROR_PASSIVE | CAN_IT_BUSOFF | \
|
||||
CAN_IT_LAST_ERROR_CODE | CAN_IT_ERROR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of private macros -----------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#endif /* CAN */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F0xx_HAL_CAN_H */
|
||||
804
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cec.h
Normal file
804
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cec.h
Normal file
@@ -0,0 +1,804 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_cec.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CEC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F0xx_HAL_CEC_H
|
||||
#define STM32F0xx_HAL_CEC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
#if defined (CEC)
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CEC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CEC_Exported_Types CEC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief CEC Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time.
|
||||
It can be one of CEC_Signal_Free_Time
|
||||
and belongs to the set {0,...,7} where
|
||||
0x0 is the default configuration
|
||||
else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */
|
||||
|
||||
uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
|
||||
it can be a value of CEC_Tolerance :
|
||||
it is either CEC_STANDARD_TOLERANCE or CEC_EXTENDED_TOLERANCE */
|
||||
|
||||
uint32_t BRERxStop; /*!< Set BRESTP bit CEC_BRERxStop : specifies whether or not a Bit Rising
|
||||
Error stops the reception.
|
||||
CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
|
||||
CEC_RX_STOP_ON_BRE: reception is stopped. */
|
||||
|
||||
uint32_t BREErrorBitGen; /*!< Set BREGEN bit CEC_BREErrorBitGen : specifies whether or not an
|
||||
Error-Bit is generated on the
|
||||
CEC line upon Bit Rising Error detection.
|
||||
CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
|
||||
CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */
|
||||
|
||||
uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit CEC_LBPEErrorBitGen : specifies whether or not an
|
||||
Error-Bit is generated on the
|
||||
CEC line upon Long Bit Period Error detection.
|
||||
CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
|
||||
CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */
|
||||
|
||||
uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit CEC_BroadCastMsgErrorBitGen : allows to avoid an
|
||||
Error-Bit generation on the CEC line
|
||||
upon an error detected on a broadcast message.
|
||||
|
||||
It supersedes BREGEN and LBPEGEN bits for a broadcast message error
|
||||
handling. It can take two values:
|
||||
|
||||
1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
|
||||
a) BRE detection: error-bit generation on the CEC line if
|
||||
BRESTP=CEC_RX_STOP_ON_BRE and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
|
||||
b) LBPE detection: error-bit generation on the CEC line
|
||||
if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
|
||||
|
||||
2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
|
||||
no error-bit generation in case neither a) nor b) are satisfied.
|
||||
Additionally, there is no error-bit generation in case of Short Bit
|
||||
Period Error detection in a broadcast message while LSTN bit is set. */
|
||||
|
||||
uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit CEC_SFT_Option : specifies when SFT timer starts.
|
||||
CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.
|
||||
CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end
|
||||
of message transmission/reception. */
|
||||
|
||||
uint32_t ListenMode; /*!< Set LSTN bit CEC_Listening_Mode : specifies device listening mode.
|
||||
It can take two values:
|
||||
|
||||
CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed
|
||||
to its own address (OAR). Messages addressed to different destination
|
||||
are ignored.
|
||||
Broadcast messages are always received.
|
||||
|
||||
CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its
|
||||
own address (OAR) with positive acknowledge. Messages addressed to
|
||||
different destination are received, but without interfering with the
|
||||
CEC bus: no acknowledge sent. */
|
||||
|
||||
uint16_t OwnAddress; /*!< Own addresses configuration
|
||||
This parameter can be a value of CEC_OWN_ADDRESS */
|
||||
|
||||
uint8_t *RxBuffer; /*!< CEC Rx buffer pointer */
|
||||
|
||||
|
||||
} CEC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL CEC State definition
|
||||
* @note HAL CEC State value is a combination of 2 different substates: gState and RxState
|
||||
(see CEC_State_Definition).
|
||||
* - gState contains CEC state information related to global Handle management
|
||||
* and also information related to Tx operations.
|
||||
* gState value coding follow below described bitmap :
|
||||
* b7 (not used)
|
||||
* x : Should be set to 0
|
||||
* b6 Error information
|
||||
* 0 : No Error
|
||||
* 1 : Error
|
||||
* b5 CEC peripheral initialization status
|
||||
* 0 : Reset (peripheral not initialized)
|
||||
* 1 : Init done (peripheral initialized. HAL CEC Init function already called)
|
||||
* b4-b3 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b2 Intrinsic process state
|
||||
* 0 : Ready
|
||||
* 1 : Busy (peripheral busy with some configuration or internal operations)
|
||||
* b1 (not used)
|
||||
* x : Should be set to 0
|
||||
* b0 Tx state
|
||||
* 0 : Ready (no Tx operation ongoing)
|
||||
* 1 : Busy (Tx operation ongoing)
|
||||
* - RxState contains information related to Rx operations.
|
||||
* RxState value coding follow below described bitmap :
|
||||
* b7-b6 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b5 CEC peripheral initialization status
|
||||
* 0 : Reset (peripheral not initialized)
|
||||
* 1 : Init done (peripheral initialized)
|
||||
* b4-b2 (not used)
|
||||
* xxx : Should be set to 000
|
||||
* b1 Rx state
|
||||
* 0 : Ready (no Rx operation ongoing)
|
||||
* 1 : Busy (Rx operation ongoing)
|
||||
* b0 (not used)
|
||||
* x : Should be set to 0.
|
||||
*/
|
||||
typedef uint32_t HAL_CEC_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CEC handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __CEC_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
{
|
||||
CEC_TypeDef *Instance; /*!< CEC registers base address */
|
||||
|
||||
CEC_InitTypeDef Init; /*!< CEC communication parameters */
|
||||
|
||||
const uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
|
||||
|
||||
uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
|
||||
|
||||
uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
|
||||
HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management
|
||||
and also related to Tx operations.
|
||||
This parameter can be a value of HAL_CEC_StateTypeDef */
|
||||
|
||||
HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations.
|
||||
This parameter can be a value of HAL_CEC_StateTypeDef */
|
||||
|
||||
uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
|
||||
in case error is reported */
|
||||
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
void (* TxCpltCallback)(struct __CEC_HandleTypeDef
|
||||
*hcec); /*!< CEC Tx Transfer completed callback */
|
||||
void (* RxCpltCallback)(struct __CEC_HandleTypeDef *hcec,
|
||||
uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */
|
||||
void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC error callback */
|
||||
|
||||
void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp DeInit callback */
|
||||
|
||||
#endif /* (USE_HAL_CEC_REGISTER_CALLBACKS) */
|
||||
} CEC_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL CEC Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CEC_TX_CPLT_CB_ID = 0x00U, /*!< CEC Tx Transfer completed callback ID */
|
||||
HAL_CEC_RX_CPLT_CB_ID = 0x01U, /*!< CEC Rx Transfer completed callback ID */
|
||||
HAL_CEC_ERROR_CB_ID = 0x02U, /*!< CEC error callback ID */
|
||||
HAL_CEC_MSPINIT_CB_ID = 0x03U, /*!< CEC Msp Init callback ID */
|
||||
HAL_CEC_MSPDEINIT_CB_ID = 0x04U /*!< CEC Msp DeInit callback ID */
|
||||
} HAL_CEC_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL CEC Callback pointer definition
|
||||
*/
|
||||
typedef void (*pCEC_CallbackTypeDef)(CEC_HandleTypeDef *hcec); /*!< pointer to an CEC callback function */
|
||||
typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
|
||||
uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed
|
||||
callback function */
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CEC_Exported_Constants CEC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup CEC_State_Definition CEC State Code Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CEC_STATE_RESET ((uint32_t)0x00000000) /*!< Peripheral is not yet Initialized
|
||||
Value is allowed for gState and RxState */
|
||||
#define HAL_CEC_STATE_READY ((uint32_t)0x00000020) /*!< Peripheral Initialized and ready for use
|
||||
Value is allowed for gState and RxState */
|
||||
#define HAL_CEC_STATE_BUSY ((uint32_t)0x00000024) /*!< an internal process is ongoing
|
||||
Value is allowed for gState only */
|
||||
#define HAL_CEC_STATE_BUSY_RX ((uint32_t)0x00000022) /*!< Data Reception process is ongoing
|
||||
Value is allowed for RxState only */
|
||||
#define HAL_CEC_STATE_BUSY_TX ((uint32_t)0x00000021) /*!< Data Transmission process is ongoing
|
||||
Value is allowed for gState only */
|
||||
#define HAL_CEC_STATE_BUSY_RX_TX ((uint32_t)0x00000023) /*!< an internal process is ongoing
|
||||
Value is allowed for gState only */
|
||||
#define HAL_CEC_STATE_ERROR ((uint32_t)0x00000050) /*!< Error Value is allowed for gState only */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup CEC_Error_Code CEC Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CEC_ERROR_NONE (uint32_t) 0x0000U /*!< no error */
|
||||
#define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */
|
||||
#define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */
|
||||
#define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */
|
||||
#define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE /*!< CEC Rx Long Bit period Error */
|
||||
#define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE /*!< CEC Rx Missing Acknowledge */
|
||||
#define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST /*!< CEC Arbitration Lost */
|
||||
#define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */
|
||||
#define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */
|
||||
#define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_CEC_ERROR_INVALID_CALLBACK ((uint32_t)0x00002000U) /*!< Invalid Callback Error */
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter
|
||||
* @{
|
||||
*/
|
||||
#define CEC_DEFAULT_SFT ((uint32_t)0x00000000U)
|
||||
#define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001U)
|
||||
#define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002U)
|
||||
#define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003U)
|
||||
#define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004U)
|
||||
#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005U)
|
||||
#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006U)
|
||||
#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Tolerance CEC Receiver Tolerance
|
||||
* @{
|
||||
*/
|
||||
#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000U)
|
||||
#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_BRERxStop CEC Reception Stop on Error
|
||||
* @{
|
||||
*/
|
||||
#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000U)
|
||||
#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported
|
||||
* @{
|
||||
*/
|
||||
#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
|
||||
#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported
|
||||
* @{
|
||||
*/
|
||||
#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
|
||||
#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message
|
||||
* @{
|
||||
*/
|
||||
#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000U)
|
||||
#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_SFT_Option CEC Signal Free Time start option
|
||||
* @{
|
||||
*/
|
||||
#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000U)
|
||||
#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Listening_Mode CEC Listening mode option
|
||||
* @{
|
||||
*/
|
||||
#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000U)
|
||||
#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register
|
||||
* @{
|
||||
*/
|
||||
#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
|
||||
* @{
|
||||
*/
|
||||
#define CEC_INITIATOR_LSB_POS ((uint32_t) 4U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_OWN_ADDRESS CEC Own Address
|
||||
* @{
|
||||
*/
|
||||
#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
|
||||
#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */
|
||||
#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */
|
||||
#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */
|
||||
#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */
|
||||
#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */
|
||||
#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */
|
||||
#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */
|
||||
#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */
|
||||
#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */
|
||||
#define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */
|
||||
#define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */
|
||||
#define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */
|
||||
#define CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13 */
|
||||
#define CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14 */
|
||||
#define CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition
|
||||
* @{
|
||||
*/
|
||||
#define CEC_IT_TXACKE CEC_IER_TXACKEIE
|
||||
#define CEC_IT_TXERR CEC_IER_TXERRIE
|
||||
#define CEC_IT_TXUDR CEC_IER_TXUDRIE
|
||||
#define CEC_IT_TXEND CEC_IER_TXENDIE
|
||||
#define CEC_IT_TXBR CEC_IER_TXBRIE
|
||||
#define CEC_IT_ARBLST CEC_IER_ARBLSTIE
|
||||
#define CEC_IT_RXACKE CEC_IER_RXACKEIE
|
||||
#define CEC_IT_LBPE CEC_IER_LBPEIE
|
||||
#define CEC_IT_SBPE CEC_IER_SBPEIE
|
||||
#define CEC_IT_BRE CEC_IER_BREIE
|
||||
#define CEC_IT_RXOVR CEC_IER_RXOVRIE
|
||||
#define CEC_IT_RXEND CEC_IER_RXENDIE
|
||||
#define CEC_IT_RXBR CEC_IER_RXBRIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Flags_Definitions CEC Flags definition
|
||||
* @{
|
||||
*/
|
||||
#define CEC_FLAG_TXACKE CEC_ISR_TXACKE
|
||||
#define CEC_FLAG_TXERR CEC_ISR_TXERR
|
||||
#define CEC_FLAG_TXUDR CEC_ISR_TXUDR
|
||||
#define CEC_FLAG_TXEND CEC_ISR_TXEND
|
||||
#define CEC_FLAG_TXBR CEC_ISR_TXBR
|
||||
#define CEC_FLAG_ARBLST CEC_ISR_ARBLST
|
||||
#define CEC_FLAG_RXACKE CEC_ISR_RXACKE
|
||||
#define CEC_FLAG_LBPE CEC_ISR_LBPE
|
||||
#define CEC_FLAG_SBPE CEC_ISR_SBPE
|
||||
#define CEC_FLAG_BRE CEC_ISR_BRE
|
||||
#define CEC_FLAG_RXOVR CEC_ISR_RXOVR
|
||||
#define CEC_FLAG_RXEND CEC_ISR_RXEND
|
||||
#define CEC_FLAG_RXBR CEC_ISR_RXBR
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
|
||||
* @{
|
||||
*/
|
||||
#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
|
||||
CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
|
||||
* @{
|
||||
*/
|
||||
#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
|
||||
* @{
|
||||
*/
|
||||
#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup CEC_Exported_Macros CEC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset CEC handle gstate & RxState
|
||||
* @param __HANDLE__ CEC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
|
||||
(__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
|
||||
(__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
|
||||
} while(0)
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
/** @brief Checks whether or not the specified CEC interrupt flag is set.
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
|
||||
* @arg CEC_FLAG_TXERR: Tx Error.
|
||||
* @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
|
||||
* @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
|
||||
* @arg CEC_FLAG_TXBR: Tx-Byte Request.
|
||||
* @arg CEC_FLAG_ARBLST: Arbitration Lost
|
||||
* @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
|
||||
* @arg CEC_FLAG_LBPE: Rx Long period Error
|
||||
* @arg CEC_FLAG_SBPE: Rx Short period Error
|
||||
* @arg CEC_FLAG_BRE: Rx Bit Rising Error
|
||||
* @arg CEC_FLAG_RXOVR: Rx Overrun.
|
||||
* @arg CEC_FLAG_RXEND: End Of Reception.
|
||||
* @arg CEC_FLAG_RXBR: Rx-Byte Received.
|
||||
* @retval ITStatus
|
||||
*/
|
||||
#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
|
||||
|
||||
/** @brief Clears the interrupt or status flag when raised (write at 1)
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @param __FLAG__ specifies the interrupt/status flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
|
||||
* @arg CEC_FLAG_TXERR: Tx Error.
|
||||
* @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
|
||||
* @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
|
||||
* @arg CEC_FLAG_TXBR: Tx-Byte Request.
|
||||
* @arg CEC_FLAG_ARBLST: Arbitration Lost
|
||||
* @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
|
||||
* @arg CEC_FLAG_LBPE: Rx Long period Error
|
||||
* @arg CEC_FLAG_SBPE: Rx Short period Error
|
||||
* @arg CEC_FLAG_BRE: Rx Bit Rising Error
|
||||
* @arg CEC_FLAG_RXOVR: Rx Overrun.
|
||||
* @arg CEC_FLAG_RXEND: End Of Reception.
|
||||
* @arg CEC_FLAG_RXBR: Rx-Byte Received.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
|
||||
|
||||
/** @brief Enables the specified CEC interrupt.
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @param __INTERRUPT__ specifies the CEC interrupt to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
|
||||
* @arg CEC_IT_TXERR: Tx Error IT Enable
|
||||
* @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
|
||||
* @arg CEC_IT_TXEND: End of transmission IT Enable
|
||||
* @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
|
||||
* @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
|
||||
* @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
|
||||
* @arg CEC_IT_LBPE: Rx Long period Error IT Enable
|
||||
* @arg CEC_IT_SBPE: Rx Short period Error IT Enable
|
||||
* @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
|
||||
* @arg CEC_IT_RXOVR: Rx Overrun IT Enable
|
||||
* @arg CEC_IT_RXEND: End Of Reception IT Enable
|
||||
* @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disables the specified CEC interrupt.
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @param __INTERRUPT__ specifies the CEC interrupt to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
|
||||
* @arg CEC_IT_TXERR: Tx Error IT Enable
|
||||
* @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
|
||||
* @arg CEC_IT_TXEND: End of transmission IT Enable
|
||||
* @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
|
||||
* @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
|
||||
* @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
|
||||
* @arg CEC_IT_LBPE: Rx Long period Error IT Enable
|
||||
* @arg CEC_IT_SBPE: Rx Short period Error IT Enable
|
||||
* @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
|
||||
* @arg CEC_IT_RXOVR: Rx Overrun IT Enable
|
||||
* @arg CEC_IT_RXEND: End Of Reception IT Enable
|
||||
* @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Checks whether or not the specified CEC interrupt is enabled.
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @param __INTERRUPT__ specifies the CEC interrupt to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
|
||||
* @arg CEC_IT_TXERR: Tx Error IT Enable
|
||||
* @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
|
||||
* @arg CEC_IT_TXEND: End of transmission IT Enable
|
||||
* @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
|
||||
* @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
|
||||
* @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
|
||||
* @arg CEC_IT_LBPE: Rx Long period Error IT Enable
|
||||
* @arg CEC_IT_SBPE: Rx Short period Error IT Enable
|
||||
* @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
|
||||
* @arg CEC_IT_RXOVR: Rx Overrun IT Enable
|
||||
* @arg CEC_IT_RXEND: End Of Reception IT Enable
|
||||
* @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
|
||||
* @retval FlagStatus
|
||||
*/
|
||||
#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
|
||||
|
||||
/** @brief Enables the CEC device
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
|
||||
|
||||
/** @brief Disables the CEC device
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
|
||||
|
||||
/** @brief Set Transmission Start flag
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
|
||||
|
||||
/** @brief Set Transmission End flag
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @retval none
|
||||
* If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
|
||||
*/
|
||||
#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
|
||||
|
||||
/** @brief Get Transmission Start flag
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @retval FlagStatus
|
||||
*/
|
||||
#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
|
||||
|
||||
/** @brief Get Transmission End flag
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @retval FlagStatus
|
||||
*/
|
||||
#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
|
||||
|
||||
/** @brief Clear OAR register
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
|
||||
|
||||
/** @brief Set OAR register (without resetting previously set address in case of multi-address mode)
|
||||
* To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position)
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, \
|
||||
(__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup CEC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CEC_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
|
||||
HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
|
||||
HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
|
||||
void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
|
||||
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID,
|
||||
pCEC_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback(CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec);
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CEC_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ***************************************************/
|
||||
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress,
|
||||
const uint8_t *pData, uint32_t Size);
|
||||
uint32_t HAL_CEC_GetLastReceivedFrameSize(const CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer);
|
||||
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
|
||||
void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CEC_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions ************************************************/
|
||||
HAL_CEC_StateTypeDef HAL_CEC_GetState(const CEC_HandleTypeDef *hcec);
|
||||
uint32_t HAL_CEC_GetError(const CEC_HandleTypeDef *hcec);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup CEC_Private_Types CEC Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup CEC_Private_Variables CEC Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup CEC_Private_Constants CEC Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup CEC_Private_Macros CEC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
|
||||
|
||||
#define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
|
||||
((__RXTOL__) == CEC_EXTENDED_TOLERANCE))
|
||||
|
||||
#define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
|
||||
((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))
|
||||
|
||||
#define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
|
||||
((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))
|
||||
|
||||
#define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
|
||||
((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
|
||||
|
||||
#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) \
|
||||
(((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
|
||||
((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
|
||||
|
||||
#define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
|
||||
((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
|
||||
|
||||
#define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
|
||||
((__MODE__) == CEC_FULL_LISTENING_MODE))
|
||||
|
||||
/** @brief Check CEC message size.
|
||||
* The message size is the payload size: without counting the header,
|
||||
* it varies from 0 byte (ping operation, one header only, no payload) to
|
||||
* 15 bytes (1 opcode and up to 14 operands following the header).
|
||||
* @param __SIZE__ CEC message size.
|
||||
* @retval Test result (TRUE or FALSE).
|
||||
*/
|
||||
#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
|
||||
|
||||
/** @brief Check CEC device Own Address Register (OAR) setting.
|
||||
* OAR address is written in a 15-bit field within CEC_CFGR register.
|
||||
* @param __ADDRESS__ CEC own address.
|
||||
* @retval Test result (TRUE or FALSE).
|
||||
*/
|
||||
#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU)
|
||||
|
||||
/** @brief Check CEC initiator or destination logical address setting.
|
||||
* Initiator and destination addresses are coded over 4 bits.
|
||||
* @param __ADDRESS__ CEC initiator or logical address.
|
||||
* @retval Test result (TRUE or FALSE).
|
||||
*/
|
||||
#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xFU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup CEC_Private_Functions CEC Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* CEC */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F0xxHAL_CEC_H */
|
||||
699
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_comp.h
Normal file
699
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_comp.h
Normal file
@@ -0,0 +1,699 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_comp.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of COMP HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F0xx_HAL_COMP_H
|
||||
#define STM32F0xx_HAL_COMP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined (COMP1) || defined (COMP2)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup COMP COMP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup COMP_Exported_Types COMP Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief COMP Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint32_t InvertingInput; /*!< Selects the inverting input of the comparator.
|
||||
This parameter can be a value of @ref COMP_InvertingInput */
|
||||
|
||||
uint32_t NonInvertingInput; /*!< Selects the non inverting input of the comparator.
|
||||
This parameter can be a value of @ref COMP_NonInvertingInput */
|
||||
|
||||
uint32_t Output; /*!< Selects the output redirection of the comparator.
|
||||
This parameter can be a value of @ref COMP_Output */
|
||||
|
||||
uint32_t OutputPol; /*!< Selects the output polarity of the comparator.
|
||||
This parameter can be a value of @ref COMP_OutputPolarity */
|
||||
|
||||
uint32_t Hysteresis; /*!< Selects the hysteresis voltage of the comparator.
|
||||
This parameter can be a value of @ref COMP_Hysteresis */
|
||||
|
||||
uint32_t Mode; /*!< Selects the operating consumption mode of the comparator
|
||||
to adjust the speed/consumption.
|
||||
This parameter can be a value of @ref COMP_Mode */
|
||||
|
||||
uint32_t WindowMode; /*!< Selects the window mode of the comparator 1 & 2.
|
||||
This parameter can be a value of @ref COMP_WindowMode */
|
||||
|
||||
uint32_t TriggerMode; /*!< Selects the trigger mode of the comparator (interrupt mode).
|
||||
This parameter can be a value of @ref COMP_TriggerMode */
|
||||
|
||||
}COMP_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief COMP Handle Structure definition
|
||||
*/
|
||||
typedef struct __COMP_HandleTypeDef
|
||||
{
|
||||
COMP_TypeDef *Instance; /*!< Register base address */
|
||||
COMP_InitTypeDef Init; /*!< COMP required parameters */
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
__IO uint32_t State; /*!< COMP communication state
|
||||
This parameter can be a value of @ref COMP_State */
|
||||
__IO uint32_t ErrorCode; /*!< COMP Error code */
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
||||
void (* TriggerCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP trigger callback */
|
||||
void (* MspInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp DeInit callback */
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
}COMP_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL COMP Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_COMP_TRIGGER_CB_ID = 0x00U, /*!< COMP trigger callback ID */
|
||||
HAL_COMP_MSPINIT_CB_ID = 0x01U, /*!< COMP Msp Init callback ID */
|
||||
HAL_COMP_MSPDEINIT_CB_ID = 0x02U /*!< COMP Msp DeInit callback ID */
|
||||
} HAL_COMP_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL COMP Callback pointer definition
|
||||
*/
|
||||
typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer to a COMP callback function */
|
||||
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup COMP_Exported_Constants COMP Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Error_Code COMP Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_COMP_ERROR_NONE (0x00U) /*!< No error */
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_COMP_ERROR_INVALID_CALLBACK (0x01U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_State COMP State
|
||||
* @{
|
||||
*/
|
||||
#define HAL_COMP_STATE_RESET (0x00000000U) /*!< COMP not yet initialized or disabled */
|
||||
#define HAL_COMP_STATE_READY (0x00000001U) /*!< COMP initialized and ready for use */
|
||||
#define HAL_COMP_STATE_READY_LOCKED (0x00000011U) /*!< COMP initialized but the configuration is locked */
|
||||
#define HAL_COMP_STATE_BUSY (0x00000002U) /*!< COMP is running */
|
||||
#define HAL_COMP_STATE_BUSY_LOCKED (0x00000012U) /*!< COMP is running and the configuration is locked */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_OutputPolarity COMP OutputPolarity
|
||||
* @{
|
||||
*/
|
||||
#define COMP_OUTPUTPOL_NONINVERTED (0x00000000U) /*!< COMP output on GPIO isn't inverted */
|
||||
#define COMP_OUTPUTPOL_INVERTED COMP_CSR_COMP1POL /*!< COMP output on GPIO is inverted */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Hysteresis COMP Hysteresis
|
||||
* @{
|
||||
*/
|
||||
#define COMP_HYSTERESIS_NONE (0x00000000U) /*!< No hysteresis */
|
||||
#define COMP_HYSTERESIS_LOW COMP_CSR_COMP1HYST_0 /*!< Hysteresis level low */
|
||||
#define COMP_HYSTERESIS_MEDIUM COMP_CSR_COMP1HYST_1 /*!< Hysteresis level medium */
|
||||
#define COMP_HYSTERESIS_HIGH COMP_CSR_COMP1HYST /*!< Hysteresis level high */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Mode COMP Mode
|
||||
* @{
|
||||
*/
|
||||
/* Please refer to the electrical characteristics in the device datasheet for
|
||||
the power consumption values */
|
||||
#define COMP_MODE_HIGHSPEED (0x00000000U) /*!< High Speed */
|
||||
#define COMP_MODE_MEDIUMSPEED COMP_CSR_COMP1MODE_0 /*!< Medium Speed */
|
||||
#define COMP_MODE_LOWPOWER COMP_CSR_COMP1MODE_1 /*!< Low power mode */
|
||||
#define COMP_MODE_ULTRALOWPOWER COMP_CSR_COMP1MODE /*!< Ultra-low power mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_InvertingInput COMP InvertingInput
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define COMP_INVERTINGINPUT_1_4VREFINT (0x00000000U) /*!< 1/4 VREFINT connected to comparator inverting input */
|
||||
#define COMP_INVERTINGINPUT_1_2VREFINT COMP_CSR_COMP1INSEL_0 /*!< 1/2 VREFINT connected to comparator inverting input */
|
||||
#define COMP_INVERTINGINPUT_3_4VREFINT COMP_CSR_COMP1INSEL_1 /*!< 3/4 VREFINT connected to comparator inverting input */
|
||||
#define COMP_INVERTINGINPUT_VREFINT (COMP_CSR_COMP1INSEL_1|COMP_CSR_COMP1INSEL_0) /*!< VREFINT connected to comparator inverting input */
|
||||
#define COMP_INVERTINGINPUT_DAC1 COMP_CSR_COMP1INSEL_2 /*!< DAC_OUT1 (PA4) connected to comparator inverting input */
|
||||
#define COMP_INVERTINGINPUT_DAC1SWITCHCLOSED (COMP_CSR_COMP1INSEL_2|COMP_CSR_COMP1SW1) /*!< DAC_OUT1 (PA4) connected to comparator inverting input
|
||||
and close switch (PA0 for COMP1 only) */
|
||||
#define COMP_INVERTINGINPUT_DAC2 (COMP_CSR_COMP1INSEL_2|COMP_CSR_COMP1INSEL_0) /*!< DAC_OUT2 (PA5) connected to comparator inverting input */
|
||||
#define COMP_INVERTINGINPUT_IO1 (COMP_CSR_COMP1INSEL_2|COMP_CSR_COMP1INSEL_1) /*!< IO (PA0 for COMP1 and PA2 for COMP2) connected to comparator inverting input */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_NonInvertingInput COMP NonInvertingInput
|
||||
* @{
|
||||
*/
|
||||
#define COMP_NONINVERTINGINPUT_IO1 (0x00000000U) /*!< I/O1 (PA1 for COMP1, PA3 for COMP2)
|
||||
connected to comparator non inverting input */
|
||||
#define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP_CSR_COMP1SW1 /*!< DAC output connected to comparator COMP1 non inverting input */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Output COMP Output
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Output Redirection common for COMP1 and COMP2 */
|
||||
#define COMP_OUTPUT_NONE (0x00000000U) /*!< COMP output isn't connected to other peripherals */
|
||||
#define COMP_OUTPUT_TIM1BKIN COMP_CSR_COMP1OUTSEL_0 /*!< COMP output connected to TIM1 Break Input (BKIN) */
|
||||
#define COMP_OUTPUT_TIM1IC1 COMP_CSR_COMP1OUTSEL_1 /*!< COMP output connected to TIM1 Input Capture 1 */
|
||||
#define COMP_OUTPUT_TIM1OCREFCLR (COMP_CSR_COMP1OUTSEL_1|COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM1 OCREF Clear */
|
||||
#define COMP_OUTPUT_TIM2IC4 COMP_CSR_COMP1OUTSEL_2 /*!< COMP output connected to TIM2 Input Capture 4 */
|
||||
#define COMP_OUTPUT_TIM2OCREFCLR (COMP_CSR_COMP1OUTSEL_2|COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM2 OCREF Clear */
|
||||
#define COMP_OUTPUT_TIM3IC1 (COMP_CSR_COMP1OUTSEL_2|COMP_CSR_COMP1OUTSEL_1) /*!< COMP output connected to TIM3 Input Capture 1 */
|
||||
#define COMP_OUTPUT_TIM3OCREFCLR COMP_CSR_COMP1OUTSEL /*!< COMP output connected to TIM3 OCREF Clear */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_OutputLevel COMP OutputLevel
|
||||
* @{
|
||||
*/
|
||||
/* When output polarity is not inverted, comparator output is low when
|
||||
the non-inverting input is at a lower voltage than the inverting input*/
|
||||
#define COMP_OUTPUTLEVEL_LOW (0x00000000U)
|
||||
/* When output polarity is not inverted, comparator output is high when
|
||||
the non-inverting input is at a higher voltage than the inverting input */
|
||||
#define COMP_OUTPUTLEVEL_HIGH COMP_CSR_COMP1OUT
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_TriggerMode COMP TriggerMode
|
||||
* @{
|
||||
*/
|
||||
#define COMP_TRIGGERMODE_NONE (0x00000000U) /*!< No External Interrupt trigger detection */
|
||||
#define COMP_TRIGGERMODE_IT_RISING (0x00000001U) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define COMP_TRIGGERMODE_IT_FALLING (0x00000002U) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define COMP_TRIGGERMODE_IT_RISING_FALLING (0x00000003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
#define COMP_TRIGGERMODE_EVENT_RISING (0x00000010U) /*!< Event Mode with Rising edge trigger detection */
|
||||
#define COMP_TRIGGERMODE_EVENT_FALLING (0x00000020U) /*!< Event Mode with Falling edge trigger detection */
|
||||
#define COMP_TRIGGERMODE_EVENT_RISING_FALLING (0x00000030U) /*!< Event Mode with Rising/Falling edge trigger detection */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_WindowMode COMP WindowMode
|
||||
* @{
|
||||
*/
|
||||
#define COMP_WINDOWMODE_DISABLE (0x00000000U) /*!< Window mode disabled */
|
||||
#define COMP_WINDOWMODE_ENABLE COMP_CSR_WNDWEN /*!< Window mode enabled: non inverting input of comparator 2
|
||||
is connected to the non inverting input of comparator 1 (PA1) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Flag COMP Flag
|
||||
* @{
|
||||
*/
|
||||
#define COMP_FLAG_LOCK ((uint32_t)COMP_CSR_COMPxLOCK) /*!< Lock flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup COMP_Exported_Macros COMP Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset COMP handle state
|
||||
* @param __HANDLE__ COMP handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_COMP_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").
|
||||
* @param __HANDLE__ COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
#define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)
|
||||
|
||||
/**
|
||||
* @brief Enable the specified comparator.
|
||||
* @param __HANDLE__ COMP handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance == COMP1) ? \
|
||||
SET_BIT(COMP->CSR, COMP_CSR_COMP1EN) : \
|
||||
SET_BIT(COMP->CSR, COMP_CSR_COMP2EN))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified comparator.
|
||||
* @param __HANDLE__ COMP handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance == COMP1) ? \
|
||||
CLEAR_BIT(COMP->CSR, COMP_CSR_COMP1EN) : \
|
||||
CLEAR_BIT(COMP->CSR, COMP_CSR_COMP2EN))
|
||||
|
||||
/**
|
||||
* @brief Lock the specified comparator configuration.
|
||||
* @param __HANDLE__ COMP handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_LOCK(__HANDLE__) (((__HANDLE__)->Instance == COMP1) ? \
|
||||
SET_BIT(COMP->CSR, COMP_CSR_COMP1LOCK) : \
|
||||
SET_BIT(COMP->CSR, COMP_CSR_COMP2LOCK))
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP1 EXTI line rising edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP1 EXTI line rising edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP1 EXTI line falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP1 EXTI line falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP1 EXTI line rising & falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
|
||||
__HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); \
|
||||
__HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP1 EXTI line rising & falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
|
||||
__HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); \
|
||||
__HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP1 EXTI line in interrupt mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP1 EXTI line in interrupt mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Generate a software interrupt on the COMP1 EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP1 EXTI Line in event mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP1 EXTI Line in event mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Check whether the COMP1 EXTI line flag is set or not.
|
||||
* @retval RESET or SET
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Clear the COMP1 EXTI flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP2 EXTI line rising edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP2 EXTI line rising edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP2 EXTI line falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP2 EXTI line falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP2 EXTI line rising & falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
|
||||
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); \
|
||||
__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP2 EXTI line rising & falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
|
||||
__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); \
|
||||
__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP2 EXTI line in interrupt mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP2 EXTI line in interrupt mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Generate a software interrupt on the COMP2 EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP2 EXTI Line in event mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP2 EXTI Line in event mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Check whether the COMP2 EXTI line flag is set or not.
|
||||
* @retval RESET or SET
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Clear the COMP2 EXTI flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/** @brief Check whether the specified COMP flag is set or not.
|
||||
* @param __HANDLE__ specifies the COMP Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg COMP_FLAG_LOCK: lock flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->CSR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup COMP_Exported_Functions COMP Exported Functions
|
||||
* @{
|
||||
*/
|
||||
/** @addtogroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
|
||||
HAL_StatusTypeDef HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp);
|
||||
void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
|
||||
void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
|
||||
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup COMP_Exported_Functions_Group2 I/O operation functions
|
||||
* @brief Data transfers functions
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
|
||||
HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
|
||||
HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp);
|
||||
HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp);
|
||||
void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup COMP_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @brief management functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
|
||||
uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp);
|
||||
|
||||
/* Callback in Interrupt mode */
|
||||
void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup COMP_Exported_Functions_Group4 Peripheral State functions
|
||||
* @brief Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
uint32_t HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
|
||||
uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup COMP_Private_Constants COMP Private Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup COMP_ExtiLine COMP EXTI Lines
|
||||
* Elements values convention: XXXX0000
|
||||
* - XXXX : Interrupt mask in the EMR/IMR/RTSR/FTSR register
|
||||
* @{
|
||||
*/
|
||||
#define COMP_EXTI_LINE_COMP1 ((uint32_t)EXTI_IMR_MR21) /*!< EXTI line 21 connected to COMP1 output */
|
||||
#define COMP_EXTI_LINE_COMP2 ((uint32_t)EXTI_IMR_MR22) /*!< EXTI line 22 connected to COMP2 output */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup COMP_Private_Macros COMP Private Macros
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup COMP_GET_EXTI_LINE COMP Private macros to get EXTI line associated with Comparators
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Get the specified EXTI line for a comparator instance.
|
||||
* @param __INSTANCE__ specifies the COMP instance.
|
||||
* @retval value of @ref COMP_ExtiLine
|
||||
*/
|
||||
#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 : \
|
||||
COMP_EXTI_LINE_COMP2)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_IS_COMP_Definitions COMP Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_COMP_OUTPUTPOL(POL) (((POL) == COMP_OUTPUTPOL_NONINVERTED) || \
|
||||
((POL) == COMP_OUTPUTPOL_INVERTED))
|
||||
|
||||
#define IS_COMP_HYSTERESIS(HYSTERESIS) (((HYSTERESIS) == COMP_HYSTERESIS_NONE) || \
|
||||
((HYSTERESIS) == COMP_HYSTERESIS_LOW) || \
|
||||
((HYSTERESIS) == COMP_HYSTERESIS_MEDIUM) || \
|
||||
((HYSTERESIS) == COMP_HYSTERESIS_HIGH))
|
||||
|
||||
#define IS_COMP_MODE(MODE) (((MODE) == COMP_MODE_HIGHSPEED) || \
|
||||
((MODE) == COMP_MODE_MEDIUMSPEED) || \
|
||||
((MODE) == COMP_MODE_LOWPOWER) || \
|
||||
((MODE) == COMP_MODE_ULTRALOWPOWER))
|
||||
|
||||
#define IS_COMP_INVERTINGINPUT(INPUT) (((INPUT) == COMP_INVERTINGINPUT_1_4VREFINT) || \
|
||||
((INPUT) == COMP_INVERTINGINPUT_1_2VREFINT) || \
|
||||
((INPUT) == COMP_INVERTINGINPUT_3_4VREFINT) || \
|
||||
((INPUT) == COMP_INVERTINGINPUT_VREFINT) || \
|
||||
((INPUT) == COMP_INVERTINGINPUT_DAC1) || \
|
||||
((INPUT) == COMP_INVERTINGINPUT_DAC1SWITCHCLOSED) || \
|
||||
((INPUT) == COMP_INVERTINGINPUT_DAC2) || \
|
||||
((INPUT) == COMP_INVERTINGINPUT_IO1))
|
||||
|
||||
#define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
|
||||
((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED))
|
||||
|
||||
#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_NONE) || \
|
||||
((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
|
||||
((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
|
||||
((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
|
||||
((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
|
||||
((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
|
||||
((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
|
||||
((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR))
|
||||
|
||||
#define IS_COMP_WINDOWMODE(WINDOWMODE) (((WINDOWMODE) == COMP_WINDOWMODE_DISABLE) || \
|
||||
((WINDOWMODE) == COMP_WINDOWMODE_ENABLE))
|
||||
|
||||
#define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \
|
||||
((__MODE__) == COMP_TRIGGERMODE_IT_RISING) || \
|
||||
((__MODE__) == COMP_TRIGGERMODE_IT_FALLING) || \
|
||||
((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING) || \
|
||||
((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING) || \
|
||||
((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING) || \
|
||||
((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Lock COMP Lock
|
||||
* @{
|
||||
*/
|
||||
#define COMP_LOCK_DISABLE (0x00000000U)
|
||||
#define COMP_LOCK_ENABLE COMP_CSR_COMP1LOCK
|
||||
|
||||
#define COMP_STATE_BIT_LOCK (0x10U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* COMP1 || COMP2 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F0xx_HAL_COMP_H */
|
||||
|
||||
|
||||
|
||||
324
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_conf_template.h
Normal file
324
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_conf_template.h
Normal file
@@ -0,0 +1,324 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_conf.h
|
||||
* @author MCD Application Team
|
||||
* @brief HAL configuration file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0xx_HAL_CONF_H
|
||||
#define __STM32F0xx_HAL_CONF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/* ########################## Module Selection ############################## */
|
||||
/**
|
||||
* @brief This is the list of modules to be used in the HAL driver
|
||||
*/
|
||||
#define HAL_MODULE_ENABLED
|
||||
#define HAL_ADC_MODULE_ENABLED
|
||||
/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
|
||||
#define HAL_CAN_MODULE_ENABLED
|
||||
#define HAL_CEC_MODULE_ENABLED
|
||||
#define HAL_COMP_MODULE_ENABLED
|
||||
#define HAL_CORTEX_MODULE_ENABLED
|
||||
#define HAL_CRC_MODULE_ENABLED
|
||||
#define HAL_DAC_MODULE_ENABLED
|
||||
#define HAL_DMA_MODULE_ENABLED
|
||||
#define HAL_FLASH_MODULE_ENABLED
|
||||
#define HAL_GPIO_MODULE_ENABLED
|
||||
#define HAL_EXTI_MODULE_ENABLED
|
||||
#define HAL_I2C_MODULE_ENABLED
|
||||
#define HAL_I2S_MODULE_ENABLED
|
||||
#define HAL_IRDA_MODULE_ENABLED
|
||||
#define HAL_IWDG_MODULE_ENABLED
|
||||
#define HAL_PCD_MODULE_ENABLED
|
||||
#define HAL_PWR_MODULE_ENABLED
|
||||
#define HAL_RCC_MODULE_ENABLED
|
||||
#define HAL_RTC_MODULE_ENABLED
|
||||
#define HAL_SMARTCARD_MODULE_ENABLED
|
||||
#define HAL_SMBUS_MODULE_ENABLED
|
||||
#define HAL_SPI_MODULE_ENABLED
|
||||
#define HAL_TIM_MODULE_ENABLED
|
||||
#define HAL_TSC_MODULE_ENABLED
|
||||
#define HAL_UART_MODULE_ENABLED
|
||||
#define HAL_USART_MODULE_ENABLED
|
||||
#define HAL_WWDG_MODULE_ENABLED
|
||||
|
||||
/* ######################### Oscillator Values adaptation ################### */
|
||||
/**
|
||||
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSE is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
/**
|
||||
* @brief In the following line adjust the External High Speed oscillator (HSE) Startup
|
||||
* Timeout value
|
||||
*/
|
||||
#if !defined (HSE_STARTUP_TIMEOUT)
|
||||
#define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
|
||||
#endif /* HSE_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief Internal High Speed oscillator (HSI) value.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSI is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE 8000000U /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/**
|
||||
* @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
|
||||
* Timeout value
|
||||
*/
|
||||
#if !defined (HSI_STARTUP_TIMEOUT)
|
||||
#define HSI_STARTUP_TIMEOUT 5000U /*!< Time out for HSI start up */
|
||||
#endif /* HSI_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief Internal High Speed oscillator for ADC (HSI14) value.
|
||||
*/
|
||||
#if !defined (HSI14_VALUE)
|
||||
#define HSI14_VALUE 14000000U /*!< Value of the Internal High Speed oscillator for ADC in Hz.
|
||||
The real value may vary depending on the variations
|
||||
in voltage and temperature. */
|
||||
#endif /* HSI14_VALUE */
|
||||
|
||||
/**
|
||||
* @brief Internal High Speed oscillator for USB (HSI48) value.
|
||||
*/
|
||||
#if !defined (HSI48_VALUE)
|
||||
#define HSI48_VALUE 48000000U /*!< Value of the Internal High Speed oscillator for USB in Hz.
|
||||
The real value may vary depending on the variations
|
||||
in voltage and temperature. */
|
||||
#endif /* HSI48_VALUE */
|
||||
|
||||
/**
|
||||
* @brief Internal Low Speed oscillator (LSI) value.
|
||||
*/
|
||||
#if !defined (LSI_VALUE)
|
||||
#define LSI_VALUE 32000U
|
||||
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
|
||||
The real value may vary depending on the variations
|
||||
in voltage and temperature. */
|
||||
/**
|
||||
* @brief External Low Speed oscillator (LSE) value.
|
||||
*/
|
||||
#if !defined (LSE_VALUE)
|
||||
#define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */
|
||||
#endif /* LSE_VALUE */
|
||||
|
||||
/**
|
||||
* @brief Time out for LSE start up value in ms.
|
||||
*/
|
||||
#if !defined (LSE_STARTUP_TIMEOUT)
|
||||
#define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
|
||||
#endif /* LSE_STARTUP_TIMEOUT */
|
||||
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to use different HSE,
|
||||
=== you can define the HSE value in your toolchain compiler preprocessor. */
|
||||
|
||||
/* ########################### System Configuration ######################### */
|
||||
/**
|
||||
* @brief This is the HAL system configuration section
|
||||
*/
|
||||
#define VDD_VALUE 3300U /*!< Value of VDD in mv */
|
||||
#define TICK_INT_PRIORITY ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority (lowest by default) */
|
||||
/* Warning: Must be set to higher priority for HAL_Delay() */
|
||||
/* and HAL_GetTick() usage under interrupt context */
|
||||
#define USE_RTOS 0U
|
||||
#define PREFETCH_ENABLE 1U
|
||||
#define INSTRUCTION_CACHE_ENABLE 0U
|
||||
#define DATA_CACHE_ENABLE 0U
|
||||
#define USE_SPI_CRC 1U
|
||||
|
||||
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
|
||||
#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */
|
||||
#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */
|
||||
#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
|
||||
#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
|
||||
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
|
||||
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
|
||||
#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
|
||||
#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
|
||||
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
|
||||
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
|
||||
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
|
||||
#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
|
||||
#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
|
||||
#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
|
||||
#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
|
||||
#define USE_HAL_TSC_REGISTER_CALLBACKS 0U /* TSC register callback disabled */
|
||||
#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
|
||||
|
||||
/* ########################## Assert Selection ############################## */
|
||||
/**
|
||||
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
||||
* HAL drivers code
|
||||
*/
|
||||
/*#define USE_FULL_ASSERT 1*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Include module's header file
|
||||
*/
|
||||
|
||||
#ifdef HAL_RCC_MODULE_ENABLED
|
||||
#include "stm32f0xx_hal_rcc.h"
|
||||
#endif /* HAL_RCC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
#include "stm32f0xx_hal_gpio.h"
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_EXTI_MODULE_ENABLED
|
||||
#include "stm32f0xx_hal_exti.h"
|
||||
#endif /* HAL_EXTI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
#include "stm32f0xx_hal_dma.h"
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||
#include "stm32f0xx_hal_cortex.h"
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ADC_MODULE_ENABLED
|
||||
#include "stm32f0xx_hal_adc.h"
|
||||
#endif /* HAL_ADC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CAN_MODULE_ENABLED
|
||||
#include "stm32f0xx_hal_can.h"
|
||||
#endif /* HAL_CAN_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
|
||||
#include "stm32f0xx_hal_can_legacy.h"
|
||||
#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CEC_MODULE_ENABLED
|
||||
#include "stm32f0xx_hal_cec.h"
|
||||
#endif /* HAL_CEC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_COMP_MODULE_ENABLED
|
||||
#include "stm32f0xx_hal_comp.h"
|
||||
#endif /* HAL_COMP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRC_MODULE_ENABLED
|
||||
#include "stm32f0xx_hal_crc.h"
|
||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DAC_MODULE_ENABLED
|
||||
#include "stm32f0xx_hal_dac.h"
|
||||
#endif /* HAL_DAC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
#include "stm32f0xx_hal_flash.h"
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED
|
||||
#include "stm32f0xx_hal_i2c.h"
|
||||
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2S_MODULE_ENABLED
|
||||
#include "stm32f0xx_hal_i2s.h"
|
||||
#endif /* HAL_I2S_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IRDA_MODULE_ENABLED
|
||||
#include "stm32f0xx_hal_irda.h"
|
||||
#endif /* HAL_IRDA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||
#include "stm32f0xx_hal_iwdg.h"
|
||||
#endif /* HAL_IWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PCD_MODULE_ENABLED
|
||||
#include "stm32f0xx_hal_pcd.h"
|
||||
#endif /* HAL_PCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
#include "stm32f0xx_hal_pwr.h"
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RTC_MODULE_ENABLED
|
||||
#include "stm32f0xx_hal_rtc.h"
|
||||
#endif /* HAL_RTC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMARTCARD_MODULE_ENABLED
|
||||
#include "stm32f0xx_hal_smartcard.h"
|
||||
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMBUS_MODULE_ENABLED
|
||||
#include "stm32f0xx_hal_smbus.h"
|
||||
#endif /* HAL_SMBUS_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPI_MODULE_ENABLED
|
||||
#include "stm32f0xx_hal_spi.h"
|
||||
#endif /* HAL_SPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_TIM_MODULE_ENABLED
|
||||
#include "stm32f0xx_hal_tim.h"
|
||||
#endif /* HAL_TIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_TSC_MODULE_ENABLED
|
||||
#include "stm32f0xx_hal_tsc.h"
|
||||
#endif /* HAL_TSC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_UART_MODULE_ENABLED
|
||||
#include "stm32f0xx_hal_uart.h"
|
||||
#endif /* HAL_UART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_USART_MODULE_ENABLED
|
||||
#include "stm32f0xx_hal_usart.h"
|
||||
#endif /* HAL_USART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_WWDG_MODULE_ENABLED
|
||||
#include "stm32f0xx_hal_wwdg.h"
|
||||
#endif /* HAL_WWDG_MODULE_ENABLED */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0xx_HAL_CONF_H */
|
||||
|
||||
|
||||
|
||||
131
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h
Normal file
131
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h
Normal file
@@ -0,0 +1,131 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_cortex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CORTEX HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0xx_HAL_CORTEX_H
|
||||
#define __STM32F0xx_HAL_CORTEX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CORTEX CORTEX
|
||||
* @{
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
|
||||
* @{
|
||||
*/
|
||||
#define SYSTICK_CLKSOURCE_HCLK_DIV8 (0x00000000U)
|
||||
#define SYSTICK_CLKSOURCE_HCLK (0x00000004U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported Macros -----------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup CORTEX_Exported_Functions CORTEX Exported Functions
|
||||
* @{
|
||||
*/
|
||||
/** @addtogroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *******************************/
|
||||
void HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority, uint32_t SubPriority);
|
||||
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_SystemReset(void);
|
||||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief Cortex control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions *************************************************/
|
||||
uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn);
|
||||
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
|
||||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
|
||||
void HAL_SYSTICK_IRQHandler(void);
|
||||
void HAL_SYSTICK_Callback(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4)
|
||||
|
||||
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
|
||||
|
||||
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
|
||||
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0xx_HAL_CORTEX_H */
|
||||
|
||||
|
||||
|
||||
356
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_crc.h
Normal file
356
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_crc.h
Normal file
@@ -0,0 +1,356 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_crc.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CRC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F0xx_HAL_CRC_H
|
||||
#define STM32F0xx_HAL_CRC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Types CRC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief CRC HAL State Structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */
|
||||
HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */
|
||||
HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
|
||||
HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
|
||||
HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */
|
||||
} HAL_CRC_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CRC Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
#if defined(CRC_POL_POL)
|
||||
uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
|
||||
If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
|
||||
X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 +
|
||||
X^4 + X^2+ X +1.
|
||||
In that case, there is no need to set GeneratingPolynomial field.
|
||||
If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and
|
||||
CRCLength fields must be set. */
|
||||
#endif /* CRC_POL_POL */
|
||||
|
||||
uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
|
||||
If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
|
||||
0xFFFFFFFF value. In that case, there is no need to set InitValue field. If
|
||||
otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */
|
||||
|
||||
#if defined(CRC_POL_POL)
|
||||
uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree
|
||||
respectively equal to 7, 8, 16 or 32. This field is written in normal,
|
||||
representation e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1
|
||||
is written 0x65. No need to specify it if DefaultPolynomialUse is set to
|
||||
DEFAULT_POLYNOMIAL_ENABLE. */
|
||||
|
||||
uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
|
||||
Value can be either one of
|
||||
@arg @ref CRC_POLYLENGTH_32B (32-bit CRC),
|
||||
@arg @ref CRC_POLYLENGTH_16B (16-bit CRC),
|
||||
@arg @ref CRC_POLYLENGTH_8B (8-bit CRC),
|
||||
@arg @ref CRC_POLYLENGTH_7B (7-bit CRC). */
|
||||
#endif /* CRC_POL_POL */
|
||||
|
||||
uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
|
||||
is set to DEFAULT_INIT_VALUE_ENABLE. */
|
||||
|
||||
uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
|
||||
Can be either one of the following values
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_NONE no input data inversion
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D
|
||||
becomes 0x58D43CB2
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion,
|
||||
0x1A2B3C4D becomes 0xD458B23C
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D
|
||||
becomes 0xB23CD458 */
|
||||
|
||||
uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
|
||||
Can be either
|
||||
@arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion,
|
||||
@arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted
|
||||
into 0x22CC4488 */
|
||||
} CRC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CRC Handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
CRC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
CRC_InitTypeDef Init; /*!< CRC configuration parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< CRC Locking object */
|
||||
|
||||
__IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
|
||||
|
||||
uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
|
||||
Can be either
|
||||
@arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes
|
||||
(8-bit data)
|
||||
@arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of
|
||||
half-words (16-bit data)
|
||||
@arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words
|
||||
(32-bit data)
|
||||
|
||||
Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization
|
||||
error must occur if InputBufferFormat is not one of the three values listed
|
||||
above */
|
||||
} CRC_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Constants CRC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(CRC_POL_POL)
|
||||
/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial
|
||||
* @{
|
||||
*/
|
||||
#define DEFAULT_CRC32_POLY 0x04C11DB7U /*!< X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* CRC_POL_POL */
|
||||
|
||||
/** @defgroup CRC_Default_InitValue Default CRC computation initialization value
|
||||
* @{
|
||||
*/
|
||||
#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Initial CRC default value */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(CRC_POL_POL)
|
||||
/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used
|
||||
* @{
|
||||
*/
|
||||
#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U) /*!< Enable default generating polynomial 0x04C11DB7 */
|
||||
#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U) /*!< Disable default generating polynomial 0x04C11DB7 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* CRC_POL_POL */
|
||||
|
||||
/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used
|
||||
* @{
|
||||
*/
|
||||
#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U) /*!< Enable initial CRC default value */
|
||||
#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U) /*!< Disable initial CRC default value */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(CRC_POL_POL)
|
||||
/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the peripheral
|
||||
* @{
|
||||
*/
|
||||
#define CRC_POLYLENGTH_32B 0x00000000U /*!< Resort to a 32-bit long generating polynomial */
|
||||
#define CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< Resort to a 16-bit long generating polynomial */
|
||||
#define CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< Resort to a 8-bit long generating polynomial */
|
||||
#define CRC_POLYLENGTH_7B CRC_CR_POLYSIZE /*!< Resort to a 7-bit long generating polynomial */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CRC_LENGTH_32B 32U /*!< 32-bit long CRC */
|
||||
#define HAL_CRC_LENGTH_16B 16U /*!< 16-bit long CRC */
|
||||
#define HAL_CRC_LENGTH_8B 8U /*!< 8-bit long CRC */
|
||||
#define HAL_CRC_LENGTH_7B 7U /*!< 7-bit long CRC */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* CRC_POL_POL */
|
||||
|
||||
/** @defgroup CRC_Input_Buffer_Format Input Buffer Format
|
||||
* @{
|
||||
*/
|
||||
/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
|
||||
* an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
|
||||
* to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
|
||||
* the CRC APIs to provide a correct result */
|
||||
#define CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U /*!< Undefined input data format */
|
||||
#define CRC_INPUTDATA_FORMAT_BYTES 0x00000001U /*!< Input data in byte format */
|
||||
#define CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U /*!< Input data in half-word format */
|
||||
#define CRC_INPUTDATA_FORMAT_WORDS 0x00000003U /*!< Input data in word format */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Macros CRC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset CRC handle state.
|
||||
* @param __HANDLE__ CRC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Reset CRC Data Register.
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
|
||||
|
||||
/**
|
||||
* @brief Set CRC INIT non-default value
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @param __INIT__ 32-bit initial value
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
|
||||
|
||||
/**
|
||||
* @brief Store data in the Independent Data (ID) register.
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @param __VALUE__ Value to be stored in the ID register
|
||||
* @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
|
||||
|
||||
/**
|
||||
* @brief Return the data stored in the Independent Data (ID) register.
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
|
||||
* @retval Value of the ID register
|
||||
*/
|
||||
#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @defgroup CRC_Private_Macros CRC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(CRC_POL_POL)
|
||||
#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
|
||||
((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
|
||||
#endif /* CRC_POL_POL */
|
||||
|
||||
#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
|
||||
((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
|
||||
|
||||
#if defined(CRC_POL_POL)
|
||||
#define IS_CRC_POL_LENGTH(LENGTH) (((LENGTH) == CRC_POLYLENGTH_32B) || \
|
||||
((LENGTH) == CRC_POLYLENGTH_16B) || \
|
||||
((LENGTH) == CRC_POLYLENGTH_8B) || \
|
||||
((LENGTH) == CRC_POLYLENGTH_7B))
|
||||
#endif /* CRC_POL_POL */
|
||||
|
||||
#define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \
|
||||
((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
|
||||
((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include CRC HAL Extended module */
|
||||
#include "stm32f0xx_hal_crc_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Functions CRC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
|
||||
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc);
|
||||
void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
|
||||
void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
|
||||
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F0xx_HAL_CRC_H */
|
||||
150
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_crc_ex.h
Normal file
150
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_crc_ex.h
Normal file
@@ -0,0 +1,150 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_crc_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CRC HAL extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F0xx_HAL_CRC_EX_H
|
||||
#define STM32F0xx_HAL_CRC_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRCEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes
|
||||
* @{
|
||||
*/
|
||||
#define CRC_INPUTDATA_INVERSION_NONE 0x00000000U /*!< No input data inversion */
|
||||
#define CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion */
|
||||
#define CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */
|
||||
#define CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN /*!< Word-wise input data inversion */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes
|
||||
* @{
|
||||
*/
|
||||
#define CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U /*!< No output data inversion */
|
||||
#define CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT /*!< Bit-wise output data inversion */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set CRC output reversal
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
|
||||
|
||||
/**
|
||||
* @brief Unset CRC output reversal
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
|
||||
|
||||
/**
|
||||
* @brief Set CRC non-default polynomial
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @param __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @defgroup CRCEx_Private_Macros CRC Extended Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \
|
||||
((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \
|
||||
((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
|
||||
((MODE) == CRC_INPUTDATA_INVERSION_WORD))
|
||||
|
||||
#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
|
||||
((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup CRCEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRCEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
|
||||
HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
|
||||
HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F0xx_HAL_CRC_EX_H */
|
||||
427
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dac.h
Normal file
427
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dac.h
Normal file
@@ -0,0 +1,427 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_dac.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DAC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F0xx_HAL_DAC_H
|
||||
#define STM32F0xx_HAL_DAC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (DAC1)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup DAC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Exported_Types DAC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */
|
||||
HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */
|
||||
HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */
|
||||
HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */
|
||||
HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */
|
||||
|
||||
}HAL_DAC_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DAC handle Structure definition
|
||||
*/
|
||||
typedef struct __DAC_HandleTypeDef
|
||||
{
|
||||
DAC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
__IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< DAC locking object */
|
||||
|
||||
DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
|
||||
|
||||
DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< DAC Error code */
|
||||
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
|
||||
void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
|
||||
void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
|
||||
void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
|
||||
void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
|
||||
|
||||
void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac);
|
||||
void (* MspDeInitCallback ) (struct __DAC_HandleTypeDef *hdac);
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
}DAC_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DAC Configuration regular Channel structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
|
||||
This parameter can be a value of @ref DAC_trigger_selection */
|
||||
|
||||
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
|
||||
This parameter can be a value of @ref DAC_output_buffer */
|
||||
|
||||
}DAC_ChannelConfTypeDef;
|
||||
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL DAC Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U, /*!< DAC CH1 Complete Callback ID */
|
||||
HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */
|
||||
HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */
|
||||
HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */
|
||||
HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */
|
||||
HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */
|
||||
HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */
|
||||
HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */
|
||||
HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */
|
||||
HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */
|
||||
HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */
|
||||
} HAL_DAC_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DAC Callback pointer definition
|
||||
*/
|
||||
typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Exported_Constants DAC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Error_Code DAC Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DAC_ERROR_NONE 0x00U /*!< No error */
|
||||
#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DMA underrun error */
|
||||
#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DMA underrun error */
|
||||
#define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */
|
||||
#define HAL_DAC_ERROR_TIMEOUT 0x08U /*!< Timeout error */
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U /*!< Invalid callback error */
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_output_buffer DAC output buffer
|
||||
* @{
|
||||
*/
|
||||
#define DAC_OUTPUTBUFFER_ENABLE (0x00000000U)
|
||||
#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_data_alignment DAC data alignment
|
||||
* @{
|
||||
*/
|
||||
#define DAC_ALIGN_12B_R (0x00000000U)
|
||||
#define DAC_ALIGN_12B_L (0x00000004U)
|
||||
#define DAC_ALIGN_8B_R (0x00000008U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_flags_definition DAC flags definition
|
||||
* @{
|
||||
*/
|
||||
#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
|
||||
#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_IT_definition DAC IT definition
|
||||
* @{
|
||||
*/
|
||||
#define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
|
||||
#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Exported_Macros DAC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset DAC handle state
|
||||
* @param __HANDLE__ specifies the DAC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_DAC_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Enable the DAC channel
|
||||
* @param __HANDLE__ specifies the DAC handle.
|
||||
* @param __DAC_Channel__ specifies the DAC channel
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
|
||||
((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
|
||||
|
||||
/** @brief Disable the DAC channel
|
||||
* @param __HANDLE__ specifies the DAC handle
|
||||
* @param __DAC_Channel__ specifies the DAC channel.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
|
||||
((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
|
||||
|
||||
/** @brief Enable the DAC interrupt
|
||||
* @param __HANDLE__ specifies the DAC handle
|
||||
* @param __INTERRUPT__ specifies the DAC interrupt.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
|
||||
* @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable the DAC interrupt
|
||||
* @param __HANDLE__ specifies the DAC handle
|
||||
* @param __INTERRUPT__ specifies the DAC interrupt.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
|
||||
|
||||
/** @brief Check whether the specified DAC interrupt source is enabled or not
|
||||
* @param __HANDLE__ DAC handle
|
||||
* @param __INTERRUPT__ DAC interrupt source to check
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
|
||||
* @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
|
||||
* @retval State of interruption (SET or RESET)
|
||||
*/
|
||||
#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/** @brief Get the selected DAC's flag status
|
||||
* @param __HANDLE__ specifies the DAC handle.
|
||||
* @param __FLAG__ specifies the DAC flag to get.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the DAC's flag
|
||||
* @param __HANDLE__ specifies the DAC handle.
|
||||
* @param __FLAG__ specifies the DAC flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup DAC_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
|
||||
((STATE) == DAC_OUTPUTBUFFER_DISABLE))
|
||||
|
||||
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
|
||||
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
|
||||
((CHANNEL) == DAC_CHANNEL_2))
|
||||
|
||||
#else
|
||||
|
||||
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1))
|
||||
|
||||
#endif /* DAC_CHANNEL2_SUPPORT */
|
||||
|
||||
|
||||
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
|
||||
((ALIGN) == DAC_ALIGN_12B_L) || \
|
||||
((ALIGN) == DAC_ALIGN_8B_R))
|
||||
|
||||
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
|
||||
|
||||
/** @brief Set DHR12R1 alignment
|
||||
* @param __ALIGNMENT__ specifies the DAC alignment
|
||||
* @retval None
|
||||
*/
|
||||
#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) ((0x00000008U) + (__ALIGNMENT__))
|
||||
|
||||
/** @brief Set DHR12R2 alignment
|
||||
* @param __ALIGNMENT__ specifies the DAC alignment
|
||||
* @retval None
|
||||
*/
|
||||
#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) ((0x00000014U) + (__ALIGNMENT__))
|
||||
|
||||
/** @brief Set DHR12RD alignment
|
||||
* @param __ALIGNMENT__ specifies the DAC alignment
|
||||
* @retval None
|
||||
*/
|
||||
#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) ((0x00000020U) + (__ALIGNMENT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include DAC HAL Extension module */
|
||||
#include "stm32f0xx_hal_dac_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
|
||||
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
|
||||
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
|
||||
|
||||
void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
|
||||
|
||||
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
|
||||
|
||||
void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
/* DAC callback registering/unregistering */
|
||||
HAL_StatusTypeDef HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackId, pDAC_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackId);
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
|
||||
|
||||
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
|
||||
uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* DAC1 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32F0xx_HAL_DAC_H */
|
||||
|
||||
|
||||
290
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dac_ex.h
Normal file
290
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dac_ex.h
Normal file
@@ -0,0 +1,290 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_dac_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DAC HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0xx_HAL_DAC_EX_H
|
||||
#define __STM32F0xx_HAL_DAC_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F051x8) || defined(STM32F058xx) || \
|
||||
defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
|
||||
defined(STM32F091xC) || defined(STM32F098xx)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup DACEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangleamplitude
|
||||
* @{
|
||||
*/
|
||||
#define DAC_LFSRUNMASK_BIT0 (0x00000000U) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
|
||||
#define DAC_TRIANGLEAMPLITUDE_1 (0x00000000U) /*!< Select max triangle amplitude of 1 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
|
||||
/** @defgroup DACEx_Exported_Macros DACEx Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_trigger_selection DAC trigger selection
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F051x8) || defined(STM32F058xx)
|
||||
|
||||
#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
|
||||
has been loaded, and not by external trigger */
|
||||
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
|
||||
|
||||
#endif /* STM32F051x8 || STM32F058xx */
|
||||
|
||||
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
|
||||
defined(STM32F091xC) || defined(STM32F098xx)
|
||||
|
||||
#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
|
||||
has been loaded, and not by external trigger */
|
||||
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
|
||||
|
||||
#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
|
||||
/* STM32F091xC || STM32F098xx */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Channel_selection DAC Channel selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
|
||||
defined(STM32F091xC) || defined(STM32F098xx)
|
||||
|
||||
#define DAC_CHANNEL_1 (0x00000000U)
|
||||
#define DAC_CHANNEL_2 (0x00000010U)
|
||||
|
||||
#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
|
||||
/* STM32F091xC || STM32F098xx */
|
||||
|
||||
#if defined(STM32F051x8) || defined(STM32F058xx)
|
||||
|
||||
#define DAC_CHANNEL_1 (0x00000000U)
|
||||
|
||||
#endif /* STM32F051x8 || STM32F058xx */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup DACEx_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
|
||||
defined(STM32F091xC) || defined(STM32F098xx)
|
||||
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
|
||||
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
|
||||
|
||||
#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
|
||||
/* STM32F091xC || STM32F098xx */
|
||||
|
||||
#if defined(STM32F051x8) || defined(STM32F058xx)
|
||||
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
|
||||
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
|
||||
|
||||
#endif /* STM32F051x8 || STM32F058xx */
|
||||
|
||||
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
|
||||
defined(STM32F091xC) || defined(STM32F098xx)
|
||||
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
|
||||
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
|
||||
|
||||
#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
|
||||
/* STM32F091xC || STM32F098xx */
|
||||
|
||||
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup DACEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DACEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
|
||||
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
|
||||
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
|
||||
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
|
||||
|
||||
void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DACEx_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
|
||||
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* STM32F051x8 || STM32F058xx || */
|
||||
/* STM32F071xB || STM32F072xB || STM32F078xx || */
|
||||
/* STM32F091xC || STM32F098xx */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F0xx_HAL_DAC_EX_H */
|
||||
|
||||
179
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h
Normal file
179
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h
Normal file
@@ -0,0 +1,179 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_def.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains HAL common defines, enumeration, macros and
|
||||
* structures definitions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0xx_HAL_DEF
|
||||
#define __STM32F0xx_HAL_DEF
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
#include "Legacy/stm32_hal_legacy.h"
|
||||
#include <stddef.h>
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief HAL Status structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_OK = 0x00U,
|
||||
HAL_ERROR = 0x01U,
|
||||
HAL_BUSY = 0x02U,
|
||||
HAL_TIMEOUT = 0x03U
|
||||
} HAL_StatusTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL Lock structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_UNLOCKED = 0x00U,
|
||||
HAL_LOCKED = 0x01U
|
||||
} HAL_LockTypeDef;
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
#if !defined(UNUSED)
|
||||
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
|
||||
#endif /* UNUSED */
|
||||
|
||||
#define HAL_MAX_DELAY 0xFFFFFFFFU
|
||||
|
||||
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
|
||||
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
|
||||
|
||||
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
|
||||
(__DMA_HANDLE__).Parent = (__HANDLE__); \
|
||||
} while(0U)
|
||||
|
||||
/** @brief Reset the Handle's State field.
|
||||
* @param __HANDLE__ specifies the Peripheral Handle.
|
||||
* @note This macro can be used for the following purpose:
|
||||
* - When the Handle is declared as local variable; before passing it as parameter
|
||||
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
|
||||
* to set to 0 the Handle's "State" field.
|
||||
* Otherwise, "State" field may have any random value and the first time the function
|
||||
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
|
||||
* (i.e. HAL_PPP_MspInit() will not be executed).
|
||||
* - When there is a need to reconfigure the low level hardware: instead of calling
|
||||
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
|
||||
* In this later function, when the Handle's "State" field is set to 0, it will execute the function
|
||||
* HAL_PPP_MspInit() which will reconfigure the low level hardware.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
|
||||
|
||||
#if (USE_RTOS == 1U)
|
||||
/* Reserved for future use */
|
||||
#error " USE_RTOS should be 0 in the current HAL release "
|
||||
#else
|
||||
#define __HAL_LOCK(__HANDLE__) \
|
||||
do{ \
|
||||
if((__HANDLE__)->Lock == HAL_LOCKED) \
|
||||
{ \
|
||||
return HAL_BUSY; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Lock = HAL_LOCKED; \
|
||||
} \
|
||||
}while (0U)
|
||||
|
||||
#define __HAL_UNLOCK(__HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->Lock = HAL_UNLOCKED; \
|
||||
}while (0U)
|
||||
#endif /* USE_RTOS */
|
||||
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
|
||||
#ifndef __weak
|
||||
#define __weak __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __packed
|
||||
#define __packed __attribute__((packed))
|
||||
#endif
|
||||
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
|
||||
#ifndef __weak
|
||||
#define __weak __attribute__((weak))
|
||||
#endif /* __weak */
|
||||
#ifndef __packed
|
||||
#define __packed __attribute__((__packed__))
|
||||
#endif /* __packed */
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
|
||||
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN
|
||||
#endif
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END __attribute__ ((aligned (4)))
|
||||
#endif
|
||||
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END __attribute__ ((aligned (4)))
|
||||
#endif /* __ALIGN_END */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#else
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END
|
||||
#endif /* __ALIGN_END */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#if defined (__CC_ARM) /* ARM Compiler V5*/
|
||||
#define __ALIGN_BEGIN __align(4)
|
||||
#elif defined (__ICCARM__) /* IAR Compiler */
|
||||
#define __ALIGN_BEGIN
|
||||
#endif /* __CC_ARM */
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
/**
|
||||
* @brief __NOINLINE definition
|
||||
*/
|
||||
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
|
||||
/* ARM V4/V5 and V6 & GNU Compiler
|
||||
-------------------------------
|
||||
*/
|
||||
#define __NOINLINE __attribute__ ( (noinline) )
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
/* ICCARM Compiler
|
||||
---------------
|
||||
*/
|
||||
#define __NOINLINE _Pragma("optimize = no_inline")
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ___STM32F0xx_HAL_DEF */
|
||||
|
||||
|
||||
561
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h
Normal file
561
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h
Normal file
@@ -0,0 +1,561 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_dma.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DMA HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0xx_HAL_DMA_H
|
||||
#define __STM32F0xx_HAL_DMA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Exported_Types DMA Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DMA Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
|
||||
from memory to memory or from peripheral to memory.
|
||||
This parameter can be a value of @ref DMA_Data_transfer_direction */
|
||||
|
||||
uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
|
||||
This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
|
||||
|
||||
uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
|
||||
This parameter can be a value of @ref DMA_Memory_incremented_mode */
|
||||
|
||||
uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
|
||||
This parameter can be a value of @ref DMA_Peripheral_data_size */
|
||||
|
||||
uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
|
||||
This parameter can be a value of @ref DMA_Memory_data_size */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_mode
|
||||
@note The circular buffer mode cannot be used if the memory-to-memory
|
||||
data transfer is configured on the selected Channel */
|
||||
|
||||
uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_Priority_level */
|
||||
} DMA_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DMA State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
|
||||
HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
|
||||
HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
|
||||
HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */
|
||||
} HAL_DMA_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DMA Error Code structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
|
||||
HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
|
||||
} HAL_DMA_LevelCompleteTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DMA Callback ID structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
|
||||
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
|
||||
HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
|
||||
HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
|
||||
HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
|
||||
|
||||
} HAL_DMA_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMA handle Structure definition
|
||||
*/
|
||||
typedef struct __DMA_HandleTypeDef
|
||||
{
|
||||
DMA_Channel_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
DMA_InitTypeDef Init; /*!< DMA communication parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< DMA locking object */
|
||||
|
||||
__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
|
||||
|
||||
void *Parent; /*!< Parent object state */
|
||||
|
||||
void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */
|
||||
|
||||
void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */
|
||||
|
||||
void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */
|
||||
|
||||
void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< DMA Error code */
|
||||
|
||||
DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
|
||||
|
||||
uint32_t ChannelIndex; /*!< DMA Channel Index */
|
||||
} DMA_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Exported_Constants DMA Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Error_Code DMA Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */
|
||||
#define HAL_DMA_ERROR_NO_XFER (0x00000004U) /*!< no ongoin transfer */
|
||||
#define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
|
||||
#define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PERIPH_TO_MEMORY (0x00000000U) /*!< Peripheral to memory direction */
|
||||
#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
|
||||
#define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
|
||||
#define DMA_PINC_DISABLE (0x00000000U) /*!< Peripheral increment mode Disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
|
||||
#define DMA_MINC_DISABLE (0x00000000U) /*!< Memory increment mode Disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PDATAALIGN_BYTE (0x00000000U) /*!< Peripheral data alignment : Byte */
|
||||
#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
|
||||
#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Memory_data_size DMA Memory data size
|
||||
* @{
|
||||
*/
|
||||
#define DMA_MDATAALIGN_BYTE (0x00000000U) /*!< Memory data alignment : Byte */
|
||||
#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
|
||||
#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_mode DMA mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_NORMAL (0x00000000U) /*!< Normal Mode */
|
||||
#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Priority_level DMA Priority level
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PRIORITY_LOW (0x00000000U) /*!< Priority level : Low */
|
||||
#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
|
||||
#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
|
||||
#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
|
||||
* @{
|
||||
*/
|
||||
#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
|
||||
#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
|
||||
#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_flag_definitions DMA flag definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_FLAG_GL1 (0x00000001U) /*!< Channel 1 global interrupt flag */
|
||||
#define DMA_FLAG_TC1 (0x00000002U) /*!< Channel 1 transfer complete flag */
|
||||
#define DMA_FLAG_HT1 (0x00000004U) /*!< Channel 1 half transfer flag */
|
||||
#define DMA_FLAG_TE1 (0x00000008U) /*!< Channel 1 transfer error flag */
|
||||
#define DMA_FLAG_GL2 (0x00000010U) /*!< Channel 2 global interrupt flag */
|
||||
#define DMA_FLAG_TC2 (0x00000020U) /*!< Channel 2 transfer complete flag */
|
||||
#define DMA_FLAG_HT2 (0x00000040U) /*!< Channel 2 half transfer flag */
|
||||
#define DMA_FLAG_TE2 (0x00000080U) /*!< Channel 2 transfer error flag */
|
||||
#define DMA_FLAG_GL3 (0x00000100U) /*!< Channel 3 global interrupt flag */
|
||||
#define DMA_FLAG_TC3 (0x00000200U) /*!< Channel 3 transfer complete flag */
|
||||
#define DMA_FLAG_HT3 (0x00000400U) /*!< Channel 3 half transfer flag */
|
||||
#define DMA_FLAG_TE3 (0x00000800U) /*!< Channel 3 transfer error flag */
|
||||
#define DMA_FLAG_GL4 (0x00001000U) /*!< Channel 4 global interrupt flag */
|
||||
#define DMA_FLAG_TC4 (0x00002000U) /*!< Channel 4 transfer complete flag */
|
||||
#define DMA_FLAG_HT4 (0x00004000U) /*!< Channel 4 half transfer flag */
|
||||
#define DMA_FLAG_TE4 (0x00008000U) /*!< Channel 4 transfer error flag */
|
||||
#define DMA_FLAG_GL5 (0x00010000U) /*!< Channel 5 global interrupt flag */
|
||||
#define DMA_FLAG_TC5 (0x00020000U) /*!< Channel 5 transfer complete flag */
|
||||
#define DMA_FLAG_HT5 (0x00040000U) /*!< Channel 5 half transfer flag */
|
||||
#define DMA_FLAG_TE5 (0x00080000U) /*!< Channel 5 transfer error flag */
|
||||
#define DMA_FLAG_GL6 (0x00100000U) /*!< Channel 6 global interrupt flag */
|
||||
#define DMA_FLAG_TC6 (0x00200000U) /*!< Channel 6 transfer complete flag */
|
||||
#define DMA_FLAG_HT6 (0x00400000U) /*!< Channel 6 half transfer flag */
|
||||
#define DMA_FLAG_TE6 (0x00800000U) /*!< Channel 6 transfer error flag */
|
||||
#define DMA_FLAG_GL7 (0x01000000U) /*!< Channel 7 global interrupt flag */
|
||||
#define DMA_FLAG_TC7 (0x02000000U) /*!< Channel 7 transfer complete flag */
|
||||
#define DMA_FLAG_HT7 (0x04000000U) /*!< Channel 7 half transfer flag */
|
||||
#define DMA_FLAG_TE7 (0x08000000U) /*!< Channel 7 transfer error flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(SYSCFG_CFGR1_DMA_RMP)
|
||||
/** @defgroup HAL_DMA_remapping HAL DMA remapping
|
||||
* Elements values convention: 0xYYYYYYYY
|
||||
* - YYYYYYYY : Position in the SYSCFG register CFGR1
|
||||
* @{
|
||||
*/
|
||||
#define DMA_REMAP_ADC_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_ADC_DMA_RMP) /*!< ADC DMA remap
|
||||
0: No remap (ADC DMA requests mapped on DMA channel 1
|
||||
1: Remap (ADC DMA requests mapped on DMA channel 2 */
|
||||
#define DMA_REMAP_USART1_TX_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1 TX DMA remap
|
||||
0: No remap (USART1_TX DMA request mapped on DMA channel 2
|
||||
1: Remap (USART1_TX DMA request mapped on DMA channel 4 */
|
||||
#define DMA_REMAP_USART1_RX_DMA_CH5 ((uint32_t)SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1 RX DMA remap
|
||||
0: No remap (USART1_RX DMA request mapped on DMA channel 3
|
||||
1: Remap (USART1_RX DMA request mapped on DMA channel 5 */
|
||||
#define DMA_REMAP_TIM16_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16 DMA request remap
|
||||
0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3)
|
||||
1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4) */
|
||||
#define DMA_REMAP_TIM17_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17 DMA request remap
|
||||
0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1
|
||||
1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2) */
|
||||
#if defined (STM32F070xB)
|
||||
#define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F070xB devices only.
|
||||
0: Disabled, need to remap before use
|
||||
1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */
|
||||
|
||||
#endif
|
||||
|
||||
#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx)
|
||||
#define DMA_REMAP_TIM16_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP2) /*!< TIM16 alternate DMA request remapping bit. Available on STM32F07x devices only
|
||||
0: No alternate remap (TIM16 DMA requestsmapped according to TIM16_DMA_RMP bit)
|
||||
1: Alternate remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6) */
|
||||
#define DMA_REMAP_TIM17_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP2) /*!< TIM17 alternate DMA request remapping bit. Available on STM32F07x devices only
|
||||
0: No alternate remap (TIM17 DMA requestsmapped according to TIM17_DMA_RMP bit)
|
||||
1: Alternate remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7) */
|
||||
#define DMA_REMAP_SPI2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_SPI2_DMA_RMP) /*!< SPI2 DMA request remapping bit. Available on STM32F07x devices only.
|
||||
0: No remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively)
|
||||
1: Remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */
|
||||
#define DMA_REMAP_USART2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_USART2_DMA_RMP) /*!< USART2 DMA request remapping bit. Available on STM32F07x devices only.
|
||||
0: No remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively)
|
||||
1: 1: Remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */
|
||||
#define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F07x devices only.
|
||||
0: No remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively)
|
||||
1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */
|
||||
#define DMA_REMAP_I2C1_DMA_CH76 ((uint32_t)SYSCFG_CFGR1_I2C1_DMA_RMP) /*!< I2C1 DMA request remapping bit. Available on STM32F07x devices only.
|
||||
0: No remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively)
|
||||
1: Remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively) */
|
||||
#define DMA_REMAP_TIM1_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM1_DMA_RMP) /*!< TIM1 DMA request remapping bit. Available on STM32F07x devices only.
|
||||
0: No remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively)
|
||||
1: Remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 */
|
||||
#define DMA_REMAP_TIM2_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM2_DMA_RMP) /*!< TIM2 DMA request remapping bit. Available on STM32F07x devices only.
|
||||
0: No remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively)
|
||||
1: Remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 */
|
||||
#define DMA_REMAP_TIM3_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM3_DMA_RMP) /*!< TIM3 DMA request remapping bit. Available on STM32F07x devices only.
|
||||
0: No remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4)
|
||||
1: Remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6) */
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* SYSCFG_CFGR1_DMA_RMP */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup DMA_Exported_Macros DMA Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset DMA handle state
|
||||
* @param __HANDLE__ DMA handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Enable the specified DMA Channel.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
|
||||
|
||||
/**
|
||||
* @brief Disable the specified DMA Channel.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
|
||||
|
||||
|
||||
/* Interrupt & Flag management */
|
||||
|
||||
/**
|
||||
* @brief Enables the specified DMA Channel interrupts.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask
|
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask
|
||||
* @arg DMA_IT_TE: Transfer error interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disables the specified DMA Channel interrupts.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask
|
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask
|
||||
* @arg DMA_IT_TE: Transfer error interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DMA Channel interrupt is enabled or disabled.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __INTERRUPT__ specifies the DMA interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask
|
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask
|
||||
* @arg DMA_IT_TE: Transfer error interrupt mask
|
||||
* @retval The state of DMA_IT (SET or RESET).
|
||||
*/
|
||||
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
|
||||
|
||||
/**
|
||||
* @brief Returns the number of remaining data units in the current DMAy Channelx transfer.
|
||||
* @param __HANDLE__ DMA handle
|
||||
*
|
||||
* @retval The number of remaining data units in the current DMA Channel transfer.
|
||||
*/
|
||||
#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
|
||||
|
||||
#if defined(SYSCFG_CFGR1_DMA_RMP)
|
||||
/** @brief DMA remapping enable/disable macros
|
||||
* @param __DMA_REMAP__ This parameter can be a value of @ref HAL_DMA_remapping
|
||||
*/
|
||||
#define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
|
||||
SYSCFG->CFGR1 |= (__DMA_REMAP__); \
|
||||
}while(0)
|
||||
#define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
|
||||
SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \
|
||||
}while(0)
|
||||
#endif /* SYSCFG_CFGR1_DMA_RMP */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include DMA HAL Extension module */
|
||||
#include "stm32f0xx_hal_dma_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup DMA_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* Input and Output operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
|
||||
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
|
||||
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
|
||||
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
|
||||
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
|
||||
((DIRECTION) == DMA_MEMORY_TO_MEMORY))
|
||||
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
|
||||
((STATE) == DMA_PINC_DISABLE))
|
||||
|
||||
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
|
||||
((STATE) == DMA_MINC_DISABLE))
|
||||
|
||||
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
|
||||
((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
|
||||
((SIZE) == DMA_PDATAALIGN_WORD))
|
||||
|
||||
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
|
||||
((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
|
||||
((SIZE) == DMA_MDATAALIGN_WORD ))
|
||||
|
||||
#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
|
||||
((MODE) == DMA_CIRCULAR))
|
||||
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
|
||||
((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
|
||||
((PRIORITY) == DMA_PRIORITY_HIGH) || \
|
||||
((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
|
||||
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
|
||||
|
||||
#if defined(SYSCFG_CFGR1_DMA_RMP)
|
||||
|
||||
#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx)
|
||||
#define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \
|
||||
((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \
|
||||
((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \
|
||||
((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \
|
||||
((RMP) == DMA_REMAP_TIM17_DMA_CH2) || \
|
||||
((RMP) == DMA_REMAP_TIM16_DMA_CH6) || \
|
||||
((RMP) == DMA_REMAP_TIM17_DMA_CH7) || \
|
||||
((RMP) == DMA_REMAP_SPI2_DMA_CH67) || \
|
||||
((RMP) == DMA_REMAP_USART2_DMA_CH67) || \
|
||||
((RMP) == DMA_REMAP_USART3_DMA_CH32) || \
|
||||
((RMP) == DMA_REMAP_I2C1_DMA_CH76) || \
|
||||
((RMP) == DMA_REMAP_TIM1_DMA_CH6) || \
|
||||
((RMP) == DMA_REMAP_TIM2_DMA_CH7) || \
|
||||
((RMP) == DMA_REMAP_TIM3_DMA_CH6))
|
||||
#elif defined (STM32F070xB)
|
||||
#define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_USART3_DMA_CH32) || \
|
||||
((RMP) == DMA_REMAP_ADC_DMA_CH2) || \
|
||||
((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \
|
||||
((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \
|
||||
((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \
|
||||
((RMP) == DMA_REMAP_TIM17_DMA_CH2))
|
||||
#else
|
||||
#define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \
|
||||
((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \
|
||||
((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \
|
||||
((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \
|
||||
((RMP) == DMA_REMAP_TIM17_DMA_CH2))
|
||||
#endif
|
||||
|
||||
#endif /* SYSCFG_CFGR1_DMA_RMP */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0xx_HAL_DMA_H */
|
||||
|
||||
|
||||
809
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h
Normal file
809
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h
Normal file
@@ -0,0 +1,809 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_dma_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DMA HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0xx_HAL_DMA_EX_H
|
||||
#define __STM32F0xx_HAL_DMA_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx DMAEx
|
||||
* @brief DMA HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
|
||||
/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
#define DMA1_CHANNEL1_RMP 0x00000000 /*!< Internal define for remapping on STM32F09x/30xC */
|
||||
#define DMA1_CHANNEL2_RMP 0x10000000 /*!< Internal define for remapping on STM32F09x/30xC */
|
||||
#define DMA1_CHANNEL3_RMP 0x20000000 /*!< Internal define for remapping on STM32F09x/30xC */
|
||||
#define DMA1_CHANNEL4_RMP 0x30000000 /*!< Internal define for remapping on STM32F09x/30xC */
|
||||
#define DMA1_CHANNEL5_RMP 0x40000000 /*!< Internal define for remapping on STM32F09x/30xC */
|
||||
#if !defined(STM32F030xC)
|
||||
#define DMA1_CHANNEL6_RMP 0x50000000 /*!< Internal define for remapping on STM32F09x/30xC */
|
||||
#define DMA1_CHANNEL7_RMP 0x60000000 /*!< Internal define for remapping on STM32F09x/30xC */
|
||||
#define DMA2_CHANNEL1_RMP 0x00000000 /*!< Internal define for remapping on STM32F09x/30xC */
|
||||
#define DMA2_CHANNEL2_RMP 0x10000000 /*!< Internal define for remapping on STM32F09x/30xC */
|
||||
#define DMA2_CHANNEL3_RMP 0x20000000 /*!< Internal define for remapping on STM32F09x/30xC */
|
||||
#define DMA2_CHANNEL4_RMP 0x30000000 /*!< Internal define for remapping on STM32F09x/30xC */
|
||||
#define DMA2_CHANNEL5_RMP 0x40000000 /*!< Internal define for remapping on STM32F09x/30xC */
|
||||
#endif /* !defined(STM32F030xC) */
|
||||
|
||||
/****************** DMA1 remap bit field definition********************/
|
||||
/* DMA1 - Channel 1 */
|
||||
#define HAL_DMA1_CH1_DEFAULT (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
|
||||
#define HAL_DMA1_CH1_ADC (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_ADC) /*!< Remap ADC on DMA1 Channel 1*/
|
||||
#define HAL_DMA1_CH1_TIM17_CH1 (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 1 */
|
||||
#define HAL_DMA1_CH1_TIM17_UP (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 1 */
|
||||
#define HAL_DMA1_CH1_USART1_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 1 */
|
||||
#define HAL_DMA1_CH1_USART2_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 1 */
|
||||
#define HAL_DMA1_CH1_USART3_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 1 */
|
||||
#define HAL_DMA1_CH1_USART4_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 1 */
|
||||
#define HAL_DMA1_CH1_USART5_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 1 */
|
||||
#define HAL_DMA1_CH1_USART6_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 1 */
|
||||
#if !defined(STM32F030xC)
|
||||
#define HAL_DMA1_CH1_USART7_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 1 */
|
||||
#define HAL_DMA1_CH1_USART8_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 1 */
|
||||
#endif /* !defined(STM32F030xC) */
|
||||
|
||||
/* DMA1 - Channel 2 */
|
||||
#define HAL_DMA1_CH2_DEFAULT (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
|
||||
#define HAL_DMA1_CH2_ADC (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_ADC) /*!< Remap ADC on DMA1 channel 2 */
|
||||
#define HAL_DMA1_CH2_I2C1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 2 */
|
||||
#define HAL_DMA1_CH2_SPI1_RX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_SPI1_RX) /*!< Remap SPI1 Rx on DMA1 channel 2 */
|
||||
#define HAL_DMA1_CH2_TIM1_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 2 */
|
||||
#define HAL_DMA1_CH2_TIM17_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 2 */
|
||||
#define HAL_DMA1_CH2_TIM17_UP (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 2 */
|
||||
#define HAL_DMA1_CH2_USART1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 2 */
|
||||
#define HAL_DMA1_CH2_USART2_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 2 */
|
||||
#define HAL_DMA1_CH2_USART3_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 2 */
|
||||
#define HAL_DMA1_CH2_USART4_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 2 */
|
||||
#define HAL_DMA1_CH2_USART5_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 2 */
|
||||
#define HAL_DMA1_CH2_USART6_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 2 */
|
||||
#if !defined(STM32F030xC)
|
||||
#define HAL_DMA1_CH2_USART7_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 2 */
|
||||
#define HAL_DMA1_CH2_USART8_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 2 */
|
||||
#endif /* !defined(STM32F030xC) */
|
||||
|
||||
/* DMA1 - Channel 3 */
|
||||
#define HAL_DMA1_CH3_DEFAULT (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
|
||||
#define HAL_DMA1_CH3_TIM6_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA1 channel 3 */
|
||||
#if !defined(STM32F030xC)
|
||||
#define HAL_DMA1_CH3_DAC_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_DAC_CH1) /*!< Remap DAC Channel 1on DMA1 channel 3 */
|
||||
#endif /* !defined(STM32F030xC) */
|
||||
#define HAL_DMA1_CH3_I2C1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 3 */
|
||||
#define HAL_DMA1_CH3_SPI1_TX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_SPI1_TX) /*!< Remap SPI1 Tx on DMA1 channel 3 */
|
||||
#define HAL_DMA1_CH3_TIM1_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 3 */
|
||||
#if !defined(STM32F030xC)
|
||||
#define HAL_DMA1_CH3_TIM2_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 3 */
|
||||
#endif /* !defined(STM32F030xC) */
|
||||
#define HAL_DMA1_CH3_TIM16_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 3 */
|
||||
#define HAL_DMA1_CH3_TIM16_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 3 */
|
||||
#define HAL_DMA1_CH3_USART1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 3 */
|
||||
#define HAL_DMA1_CH3_USART2_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 3 */
|
||||
#define HAL_DMA1_CH3_USART3_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 3 */
|
||||
#define HAL_DMA1_CH3_USART4_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 3 */
|
||||
#define HAL_DMA1_CH3_USART5_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 3 */
|
||||
#define HAL_DMA1_CH3_USART6_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 3 */
|
||||
#if !defined(STM32F030xC)
|
||||
#define HAL_DMA1_CH3_USART7_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 3 */
|
||||
#define HAL_DMA1_CH3_USART8_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 3 */
|
||||
#endif /* !defined(STM32F030xC) */
|
||||
|
||||
/* DMA1 - Channel 4 */
|
||||
#define HAL_DMA1_CH4_DEFAULT (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
|
||||
#define HAL_DMA1_CH4_TIM7_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA1 channel 4 */
|
||||
#if !defined(STM32F030xC)
|
||||
#define HAL_DMA1_CH4_DAC_CH2 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_DAC_CH2) /*!< Remap DAC Channel 2 on DMA1 channel 4 */
|
||||
#endif /* !defined(STM32F030xC) */
|
||||
#define HAL_DMA1_CH4_I2C2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_I2C2_TX) /*!< Remap I2C2 Tx on DMA1 channel 4 */
|
||||
#define HAL_DMA1_CH4_SPI2_RX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 4 */
|
||||
#if !defined(STM32F030xC)
|
||||
#define HAL_DMA1_CH4_TIM2_CH4 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 4 */
|
||||
#endif /* !defined(STM32F030xC) */
|
||||
#define HAL_DMA1_CH4_TIM3_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 4 */
|
||||
#define HAL_DMA1_CH4_TIM3_TRIG (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 4 */
|
||||
#define HAL_DMA1_CH4_TIM16_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 4 */
|
||||
#define HAL_DMA1_CH4_TIM16_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 4 */
|
||||
#define HAL_DMA1_CH4_USART1_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 4 */
|
||||
#define HAL_DMA1_CH4_USART2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 4 */
|
||||
#define HAL_DMA1_CH4_USART3_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 4 */
|
||||
#define HAL_DMA1_CH4_USART4_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 4 */
|
||||
#define HAL_DMA1_CH4_USART5_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 4 */
|
||||
#define HAL_DMA1_CH4_USART6_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 4 */
|
||||
#if !defined(STM32F030xC)
|
||||
#define HAL_DMA1_CH4_USART7_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 4 */
|
||||
#define HAL_DMA1_CH4_USART8_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 4 */
|
||||
#endif /* !defined(STM32F030xC) */
|
||||
|
||||
/* DMA1 - Channel 5 */
|
||||
#define HAL_DMA1_CH5_DEFAULT (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
|
||||
#define HAL_DMA1_CH5_I2C2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_I2C2_RX) /*!< Remap I2C2 Rx on DMA1 channel 5 */
|
||||
#define HAL_DMA1_CH5_SPI2_TX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_SPI2_TX) /*!< Remap SPI1 Tx on DMA1 channel 5 */
|
||||
#define HAL_DMA1_CH5_TIM1_CH3 (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 5 */
|
||||
#define HAL_DMA1_CH5_USART1_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 5 */
|
||||
#define HAL_DMA1_CH5_USART2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 5 */
|
||||
#define HAL_DMA1_CH5_USART3_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 5 */
|
||||
#define HAL_DMA1_CH5_USART4_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 5 */
|
||||
#define HAL_DMA1_CH5_USART5_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 5 */
|
||||
#define HAL_DMA1_CH5_USART6_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 5 */
|
||||
#if !defined(STM32F030xC)
|
||||
#define HAL_DMA1_CH5_USART7_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 5 */
|
||||
#define HAL_DMA1_CH5_USART8_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 5 */
|
||||
#endif /* !defined(STM32F030xC) */
|
||||
|
||||
#if !defined(STM32F030xC)
|
||||
/* DMA1 - Channel 6 */
|
||||
#define HAL_DMA1_CH6_DEFAULT (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
|
||||
#define HAL_DMA1_CH6_I2C1_TX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 6 */
|
||||
#define HAL_DMA1_CH6_SPI2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 6 */
|
||||
#define HAL_DMA1_CH6_TIM1_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 6 */
|
||||
#define HAL_DMA1_CH6_TIM1_CH2 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 6 */
|
||||
#define HAL_DMA1_CH6_TIM1_CH3 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 6 */
|
||||
#define HAL_DMA1_CH6_TIM3_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 6 */
|
||||
#define HAL_DMA1_CH6_TIM3_TRIG (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 6 */
|
||||
#define HAL_DMA1_CH6_TIM16_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 6 */
|
||||
#define HAL_DMA1_CH6_TIM16_UP (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 6 */
|
||||
#define HAL_DMA1_CH6_USART1_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 6 */
|
||||
#define HAL_DMA1_CH6_USART2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 6 */
|
||||
#define HAL_DMA1_CH6_USART3_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 6 */
|
||||
#define HAL_DMA1_CH6_USART4_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 6 */
|
||||
#define HAL_DMA1_CH6_USART5_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 6 */
|
||||
#define HAL_DMA1_CH6_USART6_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 6 */
|
||||
#define HAL_DMA1_CH6_USART7_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 6 */
|
||||
#define HAL_DMA1_CH6_USART8_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 6 */
|
||||
/* DMA1 - Channel 7 */
|
||||
#define HAL_DMA1_CH7_DEFAULT (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
|
||||
#define HAL_DMA1_CH7_I2C1_RX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 7 */
|
||||
#define HAL_DMA1_CH7_SPI2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_SPI2_TX) /*!< Remap SPI2 Tx on DMA1 channel 7 */
|
||||
#define HAL_DMA1_CH7_TIM2_CH2 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 7 */
|
||||
#define HAL_DMA1_CH7_TIM2_CH4 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 7 */
|
||||
#define HAL_DMA1_CH7_TIM17_CH1 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 7 */
|
||||
#define HAL_DMA1_CH7_TIM17_UP (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 7 */
|
||||
#define HAL_DMA1_CH7_USART1_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 7 */
|
||||
#define HAL_DMA1_CH7_USART2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 7 */
|
||||
#define HAL_DMA1_CH7_USART3_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 7 */
|
||||
#define HAL_DMA1_CH7_USART4_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 7 */
|
||||
#define HAL_DMA1_CH7_USART5_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 7 */
|
||||
#define HAL_DMA1_CH7_USART6_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 7 */
|
||||
#define HAL_DMA1_CH7_USART7_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 7 */
|
||||
#define HAL_DMA1_CH7_USART8_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 7 */
|
||||
|
||||
/****************** DMA2 remap bit field definition********************/
|
||||
/* DMA2 - Channel 1 */
|
||||
#define HAL_DMA2_CH1_DEFAULT (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
|
||||
#define HAL_DMA2_CH1_I2C2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_I2C2_TX) /*!< Remap I2C2 TX on DMA2 channel 1 */
|
||||
#define HAL_DMA2_CH1_USART1_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 1 */
|
||||
#define HAL_DMA2_CH1_USART2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 1 */
|
||||
#define HAL_DMA2_CH1_USART3_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 1 */
|
||||
#define HAL_DMA2_CH1_USART4_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 1 */
|
||||
#define HAL_DMA2_CH1_USART5_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 1 */
|
||||
#define HAL_DMA2_CH1_USART6_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 1 */
|
||||
#define HAL_DMA2_CH1_USART7_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 1 */
|
||||
#define HAL_DMA2_CH1_USART8_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 1 */
|
||||
/* DMA2 - Channel 2 */
|
||||
#define HAL_DMA2_CH2_DEFAULT (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
|
||||
#define HAL_DMA2_CH2_I2C2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_I2C2_RX) /*!< Remap I2C2 Rx on DMA2 channel 2 */
|
||||
#define HAL_DMA2_CH2_USART1_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 2 */
|
||||
#define HAL_DMA2_CH2_USART2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 2 */
|
||||
#define HAL_DMA2_CH2_USART3_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 2 */
|
||||
#define HAL_DMA2_CH2_USART4_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 2 */
|
||||
#define HAL_DMA2_CH2_USART5_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 2 */
|
||||
#define HAL_DMA2_CH2_USART6_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 2 */
|
||||
#define HAL_DMA2_CH2_USART7_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 2 */
|
||||
#define HAL_DMA2_CH2_USART8_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 2 */
|
||||
/* DMA2 - Channel 3 */
|
||||
#define HAL_DMA2_CH3_DEFAULT (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
|
||||
#define HAL_DMA2_CH3_TIM6_UP (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA2 channel 3 */
|
||||
#define HAL_DMA2_CH3_DAC_CH1 (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_DAC_CH1) /*!< Remap DAC channel 1 on DMA2 channel 3 */
|
||||
#define HAL_DMA2_CH3_SPI1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_SPI1_RX) /*!< Remap SPI1 Rx on DMA2 channel 3 */
|
||||
#define HAL_DMA2_CH3_USART1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 3 */
|
||||
#define HAL_DMA2_CH3_USART2_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 3 */
|
||||
#define HAL_DMA2_CH3_USART3_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 3 */
|
||||
#define HAL_DMA2_CH3_USART4_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 3 */
|
||||
#define HAL_DMA2_CH3_USART5_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 3 */
|
||||
#define HAL_DMA2_CH3_USART6_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 3 */
|
||||
#define HAL_DMA2_CH3_USART7_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 3 */
|
||||
#define HAL_DMA2_CH3_USART8_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 3 */
|
||||
/* DMA2 - Channel 4 */
|
||||
#define HAL_DMA2_CH4_DEFAULT (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
|
||||
#define HAL_DMA2_CH4_TIM7_UP (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA2 channel 4 */
|
||||
#define HAL_DMA2_CH4_DAC_CH2 (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_DAC_CH2) /*!< Remap DAC channel 2 on DMA2 channel 4 */
|
||||
#define HAL_DMA2_CH4_SPI1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_SPI1_TX) /*!< Remap SPI1 Tx on DMA2 channel 4 */
|
||||
#define HAL_DMA2_CH4_USART1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 4 */
|
||||
#define HAL_DMA2_CH4_USART2_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 4 */
|
||||
#define HAL_DMA2_CH4_USART3_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 4 */
|
||||
#define HAL_DMA2_CH4_USART4_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 4 */
|
||||
#define HAL_DMA2_CH4_USART5_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 4 */
|
||||
#define HAL_DMA2_CH4_USART6_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 4 */
|
||||
#define HAL_DMA2_CH4_USART7_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 4 */
|
||||
#define HAL_DMA2_CH4_USART8_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 4 */
|
||||
/* DMA2 - Channel 5 */
|
||||
#define HAL_DMA2_CH5_DEFAULT (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
|
||||
#define HAL_DMA2_CH5_ADC (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_ADC) /*!< Remap ADC on DMA2 channel 5 */
|
||||
#define HAL_DMA2_CH5_USART1_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 5 */
|
||||
#define HAL_DMA2_CH5_USART2_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 5 */
|
||||
#define HAL_DMA2_CH5_USART3_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 5 */
|
||||
#define HAL_DMA2_CH5_USART4_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 5 */
|
||||
#define HAL_DMA2_CH5_USART5_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 5 */
|
||||
#define HAL_DMA2_CH5_USART6_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 5 */
|
||||
#define HAL_DMA2_CH5_USART7_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 5 */
|
||||
#define HAL_DMA2_CH5_USART8_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 5 */
|
||||
#endif /* !defined(STM32F030xC) */
|
||||
|
||||
#if defined(STM32F091xC) || defined(STM32F098xx)
|
||||
#define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_ADC) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_TIM17_UP) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_USART7_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_USART8_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_DEFAULT) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_ADC) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_SPI1_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_TIM17_UP) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_USART7_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_USART8_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_DEFAULT) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_TIM6_UP) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_DAC_CH1) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_I2C1_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_SPI1_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_TIM2_CH2) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_TIM16_UP) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_USART7_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_USART8_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_DEFAULT) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_TIM7_UP) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_DAC_CH2) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_I2C2_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_SPI2_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_TIM2_CH4) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_TIM16_UP) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_USART7_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_USART8_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_DEFAULT) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_I2C2_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_SPI2_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_USART6_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_USART7_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_USART8_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH6_DEFAULT) ||\
|
||||
((REQUEST) == HAL_DMA1_CH6_I2C1_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH6_SPI2_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH6_TIM1_CH1) ||\
|
||||
((REQUEST) == HAL_DMA1_CH6_TIM1_CH2) ||\
|
||||
((REQUEST) == HAL_DMA1_CH6_TIM1_CH3) ||\
|
||||
((REQUEST) == HAL_DMA1_CH6_TIM3_CH1) ||\
|
||||
((REQUEST) == HAL_DMA1_CH6_TIM3_TRIG) ||\
|
||||
((REQUEST) == HAL_DMA1_CH6_TIM16_CH1) ||\
|
||||
((REQUEST) == HAL_DMA1_CH6_TIM16_UP) ||\
|
||||
((REQUEST) == HAL_DMA1_CH6_USART1_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH6_USART2_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH6_USART3_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH6_USART4_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH6_USART5_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH6_USART6_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH6_USART7_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH6_USART8_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH7_DEFAULT) ||\
|
||||
((REQUEST) == HAL_DMA1_CH7_I2C1_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH7_SPI2_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH7_TIM2_CH2) ||\
|
||||
((REQUEST) == HAL_DMA1_CH7_TIM2_CH4) ||\
|
||||
((REQUEST) == HAL_DMA1_CH7_TIM17_CH1) ||\
|
||||
((REQUEST) == HAL_DMA1_CH7_TIM17_UP) ||\
|
||||
((REQUEST) == HAL_DMA1_CH7_USART1_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH7_USART2_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH7_USART3_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH7_USART4_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH7_USART5_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH7_USART6_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH7_USART7_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH7_USART8_TX))
|
||||
|
||||
#define IS_HAL_DMA2_REMAP(REQUEST) (((REQUEST) == HAL_DMA2_CH1_DEFAULT) ||\
|
||||
((REQUEST) == HAL_DMA2_CH1_I2C2_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH1_USART1_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH1_USART2_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH1_USART3_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH1_USART4_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH1_USART5_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH1_USART6_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH1_USART7_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH1_USART8_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH2_DEFAULT) ||\
|
||||
((REQUEST) == HAL_DMA2_CH2_I2C2_RX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH2_USART1_RX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH2_USART2_RX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH2_USART3_RX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH2_USART4_RX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH2_USART5_RX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH2_USART6_RX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH2_USART7_RX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH2_USART8_RX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH3_DEFAULT) ||\
|
||||
((REQUEST) == HAL_DMA2_CH3_TIM6_UP) ||\
|
||||
((REQUEST) == HAL_DMA2_CH3_DAC_CH1) ||\
|
||||
((REQUEST) == HAL_DMA2_CH3_SPI1_RX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH3_USART1_RX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH3_USART2_RX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH3_USART3_RX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH3_USART4_RX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH3_USART5_RX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH3_USART6_RX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH3_USART7_RX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH3_USART8_RX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH4_DEFAULT) ||\
|
||||
((REQUEST) == HAL_DMA2_CH4_TIM7_UP) ||\
|
||||
((REQUEST) == HAL_DMA2_CH4_DAC_CH2) ||\
|
||||
((REQUEST) == HAL_DMA2_CH4_SPI1_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH4_USART1_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH4_USART2_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH4_USART3_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH4_USART4_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH4_USART5_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH4_USART6_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH4_USART7_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH4_USART8_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH5_DEFAULT) ||\
|
||||
((REQUEST) == HAL_DMA2_CH5_ADC) ||\
|
||||
((REQUEST) == HAL_DMA2_CH5_USART1_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH5_USART2_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH5_USART3_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH5_USART4_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH5_USART5_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH5_USART6_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH5_USART7_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH5_USART8_TX ))
|
||||
#endif /* STM32F091xC || STM32F098xx */
|
||||
|
||||
#if defined(STM32F030xC)
|
||||
#define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_ADC) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_TIM17_UP) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_DEFAULT) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_ADC) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_SPI1_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_TIM17_UP) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_DEFAULT) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_TIM6_UP) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_I2C1_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_SPI1_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_TIM16_UP) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_DEFAULT) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_TIM7_UP) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_I2C2_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_SPI2_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_TIM16_UP) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_DEFAULT) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_I2C2_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_SPI2_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_USART6_RX))
|
||||
#endif /* STM32F030xC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMAEx_Exported_Macros DMAEx Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/* Interrupt & Flag management */
|
||||
|
||||
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
|
||||
/**
|
||||
* @brief Returns the current DMA Channel transfer complete flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified transfer complete flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
|
||||
DMA_FLAG_TC7)
|
||||
|
||||
/**
|
||||
* @brief Returns the current DMA Channel half transfer complete flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified half transfer complete flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
|
||||
DMA_FLAG_HT7)
|
||||
|
||||
/**
|
||||
* @brief Returns the current DMA Channel transfer error flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified transfer error flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
|
||||
DMA_FLAG_TE7)
|
||||
|
||||
/**
|
||||
* @brief Return the current DMA Channel Global interrupt flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified transfer error flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
|
||||
DMA_FLAG_GL7)
|
||||
|
||||
/**
|
||||
* @brief Get the DMA Channel pending flags.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __FLAG__ Get the specified flag.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TCx: Transfer complete flag
|
||||
* @arg DMA_FLAG_HTx: Half transfer complete flag
|
||||
* @arg DMA_FLAG_TEx: Transfer error flag
|
||||
* Where x can be 1_7 to select the DMA Channel flag.
|
||||
* @retval The state of FLAG (SET or RESET).
|
||||
*/
|
||||
|
||||
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clears the DMA Channel pending flags.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TCx: Transfer complete flag
|
||||
* @arg DMA_FLAG_HTx: Half transfer complete flag
|
||||
* @arg DMA_FLAG_TEx: Transfer error flag
|
||||
* Where x can be 1_7 to select the DMA Channel flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
|
||||
|
||||
#elif defined(STM32F091xC) || defined(STM32F098xx)
|
||||
/**
|
||||
* @brief Returns the current DMA Channel transfer complete flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified transfer complete flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
|
||||
DMA_FLAG_TC5)
|
||||
|
||||
/**
|
||||
* @brief Returns the current DMA Channel half transfer complete flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified half transfer complete flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
|
||||
DMA_FLAG_HT5)
|
||||
|
||||
/**
|
||||
* @brief Returns the current DMA Channel transfer error flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified transfer error flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
|
||||
DMA_FLAG_TE5)
|
||||
|
||||
/**
|
||||
* @brief Return the current DMA Channel Global interrupt flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified transfer error flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\
|
||||
DMA_FLAG_GL5)
|
||||
|
||||
/**
|
||||
* @brief Get the DMA Channel pending flags.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __FLAG__ Get the specified flag.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TCx: Transfer complete flag
|
||||
* @arg DMA_FLAG_HTx: Half transfer complete flag
|
||||
* @arg DMA_FLAG_TEx: Transfer error flag
|
||||
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
|
||||
* @retval The state of FLAG (SET or RESET).
|
||||
*/
|
||||
|
||||
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
|
||||
(DMA1->ISR & (__FLAG__)))
|
||||
|
||||
/**
|
||||
* @brief Clears the DMA Channel pending flags.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TCx: Transfer complete flag
|
||||
* @arg DMA_FLAG_HTx: Half transfer complete flag
|
||||
* @arg DMA_FLAG_TEx: Transfer error flag
|
||||
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
|
||||
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
|
||||
(DMA1->IFCR = (__FLAG__)))
|
||||
|
||||
#else /* STM32F030x8_STM32F030xC_STM32F031x6_STM32F038xx_STM32F051x8_STM32F058xx_STM32F070x6_STM32F070xB Product devices */
|
||||
/**
|
||||
* @brief Returns the current DMA Channel transfer complete flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified transfer complete flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
|
||||
DMA_FLAG_TC5)
|
||||
|
||||
/**
|
||||
* @brief Returns the current DMA Channel half transfer complete flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified half transfer complete flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
|
||||
DMA_FLAG_HT5)
|
||||
|
||||
/**
|
||||
* @brief Returns the current DMA Channel transfer error flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified transfer error flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
|
||||
DMA_FLAG_TE5)
|
||||
|
||||
/**
|
||||
* @brief Return the current DMA Channel Global interrupt flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified transfer error flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
|
||||
DMA_FLAG_GL5)
|
||||
|
||||
/**
|
||||
* @brief Get the DMA Channel pending flags.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __FLAG__ Get the specified flag.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TCx: Transfer complete flag
|
||||
* @arg DMA_FLAG_HTx: Half transfer complete flag
|
||||
* @arg DMA_FLAG_TEx: Transfer error flag
|
||||
* Where x can be 1_5 to select the DMA Channel flag.
|
||||
* @retval The state of FLAG (SET or RESET).
|
||||
*/
|
||||
|
||||
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clears the DMA Channel pending flags.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TCx: Transfer complete flag
|
||||
* @arg DMA_FLAG_HTx: Half transfer complete flag
|
||||
* @arg DMA_FLAG_TEx: Transfer error flag
|
||||
* Where x can be 1_5 to select the DMA Channel flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
|
||||
#define __HAL_DMA1_REMAP(__REQUEST__) \
|
||||
do { assert_param(IS_HAL_DMA1_REMAP(__REQUEST__)); \
|
||||
DMA1->CSELR &= ~(0x0FU << (uint32_t)(((__REQUEST__) >> 28U) * 4U)); \
|
||||
DMA1->CSELR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFFU); \
|
||||
}while(0)
|
||||
|
||||
#if defined(STM32F091xC) || defined(STM32F098xx)
|
||||
#define __HAL_DMA2_REMAP(__REQUEST__) \
|
||||
do { assert_param(IS_HAL_DMA2_REMAP(__REQUEST__)); \
|
||||
DMA2->CSELR &= ~(0x0FU << (uint32_t)(((__REQUEST__) >> 28U) * 4U)); \
|
||||
DMA2->CSELR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFFU); \
|
||||
}while(0)
|
||||
#endif /* STM32F091xC || STM32F098xx */
|
||||
|
||||
#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0xx_HAL_DMA_EX_H */
|
||||
|
||||
373
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h
Normal file
373
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h
Normal file
@@ -0,0 +1,373 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_exti.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of EXTI HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F0xx_HAL_EXTI_H
|
||||
#define STM32F0xx_HAL_EXTI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI EXTI
|
||||
* @brief EXTI HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Types EXTI Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL EXTI common Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_EXTI_COMMON_CB_ID = 0x00U
|
||||
} EXTI_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief EXTI Handle structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Line; /*!< Exti line number */
|
||||
void (* PendingCallback)(void); /*!< Exti pending callback */
|
||||
} EXTI_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief EXTI Configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Line; /*!< The Exti line to be configured. This parameter
|
||||
can be a value of @ref EXTI_Line */
|
||||
uint32_t Mode; /*!< The Exit Mode to be configured for a core.
|
||||
This parameter can be a combination of @ref EXTI_Mode */
|
||||
uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
|
||||
can be a value of @ref EXTI_Trigger */
|
||||
uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
|
||||
This parameter is only possible for line 0 to 15. It
|
||||
can be a value of @ref EXTI_GPIOSel */
|
||||
} EXTI_ConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Line EXTI Line
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */
|
||||
#define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */
|
||||
#define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */
|
||||
#define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */
|
||||
#define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */
|
||||
#define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */
|
||||
#define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */
|
||||
#define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */
|
||||
#define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */
|
||||
#define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */
|
||||
#define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */
|
||||
#define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */
|
||||
#define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */
|
||||
#define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */
|
||||
#define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */
|
||||
#define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */
|
||||
|
||||
#if defined (EXTI_IMR_MR16)
|
||||
#define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */
|
||||
#else
|
||||
#define EXTI_LINE_16 (EXTI_RESERVED | 0x10u)
|
||||
#endif /* EXTI_IMR_MR16 */
|
||||
|
||||
#define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */
|
||||
|
||||
#if defined (EXTI_IMR_MR18)
|
||||
#define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */
|
||||
#else
|
||||
#define EXTI_LINE_18 (EXTI_RESERVED | 0x12u)
|
||||
#endif /* EXTI_IMR_MR18 */
|
||||
|
||||
#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
|
||||
|
||||
#if defined (EXTI_IMR_MR20)
|
||||
#define EXTI_LINE_20 (EXTI_CONFIG | 0x14u) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */
|
||||
#else
|
||||
#define EXTI_LINE_20 (EXTI_RESERVED | 0x14u)
|
||||
#endif /* EXTI_IMR_MR20 */
|
||||
|
||||
#if defined (EXTI_IMR_MR21)
|
||||
#define EXTI_LINE_21 (EXTI_CONFIG | 0x15u) /*!< External interrupt line 21 Connected to the Comparator 1 output */
|
||||
#else
|
||||
#define EXTI_LINE_21 (EXTI_RESERVED | 0x15u)
|
||||
#endif /* EXTI_IMR_MR21 */
|
||||
|
||||
#if defined (EXTI_IMR_MR22)
|
||||
#define EXTI_LINE_22 (EXTI_CONFIG | 0x16u) /*!< External interrupt line 22 Connected to the Comparator 2 output */
|
||||
#else
|
||||
#define EXTI_LINE_22 (EXTI_RESERVED | 0x16u)
|
||||
#endif /* EXTI_IMR_MR22 */
|
||||
|
||||
#if defined (EXTI_IMR_MR23)
|
||||
#define EXTI_LINE_23 (EXTI_DIRECT | 0x17u) /*!< External interrupt line 23 Connected to the internal I2C1 wakeup event */
|
||||
#else
|
||||
#define EXTI_LINE_23 (EXTI_RESERVED | 0x17u)
|
||||
#endif /* EXTI_IMR_MR23 */
|
||||
|
||||
#define EXTI_LINE_24 (EXTI_RESERVED | 0x18u)
|
||||
|
||||
#if defined (EXTI_IMR_MR25)
|
||||
#define EXTI_LINE_25 (EXTI_CONFIG | 0x19u) /*!< External interrupt line 25 Connected to the internal USART1 wakeup event */
|
||||
#else
|
||||
#define EXTI_LINE_25 (EXTI_RESERVED | 0x19u)
|
||||
#endif /* EXTI_IMR_MR25 */
|
||||
|
||||
#if defined (EXTI_IMR_MR26)
|
||||
#define EXTI_LINE_26 (EXTI_CONFIG | 0x1Au) /*!< External interrupt line 26 Connected to the internal USART2 wakeup event */
|
||||
#else
|
||||
#define EXTI_LINE_26 (EXTI_RESERVED | 0x1Au)
|
||||
#endif /* EXTI_IMR_MR26 */
|
||||
|
||||
#if defined (EXTI_IMR_MR27)
|
||||
#define EXTI_LINE_27 (EXTI_CONFIG | 0x1Bu) /*!< External interrupt line 27 Connected to the internal CEC wakeup event */
|
||||
#else
|
||||
#define EXTI_LINE_27 (EXTI_RESERVED | 0x1Bu)
|
||||
#endif /* EXTI_IMR_MR27 */
|
||||
|
||||
#if defined (EXTI_IMR_MR28)
|
||||
#define EXTI_LINE_28 (EXTI_CONFIG | 0x1Cu) /*!< External interrupt line 28 Connected to the internal USART3 wakeup event */
|
||||
#else
|
||||
#define EXTI_LINE_28 (EXTI_RESERVED | 0x1Cu)
|
||||
#endif /* EXTI_IMR_MR28 */
|
||||
|
||||
#define EXTI_LINE_29 (EXTI_RESERVED | 0x1Du)
|
||||
#define EXTI_LINE_30 (EXTI_RESERVED | 0x1Eu)
|
||||
|
||||
#if defined (EXTI_IMR_MR31)
|
||||
#define EXTI_LINE_31 (EXTI_CONFIG | 0x1Fu) /*!< External interrupt line 31 Connected to the VDDIO2 supply comparator output */
|
||||
#else
|
||||
#define EXTI_LINE_31 (EXTI_RESERVED | 0x1Fu)
|
||||
#endif /* EXTI_IMR_MR31 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Mode EXTI Mode
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_MODE_NONE 0x00000000u
|
||||
#define EXTI_MODE_INTERRUPT 0x00000001u
|
||||
#define EXTI_MODE_EVENT 0x00000002u
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Trigger EXTI Trigger
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_TRIGGER_NONE 0x00000000u
|
||||
#define EXTI_TRIGGER_RISING 0x00000001u
|
||||
#define EXTI_TRIGGER_FALLING 0x00000002u
|
||||
#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_GPIOSel EXTI GPIOSel
|
||||
* @brief
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_GPIOA 0x00000000u
|
||||
#define EXTI_GPIOB 0x00000001u
|
||||
#define EXTI_GPIOC 0x00000002u
|
||||
#if defined (GPIOD)
|
||||
#define EXTI_GPIOD 0x00000003u
|
||||
#endif /* GPIOD */
|
||||
#if defined (GPIOE)
|
||||
#define EXTI_GPIOE 0x00000004u
|
||||
#endif /* GPIOE */
|
||||
#define EXTI_GPIOF 0x00000005u
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants --------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Private_Constants EXTI Private Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief EXTI Line property definition
|
||||
*/
|
||||
#define EXTI_PROPERTY_SHIFT 24u
|
||||
#define EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT)
|
||||
#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
|
||||
#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
|
||||
#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
|
||||
#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
|
||||
|
||||
/**
|
||||
* @brief EXTI bit usage
|
||||
*/
|
||||
#define EXTI_PIN_MASK 0x0000001Fu
|
||||
|
||||
/**
|
||||
* @brief EXTI Mask for interrupt & event mode
|
||||
*/
|
||||
#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
|
||||
|
||||
/**
|
||||
* @brief EXTI Mask for trigger possibilities
|
||||
*/
|
||||
#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
|
||||
|
||||
/**
|
||||
* @brief EXTI Line number
|
||||
*/
|
||||
#define EXTI_LINE_NB 32uL
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Private_Macros EXTI Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \
|
||||
((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
|
||||
(((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
|
||||
(((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
|
||||
(((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
|
||||
|
||||
#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \
|
||||
(((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))
|
||||
|
||||
#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
|
||||
|
||||
#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)
|
||||
|
||||
#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)
|
||||
|
||||
#if defined (GPIOE)
|
||||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
|
||||
((__PORT__) == EXTI_GPIOB) || \
|
||||
((__PORT__) == EXTI_GPIOC) || \
|
||||
((__PORT__) == EXTI_GPIOD) || \
|
||||
((__PORT__) == EXTI_GPIOE) || \
|
||||
((__PORT__) == EXTI_GPIOF))
|
||||
#elif defined (GPIOD)
|
||||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
|
||||
((__PORT__) == EXTI_GPIOB) || \
|
||||
((__PORT__) == EXTI_GPIOC) || \
|
||||
((__PORT__) == EXTI_GPIOD) || \
|
||||
((__PORT__) == EXTI_GPIOF))
|
||||
#else
|
||||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
|
||||
((__PORT__) == EXTI_GPIOB) || \
|
||||
((__PORT__) == EXTI_GPIOC) || \
|
||||
((__PORT__) == EXTI_GPIOF))
|
||||
#endif /* GPIOE */
|
||||
|
||||
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
|
||||
* @brief EXTI Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
|
||||
* @brief Configuration functions
|
||||
* @{
|
||||
*/
|
||||
/* Configuration functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
|
||||
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
|
||||
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
|
||||
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
|
||||
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
|
||||
* @brief IO operation functions
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
|
||||
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
|
||||
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
|
||||
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F0xx_HAL_EXTI_H */
|
||||
|
||||
350
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h
Normal file
350
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h
Normal file
@@ -0,0 +1,350 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_flash.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of Flash HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0xx_HAL_FLASH_H
|
||||
#define __STM32F0xx_HAL_FLASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_TIMEOUT_VALUE (50000U) /* 50 s */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
|
||||
((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
|
||||
((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
|
||||
|
||||
#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \
|
||||
((__LATENCY__) == FLASH_LATENCY_1))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Types FLASH Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FLASH Procedure structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_PROC_NONE = 0U,
|
||||
FLASH_PROC_PAGEERASE = 1U,
|
||||
FLASH_PROC_MASSERASE = 2U,
|
||||
FLASH_PROC_PROGRAMHALFWORD = 3U,
|
||||
FLASH_PROC_PROGRAMWORD = 4U,
|
||||
FLASH_PROC_PROGRAMDOUBLEWORD = 5U
|
||||
} FLASH_ProcedureTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FLASH handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
|
||||
|
||||
__IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */
|
||||
|
||||
__IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */
|
||||
|
||||
__IO uint64_t Data; /*!< Internal variable to save data to be programmed */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< FLASH locking object */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< FLASH error code
|
||||
This parameter can be a value of @ref FLASH_Error_Codes */
|
||||
} FLASH_ProcessTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Error_Codes FLASH Error Codes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */
|
||||
#define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */
|
||||
#define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Type_Program FLASH Type Program
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_TYPEPROGRAM_HALFWORD (0x01U) /*!<Program a half-word (16-bit) at a specified address.*/
|
||||
#define FLASH_TYPEPROGRAM_WORD (0x02U) /*!<Program a word (32-bit) at a specified address.*/
|
||||
#define FLASH_TYPEPROGRAM_DOUBLEWORD (0x03U) /*!<Program a double word (64-bit) at a specified address*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Latency FLASH Latency
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_LATENCY_0 (0x00000000U) /*!< FLASH Zero Latency cycle */
|
||||
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup FLASH_Flag_definition FLASH Flag definition
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
|
||||
#define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */
|
||||
#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
|
||||
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
|
||||
#define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error Interrupt source */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
|
||||
* @brief macros to control FLASH features
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup FLASH_EM_Latency FLASH Latency
|
||||
* @brief macros to handle FLASH Latency
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set the FLASH Latency.
|
||||
* @param __LATENCY__ FLASH Latency
|
||||
* The value of this parameter depend on device used within the same series
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get the FLASH Latency.
|
||||
* @retval FLASH Latency
|
||||
* The value of this parameter depend on device used within the same series
|
||||
*/
|
||||
#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Prefetch FLASH Prefetch
|
||||
* @brief macros to handle FLASH Prefetch buffer
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enable the FLASH prefetch buffer.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE)
|
||||
|
||||
/**
|
||||
* @brief Disable the FLASH prefetch buffer.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Interrupt FLASH Interrupts
|
||||
* @brief macros to handle FLASH interrupts
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the specified FLASH interrupt.
|
||||
* @param __INTERRUPT__ FLASH interrupt
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
|
||||
* @arg @ref FLASH_IT_ERR Error Interrupt
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) SET_BIT((FLASH->CR), (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified FLASH interrupt.
|
||||
* @param __INTERRUPT__ FLASH interrupt
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
|
||||
* @arg @ref FLASH_IT_ERR Error Interrupt
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT((FLASH->CR), (uint32_t)(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Get the specified FLASH flag status.
|
||||
* @param __FLAG__ specifies the FLASH flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref FLASH_FLAG_BSY FLASH Busy flag
|
||||
* @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
|
||||
* @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
|
||||
* @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag
|
||||
* @retval The new state of __FLAG__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_FLASH_GET_FLAG(__FLAG__) (((FLASH->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clear the specified FLASH flag.
|
||||
* @param __FLAG__ specifies the FLASH flags to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
|
||||
* @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
|
||||
* @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) ((FLASH->SR) = (__FLAG__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include FLASH HAL Extended module */
|
||||
#include "stm32f0xx_hal_flash_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup FLASH_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
|
||||
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
|
||||
|
||||
/* FLASH IRQ handler function */
|
||||
void HAL_FLASH_IRQHandler(void);
|
||||
/* Callbacks in non blocking modes */
|
||||
void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
|
||||
void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_FLASH_Unlock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_Lock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
uint32_t HAL_FLASH_GetError(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private function -------------------------------------------------*/
|
||||
/** @addtogroup FLASH_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0xx_HAL_FLASH_H */
|
||||
|
||||
|
||||
445
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h
Normal file
445
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h
Normal file
@@ -0,0 +1,445 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_flash_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of Flash HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0xx_HAL_FLASH_EX_H
|
||||
#define __STM32F0xx_HAL_FLASH_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \
|
||||
((VALUE) == FLASH_TYPEERASE_MASSERASE))
|
||||
|
||||
#define IS_OPTIONBYTE(VALUE) ((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA))
|
||||
|
||||
#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \
|
||||
((VALUE) == OB_WRPSTATE_ENABLE))
|
||||
|
||||
#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1))
|
||||
|
||||
#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
|
||||
((LEVEL) == OB_RDP_LEVEL_1))/*||\
|
||||
((LEVEL) == OB_RDP_LEVEL_2))*/
|
||||
|
||||
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
|
||||
|
||||
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
|
||||
|
||||
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
|
||||
|
||||
#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
|
||||
|
||||
#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))
|
||||
|
||||
#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET))
|
||||
|
||||
#if defined(FLASH_OBR_BOOT_SEL)
|
||||
#define IS_OB_BOOT_SEL(BOOT_SEL) (((BOOT_SEL) == OB_BOOT_SEL_RESET) || ((BOOT_SEL) == OB_BOOT_SEL_SET))
|
||||
#define IS_OB_BOOT0(BOOT0) (((BOOT0) == OB_BOOT0_RESET) || ((BOOT0) == OB_BOOT0_SET))
|
||||
#endif /* FLASH_OBR_BOOT_SEL */
|
||||
|
||||
|
||||
#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U))
|
||||
|
||||
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= FLASH_BANK1_END)
|
||||
|
||||
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_BANK1_END))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief FLASH Erase structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase.
|
||||
This parameter can be a value of @ref FLASHEx_Type_Erase */
|
||||
|
||||
uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled
|
||||
This parameter must be a number between Min_Data = FLASH_BASE and Max_Data = FLASH_BANK1_END */
|
||||
|
||||
uint32_t NbPages; /*!< NbPages: Number of pagess to be erased.
|
||||
This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/
|
||||
|
||||
} FLASH_EraseInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FLASH Options bytes program structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t OptionType; /*!< OptionType: Option byte to be configured.
|
||||
This parameter can be a value of @ref FLASHEx_OB_Type */
|
||||
|
||||
uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
|
||||
This parameter can be a value of @ref FLASHEx_OB_WRP_State */
|
||||
|
||||
uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected
|
||||
This parameter can be a value of @ref FLASHEx_OB_Write_Protection */
|
||||
|
||||
uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level..
|
||||
This parameter can be a value of @ref FLASHEx_OB_Read_Protection */
|
||||
|
||||
uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
|
||||
IWDG / STOP / STDBY / BOOT1 / VDDA_ANALOG / SRAM_PARITY
|
||||
This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
|
||||
@ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1, @ref FLASHEx_OB_VDDA_Analog_Monitoring and
|
||||
@ref FLASHEx_OB_RAM_Parity_Check_Enable */
|
||||
|
||||
uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed
|
||||
This parameter can be a value of @ref FLASHEx_OB_Data_Address */
|
||||
|
||||
uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
|
||||
} FLASH_OBProgramInitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Page_Size FLASHEx Page Size
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) \
|
||||
|| defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F070x6)
|
||||
#define FLASH_PAGE_SIZE 0x400U
|
||||
#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx || STM32F070x6 */
|
||||
|
||||
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) \
|
||||
|| defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
|
||||
#define FLASH_PAGE_SIZE 0x800U
|
||||
#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F030xC */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_TYPEERASE_PAGES (0x00U) /*!<Pages erase only*/
|
||||
#define FLASH_TYPEERASE_MASSERASE (0x01U) /*!<Flash mass erase activation*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OptionByte_Constants Option Byte Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_Type Option Bytes Type
|
||||
* @{
|
||||
*/
|
||||
#define OPTIONBYTE_WRP (0x01U) /*!<WRP option byte configuration*/
|
||||
#define OPTIONBYTE_RDP (0x02U) /*!<RDP option byte configuration*/
|
||||
#define OPTIONBYTE_USER (0x04U) /*!<USER option byte configuration*/
|
||||
#define OPTIONBYTE_DATA (0x08U) /*!<DATA option byte configuration*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_WRP_State Option Byte WRP State
|
||||
* @{
|
||||
*/
|
||||
#define OB_WRPSTATE_DISABLE (0x00U) /*!<Disable the write protection of the desired pages*/
|
||||
#define OB_WRPSTATE_ENABLE (0x01U) /*!<Enable the write protection of the desired pagess*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_Write_Protection FLASHEx OB Write Protection
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) \
|
||||
|| defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F070x6)
|
||||
#define OB_WRP_PAGES0TO3 (0x00000001U) /* Write protection of page 0 to 3 */
|
||||
#define OB_WRP_PAGES4TO7 (0x00000002U) /* Write protection of page 4 to 7 */
|
||||
#define OB_WRP_PAGES8TO11 (0x00000004U) /* Write protection of page 8 to 11 */
|
||||
#define OB_WRP_PAGES12TO15 (0x00000008U) /* Write protection of page 12 to 15 */
|
||||
#define OB_WRP_PAGES16TO19 (0x00000010U) /* Write protection of page 16 to 19 */
|
||||
#define OB_WRP_PAGES20TO23 (0x00000020U) /* Write protection of page 20 to 23 */
|
||||
#define OB_WRP_PAGES24TO27 (0x00000040U) /* Write protection of page 24 to 27 */
|
||||
#define OB_WRP_PAGES28TO31 (0x00000080U) /* Write protection of page 28 to 31 */
|
||||
#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
|
||||
#define OB_WRP_PAGES32TO35 (0x00000100U) /* Write protection of page 32 to 35 */
|
||||
#define OB_WRP_PAGES36TO39 (0x00000200U) /* Write protection of page 36 to 39 */
|
||||
#define OB_WRP_PAGES40TO43 (0x00000400U) /* Write protection of page 40 to 43 */
|
||||
#define OB_WRP_PAGES44TO47 (0x00000800U) /* Write protection of page 44 to 47 */
|
||||
#define OB_WRP_PAGES48TO51 (0x00001000U) /* Write protection of page 48 to 51 */
|
||||
#define OB_WRP_PAGES52TO57 (0x00002000U) /* Write protection of page 52 to 57 */
|
||||
#define OB_WRP_PAGES56TO59 (0x00004000U) /* Write protection of page 56 to 59 */
|
||||
#define OB_WRP_PAGES60TO63 (0x00008000U) /* Write protection of page 60 to 63 */
|
||||
#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
|
||||
|
||||
#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) \
|
||||
|| defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F070x6)
|
||||
#define OB_WRP_PAGES0TO31MASK (0x000000FFU)
|
||||
#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F038xx || STM32F058xx || STM32F070x6 */
|
||||
|
||||
#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
|
||||
#define OB_WRP_PAGES32TO63MASK (0x0000FF00U)
|
||||
#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
|
||||
|
||||
#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F038xx)|| defined(STM32F070x6)
|
||||
#define OB_WRP_ALLPAGES (0x000000FFU) /*!< Write protection of all pages */
|
||||
#endif /* STM32F030x6 || STM32F031x6 || STM32F042x6 || STM32F048xx || STM32F038xx || STM32F070x6 */
|
||||
|
||||
#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
|
||||
#define OB_WRP_ALLPAGES (0x0000FFFFU) /*!< Write protection of all pages */
|
||||
#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
|
||||
#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F038xx || STM32F058xx || STM32F070x6 */
|
||||
|
||||
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) \
|
||||
|| defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
|
||||
#define OB_WRP_PAGES0TO1 (0x00000001U) /* Write protection of page 0 to 1 */
|
||||
#define OB_WRP_PAGES2TO3 (0x00000002U) /* Write protection of page 2 to 3 */
|
||||
#define OB_WRP_PAGES4TO5 (0x00000004U) /* Write protection of page 4 to 5 */
|
||||
#define OB_WRP_PAGES6TO7 (0x00000008U) /* Write protection of page 6 to 7 */
|
||||
#define OB_WRP_PAGES8TO9 (0x00000010U) /* Write protection of page 8 to 9 */
|
||||
#define OB_WRP_PAGES10TO11 (0x00000020U) /* Write protection of page 10 to 11 */
|
||||
#define OB_WRP_PAGES12TO13 (0x00000040U) /* Write protection of page 12 to 13 */
|
||||
#define OB_WRP_PAGES14TO15 (0x00000080U) /* Write protection of page 14 to 15 */
|
||||
#define OB_WRP_PAGES16TO17 (0x00000100U) /* Write protection of page 16 to 17 */
|
||||
#define OB_WRP_PAGES18TO19 (0x00000200U) /* Write protection of page 18 to 19 */
|
||||
#define OB_WRP_PAGES20TO21 (0x00000400U) /* Write protection of page 20 to 21 */
|
||||
#define OB_WRP_PAGES22TO23 (0x00000800U) /* Write protection of page 22 to 23 */
|
||||
#define OB_WRP_PAGES24TO25 (0x00001000U) /* Write protection of page 24 to 25 */
|
||||
#define OB_WRP_PAGES26TO27 (0x00002000U) /* Write protection of page 26 to 27 */
|
||||
#define OB_WRP_PAGES28TO29 (0x00004000U) /* Write protection of page 28 to 29 */
|
||||
#define OB_WRP_PAGES30TO31 (0x00008000U) /* Write protection of page 30 to 31 */
|
||||
#define OB_WRP_PAGES32TO33 (0x00010000U) /* Write protection of page 32 to 33 */
|
||||
#define OB_WRP_PAGES34TO35 (0x00020000U) /* Write protection of page 34 to 35 */
|
||||
#define OB_WRP_PAGES36TO37 (0x00040000U) /* Write protection of page 36 to 37 */
|
||||
#define OB_WRP_PAGES38TO39 (0x00080000U) /* Write protection of page 38 to 39 */
|
||||
#define OB_WRP_PAGES40TO41 (0x00100000U) /* Write protection of page 40 to 41 */
|
||||
#define OB_WRP_PAGES42TO43 (0x00200000U) /* Write protection of page 42 to 43 */
|
||||
#define OB_WRP_PAGES44TO45 (0x00400000U) /* Write protection of page 44 to 45 */
|
||||
#define OB_WRP_PAGES46TO47 (0x00800000U) /* Write protection of page 46 to 47 */
|
||||
#define OB_WRP_PAGES48TO49 (0x01000000U) /* Write protection of page 48 to 49 */
|
||||
#define OB_WRP_PAGES50TO51 (0x02000000U) /* Write protection of page 50 to 51 */
|
||||
#define OB_WRP_PAGES52TO53 (0x04000000U) /* Write protection of page 52 to 53 */
|
||||
#define OB_WRP_PAGES54TO55 (0x08000000U) /* Write protection of page 54 to 55 */
|
||||
#define OB_WRP_PAGES56TO57 (0x10000000U) /* Write protection of page 56 to 57 */
|
||||
#define OB_WRP_PAGES58TO59 (0x20000000U) /* Write protection of page 58 to 59 */
|
||||
#define OB_WRP_PAGES60TO61 (0x40000000U) /* Write protection of page 60 to 61 */
|
||||
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
|
||||
#define OB_WRP_PAGES62TO63 (0x80000000U) /* Write protection of page 62 to 63 */
|
||||
#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB */
|
||||
#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
|
||||
#define OB_WRP_PAGES62TO127 (0x80000000U) /* Write protection of page 62 to 127 */
|
||||
#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
|
||||
|
||||
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) \
|
||||
|| defined(STM32F091xC) || defined(STM32F098xx)|| defined(STM32F030xC)
|
||||
#define OB_WRP_PAGES0TO15MASK (0x000000FFU)
|
||||
#define OB_WRP_PAGES16TO31MASK (0x0000FF00U)
|
||||
#define OB_WRP_PAGES32TO47MASK (0x00FF0000U)
|
||||
#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F070xB || STM32F030xC */
|
||||
|
||||
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
|
||||
#define OB_WRP_PAGES48TO63MASK (0xFF000000U)
|
||||
#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB */
|
||||
#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
|
||||
#define OB_WRP_PAGES48TO127MASK (0xFF000000U)
|
||||
#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
|
||||
|
||||
#define OB_WRP_ALLPAGES (0xFFFFFFFFU) /*!< Write protection of all pages */
|
||||
#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F030xC || STM32F070xB */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_Read_Protection Option Byte Read Protection
|
||||
* @{
|
||||
*/
|
||||
#define OB_RDP_LEVEL_0 ((uint8_t)0xAAU)
|
||||
#define OB_RDP_LEVEL_1 ((uint8_t)0xBBU)
|
||||
#define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /*!< Warning: When enabling read protection level 2
|
||||
it's no more possible to go back to level 1 or 0 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_IWatchdog Option Byte IWatchdog
|
||||
* @{
|
||||
*/
|
||||
#define OB_IWDG_SW ((uint8_t)0x01U) /*!< Software IWDG selected */
|
||||
#define OB_IWDG_HW ((uint8_t)0x00U) /*!< Hardware IWDG selected */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_nRST_STOP Option Byte nRST STOP
|
||||
* @{
|
||||
*/
|
||||
#define OB_STOP_NO_RST ((uint8_t)0x02U) /*!< No reset generated when entering in STOP */
|
||||
#define OB_STOP_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STOP */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_nRST_STDBY Option Byte nRST STDBY
|
||||
* @{
|
||||
*/
|
||||
#define OB_STDBY_NO_RST ((uint8_t)0x04U) /*!< No reset generated when entering in STANDBY */
|
||||
#define OB_STDBY_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STANDBY */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_BOOT1 Option Byte BOOT1
|
||||
* @{
|
||||
*/
|
||||
#define OB_BOOT1_RESET ((uint8_t)0x00U) /*!< BOOT1 Reset */
|
||||
#define OB_BOOT1_SET ((uint8_t)0x10U) /*!< BOOT1 Set */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_VDDA_Analog_Monitoring Option Byte VDDA Analog Monitoring
|
||||
* @{
|
||||
*/
|
||||
#define OB_VDDA_ANALOG_ON ((uint8_t)0x20U) /*!< Analog monitoring on VDDA Power source ON */
|
||||
#define OB_VDDA_ANALOG_OFF ((uint8_t)0x00U) /*!< Analog monitoring on VDDA Power source OFF */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_RAM_Parity_Check_Enable Option Byte SRAM Parity Check Enable
|
||||
* @{
|
||||
*/
|
||||
#define OB_SRAM_PARITY_SET ((uint8_t)0x00U) /*!< SRAM parity check enable set */
|
||||
#define OB_SRAM_PARITY_RESET ((uint8_t)0x40U) /*!< SRAM parity check enable reset */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(FLASH_OBR_BOOT_SEL)
|
||||
/** @defgroup FLASHEx_OB_BOOT_SEL FLASHEx Option Byte BOOT SEL
|
||||
* @{
|
||||
*/
|
||||
#define OB_BOOT_SEL_RESET ((uint8_t)0x00U) /*!< BOOT_SEL Reset */
|
||||
#define OB_BOOT_SEL_SET ((uint8_t)0x80U) /*!< BOOT_SEL Set */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_BOOT0 FLASHEx Option Byte BOOT0
|
||||
* @{
|
||||
*/
|
||||
#define OB_BOOT0_RESET ((uint8_t)0x00U) /*!< BOOT0 Reset */
|
||||
#define OB_BOOT0_SET ((uint8_t)0x08U) /*!< BOOT0 Set */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FLASH_OBR_BOOT_SEL */
|
||||
|
||||
|
||||
/** @defgroup FLASHEx_OB_Data_Address Option Byte Data Address
|
||||
* @{
|
||||
*/
|
||||
#define OB_DATA_ADDRESS_DATA0 (0x1FFFF804U)
|
||||
#define OB_DATA_ADDRESS_DATA1 (0x1FFFF806U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup FLASHEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OBErase(void);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0xx_HAL_FLASH_EX_H */
|
||||
|
||||
|
||||
320
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h
Normal file
320
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h
Normal file
@@ -0,0 +1,320 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_gpio.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of GPIO HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0xx_HAL_GPIO_H
|
||||
#define __STM32F0xx_HAL_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Types GPIO Exported Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief GPIO Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_pins */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_mode */
|
||||
|
||||
uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_pull */
|
||||
|
||||
uint32_t Speed; /*!< Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_speed */
|
||||
|
||||
uint32_t Alternate; /*!< Peripheral to be connected to the selected pins
|
||||
This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
|
||||
}GPIO_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief GPIO Bit SET and Bit RESET enumeration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PIN_RESET = 0U,
|
||||
GPIO_PIN_SET
|
||||
}GPIO_PinState;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup GPIO_pins GPIO pins
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */
|
||||
#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */
|
||||
#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */
|
||||
#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */
|
||||
#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */
|
||||
#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */
|
||||
#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */
|
||||
#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */
|
||||
#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */
|
||||
#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */
|
||||
#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */
|
||||
#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */
|
||||
#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */
|
||||
#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */
|
||||
#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */
|
||||
#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */
|
||||
#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */
|
||||
|
||||
#define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_mode GPIO mode
|
||||
* @brief GPIO Configuration Mode
|
||||
* Elements values convention: 0x00WX00YZ
|
||||
* - W : EXTI trigger detection on 3 bits
|
||||
* - X : EXTI mode (IT or Event) on 2 bits
|
||||
* - Y : Output type (Push Pull or Open Drain) on 1 bit
|
||||
* - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */
|
||||
#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */
|
||||
#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */
|
||||
#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */
|
||||
#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */
|
||||
|
||||
#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */
|
||||
|
||||
#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
|
||||
#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection *//**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_speed GPIO speed
|
||||
* @brief GPIO Output Maximum frequency
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< range up to 2 MHz, please refer to the product datasheet */
|
||||
#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< range 4 MHz to 10 MHz, please refer to the product datasheet */
|
||||
#define GPIO_SPEED_FREQ_HIGH (0x00000003U) /*!< range 10 MHz to 50 MHz, please refer to the product datasheet */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pull GPIO pull
|
||||
* @brief GPIO Pull-Up or Pull-Down Activation
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */
|
||||
#define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */
|
||||
#define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified EXTI line flag is set or not.
|
||||
* @param __EXTI_LINE__ specifies the EXTI line flag to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval The new state of __EXTI_LINE__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Clear the EXTI's line pending flags.
|
||||
* @param __EXTI_LINE__ specifies the EXTI lines flags to clear.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified EXTI line is asserted or not.
|
||||
* @param __EXTI_LINE__ specifies the EXTI line to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval The new state of __EXTI_LINE__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Clear the EXTI's line pending bits.
|
||||
* @param __EXTI_LINE__ specifies the EXTI lines to clear.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on selected EXTI line.
|
||||
* @param __EXTI_LINE__ specifies the EXTI line to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Private_Constants GPIO Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_MODE_Pos 0U
|
||||
#define GPIO_MODE (0x3UL << GPIO_MODE_Pos)
|
||||
#define MODE_INPUT (0x0UL << GPIO_MODE_Pos)
|
||||
#define MODE_OUTPUT (0x1UL << GPIO_MODE_Pos)
|
||||
#define MODE_AF (0x2UL << GPIO_MODE_Pos)
|
||||
#define MODE_ANALOG (0x3UL << GPIO_MODE_Pos)
|
||||
#define OUTPUT_TYPE_Pos 4U
|
||||
#define OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos)
|
||||
#define OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos)
|
||||
#define OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos)
|
||||
#define EXTI_MODE_Pos 16U
|
||||
#define EXTI_MODE (0x3UL << EXTI_MODE_Pos)
|
||||
#define EXTI_IT (0x1UL << EXTI_MODE_Pos)
|
||||
#define EXTI_EVT (0x2UL << EXTI_MODE_Pos)
|
||||
#define TRIGGER_MODE_Pos 20U
|
||||
#define TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos)
|
||||
#define TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos)
|
||||
#define TRIGGER_FALLING (0x2UL << TRIGGER_MODE_Pos)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Private_Macros GPIO Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
|
||||
|
||||
#define IS_GPIO_PIN(__PIN__) (((((uint32_t)(__PIN__)) & GPIO_PIN_MASK) != 0x00U) &&\
|
||||
((((uint32_t)(__PIN__)) & ~GPIO_PIN_MASK) == 0x00U))
|
||||
|
||||
#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
|
||||
((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\
|
||||
((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\
|
||||
((__MODE__) == GPIO_MODE_AF_PP) ||\
|
||||
((__MODE__) == GPIO_MODE_AF_OD) ||\
|
||||
((__MODE__) == GPIO_MODE_IT_RISING) ||\
|
||||
((__MODE__) == GPIO_MODE_IT_FALLING) ||\
|
||||
((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\
|
||||
((__MODE__) == GPIO_MODE_EVT_RISING) ||\
|
||||
((__MODE__) == GPIO_MODE_EVT_FALLING) ||\
|
||||
((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
|
||||
((__MODE__) == GPIO_MODE_ANALOG))
|
||||
|
||||
#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\
|
||||
((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\
|
||||
((__SPEED__) == GPIO_SPEED_FREQ_HIGH))
|
||||
|
||||
#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\
|
||||
((__PULL__) == GPIO_PULLUP) || \
|
||||
((__PULL__) == GPIO_PULLDOWN))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include GPIO HAL Extended module */
|
||||
#include "stm32f0xx_hal_gpio_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup GPIO_Exported_Functions GPIO Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
|
||||
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
|
||||
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0xx_HAL_GPIO_H */
|
||||
|
||||
797
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h
Normal file
797
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h
Normal file
@@ -0,0 +1,797 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_gpio_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of GPIO HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0xx_HAL_GPIO_EX_H
|
||||
#define __STM32F0xx_HAL_GPIO_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIOEx GPIOEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (STM32F030x6)
|
||||
/*------------------------- STM32F030x6---------------------------*/
|
||||
/* AF 0 */
|
||||
#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */
|
||||
#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */
|
||||
|
||||
/* AF 1 */
|
||||
#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */
|
||||
|
||||
/* AF 2 */
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */
|
||||
|
||||
/* AF 3 */
|
||||
#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */
|
||||
|
||||
/* AF 4 */
|
||||
#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */
|
||||
|
||||
/* AF 5 */
|
||||
#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */
|
||||
|
||||
/* AF 6 */
|
||||
#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U)
|
||||
|
||||
#endif /* STM32F030x6 */
|
||||
|
||||
/*---------------------------------- STM32F030x8 -------------------------------------------*/
|
||||
#if defined (STM32F030x8)
|
||||
/* AF 0 */
|
||||
#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */
|
||||
#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */
|
||||
|
||||
/* AF 1 */
|
||||
#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */
|
||||
|
||||
/* AF 2 */
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */
|
||||
|
||||
/* AF 3 */
|
||||
#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */
|
||||
|
||||
/* AF 4 */
|
||||
#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */
|
||||
|
||||
/* AF 5 */
|
||||
#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */
|
||||
|
||||
/* AF 6 */
|
||||
#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U)
|
||||
|
||||
#endif /* STM32F030x8 */
|
||||
|
||||
#if defined (STM32F031x6) || defined (STM32F038xx)
|
||||
/*--------------------------- STM32F031x6/STM32F038xx ---------------------------*/
|
||||
/* AF 0 */
|
||||
#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF0_SWDAT ((uint8_t)0x00U) /*!< AF0: SWDAT Alternate Function mapping */
|
||||
#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */
|
||||
|
||||
/* AF 1 */
|
||||
#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */
|
||||
|
||||
/* AF 2 */
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */
|
||||
|
||||
/* AF 3 */
|
||||
#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */
|
||||
|
||||
/* AF 4 */
|
||||
#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */
|
||||
|
||||
/* AF 5 */
|
||||
#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */
|
||||
|
||||
/* AF 6 */
|
||||
#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U)
|
||||
|
||||
#endif /* STM32F031x6 || STM32F038xx */
|
||||
|
||||
#if defined (STM32F051x8) || defined (STM32F058xx)
|
||||
/*--------------------------- STM32F051x8/STM32F058xx---------------------------*/
|
||||
/* AF 0 */
|
||||
#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */
|
||||
#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */
|
||||
#define GPIO_AF0_CEC ((uint8_t)0x00U) /*!< AF0: CEC Alternate Function mapping */
|
||||
|
||||
/* AF 1 */
|
||||
#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */
|
||||
#define GPIO_AF1_CEC ((uint8_t)0x01U) /*!< AF1: CEC Alternate Function mapping */
|
||||
|
||||
/* AF 2 */
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */
|
||||
|
||||
/* AF 3 */
|
||||
#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF3_TSC ((uint8_t)0x03U) /*!< AF3: TSC Alternate Function mapping */
|
||||
|
||||
/* AF 4 */
|
||||
#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */
|
||||
|
||||
/* AF 5 */
|
||||
#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */
|
||||
|
||||
/* AF 6 */
|
||||
#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */
|
||||
|
||||
/* AF 7 */
|
||||
#define GPIO_AF7_COMP1 ((uint8_t)0x07U) /*!< AF7: COMP1 Alternate Function mapping */
|
||||
#define GPIO_AF7_COMP2 ((uint8_t)0x07U) /*!< AF7: COMP2 Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07U)
|
||||
|
||||
#endif /* STM32F051x8/STM32F058xx */
|
||||
|
||||
#if defined (STM32F071xB)
|
||||
/*--------------------------- STM32F071xB ---------------------------*/
|
||||
/* AF 0 */
|
||||
#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: AEVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */
|
||||
#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */
|
||||
#define GPIO_AF0_CEC ((uint8_t)0x00U) /*!< AF0: CEC Alternate Function mapping */
|
||||
#define GPIO_AF0_CRS ((uint8_t)0x00U) /*!< AF0: CRS Alternate Function mapping */
|
||||
#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM1 ((uint8_t)0x00U) /*!< AF0: TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM16 ((uint8_t)0x00U) /*!< AF0: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF0_TSC ((uint8_t)0x00U) /*!< AF0: TSC Alternate Function mapping */
|
||||
#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART2 ((uint8_t)0x00U) /*!< AF0: USART2 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART3 ((uint8_t)0x00U) /*!< AF0: USART3 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART4 ((uint8_t)0x00U) /*!< AF0: USART4 Alternate Function mapping */
|
||||
|
||||
/* AF 1 */
|
||||
#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART3 ((uint8_t)0x01U) /*!< AF1: USART3 Alternate Function mapping */
|
||||
#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */
|
||||
#define GPIO_AF1_CEC ((uint8_t)0x01U) /*!< AF1: CEC Alternate Function mapping */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF1_TSC ((uint8_t)0x01U) /*!< AF1: TSC Alternate Function mapping */
|
||||
#define GPIO_AF1_SPI1 ((uint8_t)0x01U) /*!< AF1: SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */
|
||||
|
||||
/* AF 2 */
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */
|
||||
|
||||
/* AF 3 */
|
||||
#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF3_TSC ((uint8_t)0x03U) /*!< AF3: TSC Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */
|
||||
|
||||
/* AF 4 */
|
||||
#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF4_USART4 ((uint8_t)0x04U) /*!< AF4: USART4 Alternate Function mapping */
|
||||
#define GPIO_AF4_USART3 ((uint8_t)0x04U) /*!< AF4: USART3 Alternate Function mapping */
|
||||
#define GPIO_AF4_CRS ((uint8_t)0x04U) /*!< AF4: CRS Alternate Function mapping */
|
||||
|
||||
/* AF 5 */
|
||||
#define GPIO_AF5_TIM15 ((uint8_t)0x05U) /*!< AF5: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */
|
||||
|
||||
/* AF 6 */
|
||||
#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */
|
||||
|
||||
/* AF 7 */
|
||||
#define GPIO_AF7_COMP1 ((uint8_t)0x07U) /*!< AF7: COMP1 Alternate Function mapping */
|
||||
#define GPIO_AF7_COMP2 ((uint8_t)0x07U) /*!< AF7: COMP2 Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07U)
|
||||
|
||||
#endif /* STM32F071xB */
|
||||
|
||||
|
||||
#if defined(STM32F091xC) || defined(STM32F098xx)
|
||||
/*--------------------------- STM32F091xC || STM32F098xx ------------------------------*/
|
||||
/* AF 0 */
|
||||
#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */
|
||||
#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */
|
||||
#define GPIO_AF0_CEC ((uint8_t)0x00U) /*!< AF0: CEC Alternate Function mapping */
|
||||
#define GPIO_AF0_CRS ((uint8_t)0x00U) /*!< AF0: CRS Alternate Function mapping */
|
||||
#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM1 ((uint8_t)0x00U) /*!< AF0: TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM16 ((uint8_t)0x00U) /*!< AF0: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF0_TSC ((uint8_t)0x00U) /*!< AF0: TSC Alternate Function mapping */
|
||||
#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART2 ((uint8_t)0x00U) /*!< AF0: USART2 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART3 ((uint8_t)0x00U) /*!< AF0: USART3 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART4 ((uint8_t)0x00U) /*!< AF0: USART4 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART8 ((uint8_t)0x00U) /*!< AF0: USART8 Alternate Function mapping */
|
||||
#define GPIO_AF0_CAN ((uint8_t)0x00U) /*!< AF0: CAN Alternate Function mapping */
|
||||
|
||||
/* AF 1 */
|
||||
#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART3 ((uint8_t)0x01U) /*!< AF1: USART3 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART4 ((uint8_t)0x01U) /*!< AF1: USART4 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART5 ((uint8_t)0x01U) /*!< AF1: USART5 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART6 ((uint8_t)0x01U) /*!< AF1: USART6 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART7 ((uint8_t)0x01U) /*!< AF1: USART7 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART8 ((uint8_t)0x01U) /*!< AF1: USART8 Alternate Function mapping */
|
||||
#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */
|
||||
#define GPIO_AF1_CEC ((uint8_t)0x01U) /*!< AF1: CEC Alternate Function mapping */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF1_TSC ((uint8_t)0x01U) /*!< AF1: TSC Alternate Function mapping */
|
||||
#define GPIO_AF1_SPI1 ((uint8_t)0x01U) /*!< AF1: SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */
|
||||
|
||||
/* AF 2 */
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF2_USART5 ((uint8_t)0x02U) /*!< AF2: USART5 Alternate Function mapping */
|
||||
#define GPIO_AF2_USART6 ((uint8_t)0x02U) /*!< AF2: USART6 Alternate Function mapping */
|
||||
#define GPIO_AF2_USART7 ((uint8_t)0x02U) /*!< AF2: USART7 Alternate Function mapping */
|
||||
#define GPIO_AF2_USART8 ((uint8_t)0x02U) /*!< AF2: USART8 Alternate Function mapping */
|
||||
|
||||
/* AF 3 */
|
||||
#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF3_TSC ((uint8_t)0x03U) /*!< AF3: TSC Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */
|
||||
|
||||
/* AF 4 */
|
||||
#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF4_USART4 ((uint8_t)0x04U) /*!< AF4: USART4 Alternate Function mapping */
|
||||
#define GPIO_AF4_USART3 ((uint8_t)0x04U) /*!< AF4: USART3 Alternate Function mapping */
|
||||
#define GPIO_AF4_CRS ((uint8_t)0x04U) /*!< AF4: CRS Alternate Function mapping */
|
||||
#define GPIO_AF4_CAN ((uint8_t)0x04U) /*!< AF4: CAN Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_USART5 ((uint8_t)0x04U) /*!< AF4: USART5 Alternate Function mapping */
|
||||
|
||||
/* AF 5 */
|
||||
#define GPIO_AF5_TIM15 ((uint8_t)0x05U) /*!< AF5: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF5_MCO ((uint8_t)0x05U) /*!< AF5: MCO Alternate Function mapping */
|
||||
#define GPIO_AF5_USART6 ((uint8_t)0x05U) /*!< AF5: USART6 Alternate Function mapping */
|
||||
|
||||
/* AF 6 */
|
||||
#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */
|
||||
|
||||
/* AF 7 */
|
||||
#define GPIO_AF7_COMP1 ((uint8_t)0x07U) /*!< AF7: COMP1 Alternate Function mapping */
|
||||
#define GPIO_AF7_COMP2 ((uint8_t)0x07U) /*!< AF7: COMP2 Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07U)
|
||||
|
||||
#endif /* STM32F091xC || STM32F098xx */
|
||||
|
||||
#if defined(STM32F030xC)
|
||||
/*--------------------------- STM32F030xC ----------------------------------------------------*/
|
||||
/* AF 0 */
|
||||
#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */
|
||||
#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */
|
||||
#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART4 ((uint8_t)0x00U) /*!< AF0: USART4 Alternate Function mapping */
|
||||
|
||||
/* AF 1 */
|
||||
#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART3 ((uint8_t)0x01U) /*!< AF1: USART3 Alternate Function mapping */
|
||||
#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */
|
||||
|
||||
/* AF 2 */
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF2_USART5 ((uint8_t)0x02U) /*!< AF2: USART5 Alternate Function mapping */
|
||||
#define GPIO_AF2_USART6 ((uint8_t)0x02U) /*!< AF2: USART6 Alternate Function mapping */
|
||||
|
||||
/* AF 3 */
|
||||
#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */
|
||||
|
||||
/* AF 4 */
|
||||
#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF4_USART4 ((uint8_t)0x04U) /*!< AF4: USART4 Alternate Function mapping */
|
||||
#define GPIO_AF4_USART3 ((uint8_t)0x04U) /*!< AF4: USART3 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_USART5 ((uint8_t)0x04U) /*!< AF4: USART5 Alternate Function mapping */
|
||||
|
||||
/* AF 5 */
|
||||
#define GPIO_AF5_TIM15 ((uint8_t)0x05U) /*!< AF5: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF5_MCO ((uint8_t)0x05U) /*!< AF5: MCO Alternate Function mapping */
|
||||
#define GPIO_AF5_USART6 ((uint8_t)0x05U) /*!< AF5: USART6 Alternate Function mapping */
|
||||
|
||||
/* AF 6 */
|
||||
#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U)
|
||||
|
||||
#endif /* STM32F030xC */
|
||||
|
||||
#if defined (STM32F072xB) || defined (STM32F078xx)
|
||||
/*--------------------------- STM32F072xB/STM32F078xx ---------------------------*/
|
||||
/* AF 0 */
|
||||
#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */
|
||||
#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */
|
||||
#define GPIO_AF0_CEC ((uint8_t)0x00U) /*!< AF0: CEC Alternate Function mapping */
|
||||
#define GPIO_AF0_CRS ((uint8_t)0x00U) /*!< AF0: CRS Alternate Function mapping */
|
||||
#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM1 ((uint8_t)0x00U) /*!< AF0: TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM16 ((uint8_t)0x00U) /*!< AF0: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF0_TSC ((uint8_t)0x00U) /*!< AF0: TSC Alternate Function mapping */
|
||||
#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART2 ((uint8_t)0x00U) /*!< AF0: USART2 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART3 ((uint8_t)0x00U) /*!< AF0: USART3 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART4 ((uint8_t)0x00U) /*!< AF0: USART4 Alternate Function mapping */
|
||||
#define GPIO_AF0_CAN ((uint8_t)0x00U) /*!< AF0: CAN Alternate Function mapping */
|
||||
|
||||
/* AF 1 */
|
||||
#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART3 ((uint8_t)0x01U) /*!< AF1: USART3 Alternate Function mapping */
|
||||
#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */
|
||||
#define GPIO_AF1_CEC ((uint8_t)0x01U) /*!< AF1: CEC Alternate Function mapping */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF1_TSC ((uint8_t)0x01U) /*!< AF1: TSC Alternate Function mapping */
|
||||
#define GPIO_AF1_SPI1 ((uint8_t)0x01U) /*!< AF1: SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */
|
||||
|
||||
/* AF 2 */
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF2_USB ((uint8_t)0x02U) /*!< AF2: USB Alternate Function mapping */
|
||||
|
||||
/* AF 3 */
|
||||
#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF3_TSC ((uint8_t)0x03U) /*!< AF3: TSC Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */
|
||||
|
||||
/* AF 4 */
|
||||
#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF4_USART4 ((uint8_t)0x04U) /*!< AF4: USART4 Alternate Function mapping */
|
||||
#define GPIO_AF4_USART3 ((uint8_t)0x04U) /*!< AF4: USART3 Alternate Function mapping */
|
||||
#define GPIO_AF4_CRS ((uint8_t)0x04U) /*!< AF4: CRS Alternate Function mapping */
|
||||
#define GPIO_AF4_CAN ((uint8_t)0x04U) /*!< AF4: CAN Alternate Function mapping */
|
||||
|
||||
/* AF 5 */
|
||||
#define GPIO_AF5_TIM15 ((uint8_t)0x05U) /*!< AF5: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */
|
||||
|
||||
/* AF 6 */
|
||||
#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */
|
||||
|
||||
/* AF 7 */
|
||||
#define GPIO_AF7_COMP1 ((uint8_t)0x07U) /*!< AF7: COMP1 Alternate Function mapping */
|
||||
#define GPIO_AF7_COMP2 ((uint8_t)0x07U) /*!< AF7: COMP2 Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07U)
|
||||
|
||||
#endif /* STM32F072xB || STM32F078xx */
|
||||
|
||||
#if defined (STM32F070xB)
|
||||
/*---------------------------------- STM32F070xB ---------------------------------------------*/
|
||||
/* AF 0 */
|
||||
#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */
|
||||
#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */
|
||||
#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART4 ((uint8_t)0x00U) /*!< AF0: USART4 Alternate Function mapping */
|
||||
|
||||
/* AF 1 */
|
||||
#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART3 ((uint8_t)0x01U) /*!< AF1: USART4 Alternate Function mapping */
|
||||
#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */
|
||||
|
||||
/* AF 2 */
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF2_USB ((uint8_t)0x02U) /*!< AF2: USB Alternate Function mapping */
|
||||
|
||||
/* AF 3 */
|
||||
#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */
|
||||
|
||||
/* AF 4 */
|
||||
#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF4_USART4 ((uint8_t)0x04U) /*!< AF4: USART4 Alternate Function mapping */
|
||||
#define GPIO_AF4_USART3 ((uint8_t)0x04U) /*!< AF4: USART3 Alternate Function mapping */
|
||||
|
||||
/* AF 5 */
|
||||
#define GPIO_AF5_TIM15 ((uint8_t)0x05U) /*!< AF5: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */
|
||||
|
||||
/* AF 6 */
|
||||
#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U)
|
||||
|
||||
#endif /* STM32F070xB */
|
||||
|
||||
#if defined (STM32F042x6) || defined (STM32F048xx)
|
||||
/*--------------------------- STM32F042x6/STM32F048xx ---------------------------*/
|
||||
/* AF 0 */
|
||||
#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF0_CEC ((uint8_t)0x00U) /*!< AF0: CEC Alternate Function mapping */
|
||||
#define GPIO_AF0_CRS ((uint8_t)0x00U) /*!< AF0: CRS Alternate Function mapping */
|
||||
#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */
|
||||
#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */
|
||||
|
||||
/* AF 1 */
|
||||
#define GPIO_AF1_CEC ((uint8_t)0x01U) /*!< AF1: CEC Alternate Function mapping */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */
|
||||
#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */
|
||||
|
||||
/* AF 2 */
|
||||
#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF2_USB ((uint8_t)0x02U) /*!< AF2: USB Alternate Function mapping */
|
||||
|
||||
/* AF 3 */
|
||||
#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF3_TSC ((uint8_t)0x03U) /*!< AF3: TSC Alternate Function mapping */
|
||||
|
||||
/* AF 4 */
|
||||
#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF4_CAN ((uint8_t)0x04U) /*!< AF4: CAN Alternate Function mapping */
|
||||
#define GPIO_AF4_CRS ((uint8_t)0x04U) /*!< AF4: CRS Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */
|
||||
|
||||
/* AF 5 */
|
||||
#define GPIO_AF5_MCO ((uint8_t)0x05U) /*!< AF5: MCO Alternate Function mapping */
|
||||
#define GPIO_AF5_I2C1 ((uint8_t)0x05U) /*!< AF5: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF5_USB ((uint8_t)0x05U) /*!< AF5: USB Alternate Function mapping */
|
||||
|
||||
/* AF 6 */
|
||||
#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U)
|
||||
|
||||
#endif /* STM32F042x6 || STM32F048xx */
|
||||
|
||||
#if defined (STM32F070x6)
|
||||
/*--------------------------------------- STM32F070x6 ----------------------------------------*/
|
||||
/* AF 0 */
|
||||
#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */
|
||||
#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */
|
||||
|
||||
/* AF 1 */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */
|
||||
#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */
|
||||
|
||||
/* AF 2 */
|
||||
#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF2_USB ((uint8_t)0x02U) /*!< AF2: USB Alternate Function mapping */
|
||||
|
||||
/* AF 3 */
|
||||
#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */
|
||||
|
||||
/* AF 4 */
|
||||
#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */
|
||||
|
||||
/* AF 5 */
|
||||
#define GPIO_AF5_MCO ((uint8_t)0x05U) /*!< AF5: MCO Alternate Function mapping */
|
||||
#define GPIO_AF5_I2C1 ((uint8_t)0x05U) /*!< AF5: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF5_USB ((uint8_t)0x05U) /*!< AF5: USB Alternate Function mapping */
|
||||
|
||||
/* AF 6 */
|
||||
#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U)
|
||||
|
||||
#endif /* STM32F070x6 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIOEx_Get_Port_Index GPIOEx_Get Port Index
|
||||
* @{
|
||||
*/
|
||||
#if defined(GPIOD) && defined(GPIOE)
|
||||
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
|
||||
((__GPIOx__) == (GPIOB))? 1U :\
|
||||
((__GPIOx__) == (GPIOC))? 2U :\
|
||||
((__GPIOx__) == (GPIOD))? 3U :\
|
||||
((__GPIOx__) == (GPIOE))? 4U : 5U)
|
||||
#endif
|
||||
|
||||
#if defined(GPIOD) && !defined(GPIOE)
|
||||
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
|
||||
((__GPIOx__) == (GPIOB))? 1U :\
|
||||
((__GPIOx__) == (GPIOC))? 2U :\
|
||||
((__GPIOx__) == (GPIOD))? 3U : 5U)
|
||||
#endif
|
||||
|
||||
#if !defined(GPIOD) && defined(GPIOE)
|
||||
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
|
||||
((__GPIOx__) == (GPIOB))? 1U :\
|
||||
((__GPIOx__) == (GPIOC))? 2U :\
|
||||
((__GPIOx__) == (GPIOE))? 4U : 5U)
|
||||
#endif
|
||||
|
||||
#if !defined(GPIOD) && !defined(GPIOE)
|
||||
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
|
||||
((__GPIOx__) == (GPIOB))? 1U :\
|
||||
((__GPIOx__) == (GPIOC))? 2U : 5U)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0xx_HAL_GPIO_EX_H */
|
||||
|
||||
838
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h
Normal file
838
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h
Normal file
@@ -0,0 +1,838 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_i2c.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of I2C HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F0xx_HAL_I2C_H
|
||||
#define STM32F0xx_HAL_I2C_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup I2C_Exported_Types I2C Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
|
||||
* @brief I2C Configuration Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
|
||||
This parameter calculated by referring to I2C initialization section
|
||||
in Reference manual */
|
||||
|
||||
uint32_t OwnAddress1; /*!< Specifies the first device own address.
|
||||
This parameter can be a 7-bit or 10-bit address. */
|
||||
|
||||
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
|
||||
This parameter can be a value of @ref I2C_ADDRESSING_MODE */
|
||||
|
||||
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
|
||||
This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
|
||||
|
||||
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
|
||||
This parameter can be a 7-bit address. */
|
||||
|
||||
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing
|
||||
mode is selected.
|
||||
This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
|
||||
|
||||
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
|
||||
This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
|
||||
|
||||
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
|
||||
This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
|
||||
|
||||
} I2C_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_state_structure_definition HAL state structure definition
|
||||
* @brief HAL State structure definition
|
||||
* @note HAL I2C State value coding follow below described bitmap :\n
|
||||
* b7-b6 Error information\n
|
||||
* 00 : No Error\n
|
||||
* 01 : Abort (Abort user request on going)\n
|
||||
* 10 : Timeout\n
|
||||
* 11 : Error\n
|
||||
* b5 Peripheral initialization status\n
|
||||
* 0 : Reset (peripheral not initialized)\n
|
||||
* 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
|
||||
* b4 (not used)\n
|
||||
* x : Should be set to 0\n
|
||||
* b3\n
|
||||
* 0 : Ready or Busy (No Listen mode ongoing)\n
|
||||
* 1 : Listen (peripheral in Address Listen Mode)\n
|
||||
* b2 Intrinsic process state\n
|
||||
* 0 : Ready\n
|
||||
* 1 : Busy (peripheral busy with some configuration or internal operations)\n
|
||||
* b1 Rx state\n
|
||||
* 0 : Ready (no Rx operation ongoing)\n
|
||||
* 1 : Busy (Rx operation ongoing)\n
|
||||
* b0 Tx state\n
|
||||
* 0 : Ready (no Tx operation ongoing)\n
|
||||
* 1 : Busy (Tx operation ongoing)
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
|
||||
HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
|
||||
HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
|
||||
HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
|
||||
process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
|
||||
process is ongoing */
|
||||
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
|
||||
|
||||
} HAL_I2C_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_mode_structure_definition HAL mode structure definition
|
||||
* @brief HAL Mode structure definition
|
||||
* @note HAL I2C Mode value coding follow below described bitmap :\n
|
||||
* b7 (not used)\n
|
||||
* x : Should be set to 0\n
|
||||
* b6\n
|
||||
* 0 : None\n
|
||||
* 1 : Memory (HAL I2C communication is in Memory Mode)\n
|
||||
* b5\n
|
||||
* 0 : None\n
|
||||
* 1 : Slave (HAL I2C communication is in Slave Mode)\n
|
||||
* b4\n
|
||||
* 0 : None\n
|
||||
* 1 : Master (HAL I2C communication is in Master Mode)\n
|
||||
* b3-b2-b1-b0 (not used)\n
|
||||
* xxxx : Should be set to 0000
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
|
||||
HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
|
||||
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
|
||||
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
|
||||
|
||||
} HAL_I2C_ModeTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Error_Code_definition I2C Error Code definition
|
||||
* @brief I2C Error Code definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */
|
||||
#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */
|
||||
#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */
|
||||
#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */
|
||||
#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
|
||||
#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
|
||||
#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
|
||||
* @brief I2C handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct __I2C_HandleTypeDef
|
||||
{
|
||||
I2C_TypeDef *Instance; /*!< I2C registers base address */
|
||||
|
||||
I2C_InitTypeDef Init; /*!< I2C communication parameters */
|
||||
|
||||
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
|
||||
|
||||
uint16_t XferSize; /*!< I2C transfer size */
|
||||
|
||||
__IO uint16_t XferCount; /*!< I2C transfer counter */
|
||||
|
||||
__IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can
|
||||
be a value of @ref I2C_XFEROPTIONS */
|
||||
|
||||
__IO uint32_t PreviousState; /*!< I2C communication Previous state */
|
||||
|
||||
HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
|
||||
/*!< I2C transfer IRQ handler function pointer */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
|
||||
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< I2C locking object */
|
||||
|
||||
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
|
||||
|
||||
__IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< I2C Error code */
|
||||
|
||||
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
|
||||
|
||||
__IO uint32_t Devaddress; /*!< I2C Target device address */
|
||||
|
||||
__IO uint32_t Memaddress; /*!< I2C Target memory address */
|
||||
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Master Tx Transfer completed callback */
|
||||
void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Master Rx Transfer completed callback */
|
||||
void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Slave Tx Transfer completed callback */
|
||||
void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Slave Rx Transfer completed callback */
|
||||
void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Listen Complete callback */
|
||||
void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Memory Tx Transfer completed callback */
|
||||
void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Memory Rx Transfer completed callback */
|
||||
void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Error callback */
|
||||
void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Abort callback */
|
||||
|
||||
void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
|
||||
/*!< I2C Slave Address Match callback */
|
||||
|
||||
void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Msp DeInit callback */
|
||||
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
} I2C_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL I2C Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */
|
||||
HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */
|
||||
HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */
|
||||
HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */
|
||||
HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */
|
||||
HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */
|
||||
HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */
|
||||
HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */
|
||||
HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */
|
||||
|
||||
HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */
|
||||
HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */
|
||||
|
||||
} HAL_I2C_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL I2C Callback pointer definition
|
||||
*/
|
||||
typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c);
|
||||
/*!< pointer to an I2C callback function */
|
||||
typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection,
|
||||
uint16_t AddrMatchCode);
|
||||
/*!< pointer to an I2C Address Match callback function */
|
||||
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2C_Exported_Constants I2C Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
|
||||
#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
|
||||
#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
|
||||
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
|
||||
#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
|
||||
#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)
|
||||
|
||||
/* List of XferOptions in usage of :
|
||||
* 1- Restart condition in all use cases (direction change or not)
|
||||
*/
|
||||
#define I2C_OTHER_FRAME (0x000000AAU)
|
||||
#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)
|
||||
#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DUALADDRESS_DISABLE (0x00000000U)
|
||||
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
|
||||
* @{
|
||||
*/
|
||||
#define I2C_OA2_NOMASK ((uint8_t)0x00U)
|
||||
#define I2C_OA2_MASK01 ((uint8_t)0x01U)
|
||||
#define I2C_OA2_MASK02 ((uint8_t)0x02U)
|
||||
#define I2C_OA2_MASK03 ((uint8_t)0x03U)
|
||||
#define I2C_OA2_MASK04 ((uint8_t)0x04U)
|
||||
#define I2C_OA2_MASK05 ((uint8_t)0x05U)
|
||||
#define I2C_OA2_MASK06 ((uint8_t)0x06U)
|
||||
#define I2C_OA2_MASK07 ((uint8_t)0x07U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_GENERALCALL_DISABLE (0x00000000U)
|
||||
#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_NOSTRETCH_DISABLE (0x00000000U)
|
||||
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
|
||||
* @{
|
||||
*/
|
||||
#define I2C_MEMADD_SIZE_8BIT (0x00000001U)
|
||||
#define I2C_MEMADD_SIZE_16BIT (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DIRECTION_TRANSMIT (0x00000000U)
|
||||
#define I2C_DIRECTION_RECEIVE (0x00000001U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_RELOAD_MODE I2C_CR2_RELOAD
|
||||
#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
|
||||
#define I2C_SOFTEND_MODE (0x00000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_NO_STARTSTOP (0x00000000U)
|
||||
#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
|
||||
#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
|
||||
#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
|
||||
* @brief I2C Interrupt definition
|
||||
* Elements values convention: 0xXXXXXXXX
|
||||
* - XXXXXXXX : Interrupt control mask
|
||||
* @{
|
||||
*/
|
||||
#define I2C_IT_ERRI I2C_CR1_ERRIE
|
||||
#define I2C_IT_TCI I2C_CR1_TCIE
|
||||
#define I2C_IT_STOPI I2C_CR1_STOPIE
|
||||
#define I2C_IT_NACKI I2C_CR1_NACKIE
|
||||
#define I2C_IT_ADDRI I2C_CR1_ADDRIE
|
||||
#define I2C_IT_RXI I2C_CR1_RXIE
|
||||
#define I2C_IT_TXI I2C_CR1_TXIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Flag_definition I2C Flag definition
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FLAG_TXE I2C_ISR_TXE
|
||||
#define I2C_FLAG_TXIS I2C_ISR_TXIS
|
||||
#define I2C_FLAG_RXNE I2C_ISR_RXNE
|
||||
#define I2C_FLAG_ADDR I2C_ISR_ADDR
|
||||
#define I2C_FLAG_AF I2C_ISR_NACKF
|
||||
#define I2C_FLAG_STOPF I2C_ISR_STOPF
|
||||
#define I2C_FLAG_TC I2C_ISR_TC
|
||||
#define I2C_FLAG_TCR I2C_ISR_TCR
|
||||
#define I2C_FLAG_BERR I2C_ISR_BERR
|
||||
#define I2C_FLAG_ARLO I2C_ISR_ARLO
|
||||
#define I2C_FLAG_OVR I2C_ISR_OVR
|
||||
#define I2C_FLAG_PECERR I2C_ISR_PECERR
|
||||
#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
|
||||
#define I2C_FLAG_ALERT I2C_ISR_ALERT
|
||||
#define I2C_FLAG_BUSY I2C_ISR_BUSY
|
||||
#define I2C_FLAG_DIR I2C_ISR_DIR
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2C_Exported_Macros I2C Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset I2C handle state.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_I2C_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Enable the specified I2C interrupt.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref I2C_IT_RXI RX interrupt enable
|
||||
* @arg @ref I2C_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable the specified I2C interrupt.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref I2C_IT_RXI RX interrupt enable
|
||||
* @arg @ref I2C_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Check whether the specified I2C interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __INTERRUPT__ specifies the I2C interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref I2C_IT_RXI RX interrupt enable
|
||||
* @arg @ref I2C_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval The new state of __INTERRUPT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \
|
||||
(__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified I2C flag is set or not.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_FLAG_TXE Transmit data register empty
|
||||
* @arg @ref I2C_FLAG_TXIS Transmit interrupt status
|
||||
* @arg @ref I2C_FLAG_RXNE Receive data register not empty
|
||||
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
|
||||
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
|
||||
* @arg @ref I2C_FLAG_STOPF STOP detection flag
|
||||
* @arg @ref I2C_FLAG_TC Transfer complete (master mode)
|
||||
* @arg @ref I2C_FLAG_TCR Transfer complete reload
|
||||
* @arg @ref I2C_FLAG_BERR Bus error
|
||||
* @arg @ref I2C_FLAG_ARLO Arbitration lost
|
||||
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
|
||||
* @arg @ref I2C_FLAG_PECERR PEC error in reception
|
||||
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
|
||||
* @arg @ref I2C_FLAG_ALERT SMBus alert
|
||||
* @arg @ref I2C_FLAG_BUSY Bus busy
|
||||
* @arg @ref I2C_FLAG_DIR Transfer direction (slave mode)
|
||||
*
|
||||
* @retval The new state of __FLAG__ (SET or RESET).
|
||||
*/
|
||||
#define I2C_FLAG_MASK (0x0001FFFFU)
|
||||
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \
|
||||
(__FLAG__)) == (__FLAG__)) ? SET : RESET)
|
||||
|
||||
/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref I2C_FLAG_TXE Transmit data register empty
|
||||
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
|
||||
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
|
||||
* @arg @ref I2C_FLAG_STOPF STOP detection flag
|
||||
* @arg @ref I2C_FLAG_BERR Bus error
|
||||
* @arg @ref I2C_FLAG_ARLO Arbitration lost
|
||||
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
|
||||
* @arg @ref I2C_FLAG_PECERR PEC error in reception
|
||||
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
|
||||
* @arg @ref I2C_FLAG_ALERT SMBus alert
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \
|
||||
((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
|
||||
((__HANDLE__)->Instance->ICR = (__FLAG__)))
|
||||
|
||||
/** @brief Enable the specified I2C peripheral.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
|
||||
|
||||
/** @brief Disable the specified I2C peripheral.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
|
||||
|
||||
/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include I2C HAL Extended module */
|
||||
#include "stm32f0xx_hal_i2c_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup I2C_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions******************************/
|
||||
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
|
||||
pI2C_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions ****************************************************/
|
||||
/******* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
|
||||
uint32_t Timeout);
|
||||
|
||||
/******* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
|
||||
|
||||
/******* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
|
||||
* @{
|
||||
*/
|
||||
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
|
||||
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
|
||||
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State, Mode and Error functions *********************************/
|
||||
HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c);
|
||||
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c);
|
||||
uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Constants I2C Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Macro I2C Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
|
||||
((MODE) == I2C_ADDRESSINGMODE_10BIT))
|
||||
|
||||
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
|
||||
((ADDRESS) == I2C_DUALADDRESS_ENABLE))
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
|
||||
((MASK) == I2C_OA2_MASK01) || \
|
||||
((MASK) == I2C_OA2_MASK02) || \
|
||||
((MASK) == I2C_OA2_MASK03) || \
|
||||
((MASK) == I2C_OA2_MASK04) || \
|
||||
((MASK) == I2C_OA2_MASK05) || \
|
||||
((MASK) == I2C_OA2_MASK06) || \
|
||||
((MASK) == I2C_OA2_MASK07))
|
||||
|
||||
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
|
||||
((CALL) == I2C_GENERALCALL_ENABLE))
|
||||
|
||||
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
|
||||
((STRETCH) == I2C_NOSTRETCH_ENABLE))
|
||||
|
||||
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
|
||||
((SIZE) == I2C_MEMADD_SIZE_16BIT))
|
||||
|
||||
#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
|
||||
((MODE) == I2C_AUTOEND_MODE) || \
|
||||
((MODE) == I2C_SOFTEND_MODE))
|
||||
|
||||
#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
|
||||
((REQUEST) == I2C_GENERATE_START_READ) || \
|
||||
((REQUEST) == I2C_GENERATE_START_WRITE) || \
|
||||
((REQUEST) == I2C_NO_STARTSTOP))
|
||||
|
||||
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
|
||||
((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
|
||||
((REQUEST) == I2C_NEXT_FRAME) || \
|
||||
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
|
||||
((REQUEST) == I2C_LAST_FRAME) || \
|
||||
((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \
|
||||
IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
|
||||
|
||||
#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \
|
||||
((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
|
||||
|
||||
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
|
||||
(uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
|
||||
I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
|
||||
I2C_CR2_RD_WRN)))
|
||||
|
||||
#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \
|
||||
>> 16U))
|
||||
#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \
|
||||
>> 16U))
|
||||
#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
|
||||
#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
|
||||
#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
|
||||
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
|
||||
|
||||
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \
|
||||
(uint16_t)(0xFF00U))) >> 8U)))
|
||||
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
|
||||
|
||||
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
|
||||
(I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
|
||||
(~I2C_CR2_RD_WRN)) : \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
|
||||
(I2C_CR2_ADD10) | (I2C_CR2_START) | \
|
||||
(I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)))
|
||||
|
||||
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
|
||||
((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
|
||||
#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Functions ---------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Functions I2C Private Functions
|
||||
* @{
|
||||
*/
|
||||
/* Private functions are defined in stm32f0xx_hal_i2c.c file */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32F0xx_HAL_I2C_H */
|
||||
190
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h
Normal file
190
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h
Normal file
@@ -0,0 +1,190 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_i2c_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of I2C HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F0xx_HAL_I2C_EX_H
|
||||
#define STM32F0xx_HAL_I2C_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
|
||||
* @{
|
||||
*/
|
||||
#define I2C_ANALOGFILTER_ENABLE 0x00000000U
|
||||
#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */
|
||||
#if defined(SYSCFG_CFGR1_I2C_FMP_PA9)
|
||||
#define I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast Mode Plus on PA9 */
|
||||
#define I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast Mode Plus on PA10 */
|
||||
#else
|
||||
#define I2C_FASTMODEPLUS_PA9 (uint32_t)(0x00000001U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PA9 not supported */
|
||||
#define I2C_FASTMODEPLUS_PA10 (uint32_t)(0x00000002U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PA10 not supported */
|
||||
#endif /* SYSCFG_CFGR1_I2C_FMP_PA9 */
|
||||
#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< Enable Fast Mode Plus on PB6 */
|
||||
#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< Enable Fast Mode Plus on PB7 */
|
||||
#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< Enable Fast Mode Plus on PB8 */
|
||||
#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< Enable Fast Mode Plus on PB9 */
|
||||
#if defined(SYSCFG_CFGR1_I2C_FMP_I2C1)
|
||||
#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /*!< Enable Fast Mode Plus on I2C1 pins */
|
||||
#else
|
||||
#define I2C_FASTMODEPLUS_I2C1 (uint32_t)(0x00000100U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C1 not supported */
|
||||
#endif /* SYSCFG_CFGR1_I2C_FMP_I2C1 */
|
||||
#if defined(SYSCFG_CFGR1_I2C_FMP_I2C2)
|
||||
#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C_FMP_I2C2 /*!< Enable Fast Mode Plus on I2C2 pins */
|
||||
#else
|
||||
#define I2C_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported */
|
||||
#endif /* SYSCFG_CFGR1_I2C_FMP_I2C2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions
|
||||
* @brief Extended features functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c,
|
||||
uint32_t AnalogFilter);
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c,
|
||||
uint32_t DigitalFilter);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#if defined(I2C_CR1_WUPEN)
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* I2C_CR1_WUPEN */
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
|
||||
* @{
|
||||
*/
|
||||
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
|
||||
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
|
||||
((FILTER) == I2C_ANALOGFILTER_DISABLE))
|
||||
|
||||
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
|
||||
|
||||
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \
|
||||
((((__CONFIG__) & (I2C_FASTMODEPLUS_PA9)) == I2C_FASTMODEPLUS_PA9) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_PA10)) == I2C_FASTMODEPLUS_PA10) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2)))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Functions ---------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
|
||||
* @{
|
||||
*/
|
||||
/* Private functions are defined in stm32f0xx_hal_i2c_ex.c file */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F0xx_HAL_I2C_EX_H */
|
||||
554
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2s.h
Normal file
554
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2s.h
Normal file
@@ -0,0 +1,554 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_i2s.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of I2S HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F0xx_HAL_I2S_H
|
||||
#define STM32F0xx_HAL_I2S_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
#if defined(SPI_I2S_SUPPORT)
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2S
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup I2S_Exported_Types I2S Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief I2S Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Mode; /*!< Specifies the I2S operating mode.
|
||||
This parameter can be a value of @ref I2S_Mode */
|
||||
|
||||
uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Standard */
|
||||
|
||||
uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Data_Format */
|
||||
|
||||
uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
|
||||
This parameter can be a value of @ref I2S_MCLK_Output */
|
||||
|
||||
uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Audio_Frequency */
|
||||
|
||||
uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
|
||||
This parameter can be a value of @ref I2S_Clock_Polarity */
|
||||
} I2S_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */
|
||||
HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */
|
||||
HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */
|
||||
HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
|
||||
HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
|
||||
HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */
|
||||
HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */
|
||||
} HAL_I2S_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief I2S handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __I2S_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
{
|
||||
SPI_TypeDef *Instance; /*!< I2S registers base address */
|
||||
|
||||
I2S_InitTypeDef Init; /*!< I2S communication parameters */
|
||||
|
||||
uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
|
||||
|
||||
__IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
|
||||
|
||||
__IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
|
||||
|
||||
uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
|
||||
|
||||
__IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
|
||||
|
||||
__IO uint16_t RxXferCount; /*!< I2S Rx transfer counter
|
||||
(This field is initialized at the
|
||||
same value as transfer size at the
|
||||
beginning of the transfer and
|
||||
decremented when a sample is received
|
||||
NbSamplesReceived = RxBufferSize-RxBufferCount) */
|
||||
DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
|
||||
|
||||
__IO HAL_LockTypeDef Lock; /*!< I2S locking object */
|
||||
|
||||
__IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< I2S Error code
|
||||
This parameter can be a value of @ref I2S_Error */
|
||||
|
||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
|
||||
void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Completed callback */
|
||||
void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Completed callback */
|
||||
void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Half Completed callback */
|
||||
void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Half Completed callback */
|
||||
void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Error callback */
|
||||
void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp DeInit callback */
|
||||
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
} I2S_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
|
||||
/**
|
||||
* @brief HAL I2S Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2S_TX_COMPLETE_CB_ID = 0x00U, /*!< I2S Tx Completed callback ID */
|
||||
HAL_I2S_RX_COMPLETE_CB_ID = 0x01U, /*!< I2S Rx Completed callback ID */
|
||||
HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< I2S Tx Half Completed callback ID */
|
||||
HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< I2S Rx Half Completed callback ID */
|
||||
HAL_I2S_ERROR_CB_ID = 0x06U, /*!< I2S Error callback ID */
|
||||
HAL_I2S_MSPINIT_CB_ID = 0x07U, /*!< I2S Msp Init callback ID */
|
||||
HAL_I2S_MSPDEINIT_CB_ID = 0x08U /*!< I2S Msp DeInit callback ID */
|
||||
|
||||
} HAL_I2S_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL I2S Callback pointer definition
|
||||
*/
|
||||
typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */
|
||||
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup I2S_Exported_Constants I2S Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup I2S_Error I2S Error
|
||||
* @{
|
||||
*/
|
||||
#define HAL_I2S_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_I2S_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */
|
||||
#define HAL_I2S_ERROR_OVR (0x00000002U) /*!< OVR error */
|
||||
#define HAL_I2S_ERROR_UDR (0x00000004U) /*!< UDR error */
|
||||
#define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */
|
||||
#define HAL_I2S_ERROR_PRESCALER (0x00000010U) /*!< Prescaler Calculation error */
|
||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
|
||||
#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
#define HAL_I2S_ERROR_BUSY_LINE_RX (0x00000040U) /*!< Busy Rx Line error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Mode I2S Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2S_MODE_SLAVE_TX (0x00000000U)
|
||||
#define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
|
||||
#define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
|
||||
#define I2S_MODE_MASTER_RX ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Standard I2S Standard
|
||||
* @{
|
||||
*/
|
||||
#define I2S_STANDARD_PHILIPS (0x00000000U)
|
||||
#define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
|
||||
#define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
|
||||
#define I2S_STANDARD_PCM_SHORT ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1))
|
||||
#define I2S_STANDARD_PCM_LONG ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Data_Format I2S Data Format
|
||||
* @{
|
||||
*/
|
||||
#define I2S_DATAFORMAT_16B (0x00000000U)
|
||||
#define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
|
||||
#define I2S_DATAFORMAT_24B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
|
||||
#define I2S_DATAFORMAT_32B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_MCLK_Output I2S MCLK Output
|
||||
* @{
|
||||
*/
|
||||
#define I2S_MCLKOUTPUT_ENABLE (SPI_I2SPR_MCKOE)
|
||||
#define I2S_MCLKOUTPUT_DISABLE (0x00000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
|
||||
* @{
|
||||
*/
|
||||
#define I2S_AUDIOFREQ_192K (192000U)
|
||||
#define I2S_AUDIOFREQ_96K (96000U)
|
||||
#define I2S_AUDIOFREQ_48K (48000U)
|
||||
#define I2S_AUDIOFREQ_44K (44100U)
|
||||
#define I2S_AUDIOFREQ_32K (32000U)
|
||||
#define I2S_AUDIOFREQ_22K (22050U)
|
||||
#define I2S_AUDIOFREQ_16K (16000U)
|
||||
#define I2S_AUDIOFREQ_11K (11025U)
|
||||
#define I2S_AUDIOFREQ_8K (8000U)
|
||||
#define I2S_AUDIOFREQ_DEFAULT (2U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
|
||||
* @{
|
||||
*/
|
||||
#define I2S_CPOL_LOW (0x00000000U)
|
||||
#define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
|
||||
* @{
|
||||
*/
|
||||
#define I2S_IT_TXE SPI_CR2_TXEIE
|
||||
#define I2S_IT_RXNE SPI_CR2_RXNEIE
|
||||
#define I2S_IT_ERR SPI_CR2_ERRIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Flags_Definition I2S Flags Definition
|
||||
* @{
|
||||
*/
|
||||
#define I2S_FLAG_TXE SPI_SR_TXE
|
||||
#define I2S_FLAG_RXNE SPI_SR_RXNE
|
||||
|
||||
#define I2S_FLAG_UDR SPI_SR_UDR
|
||||
#define I2S_FLAG_OVR SPI_SR_OVR
|
||||
#define I2S_FLAG_FRE SPI_SR_FRE
|
||||
|
||||
#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
|
||||
#define I2S_FLAG_BSY SPI_SR_BSY
|
||||
|
||||
#define I2S_FLAG_MASK (SPI_SR_RXNE\
|
||||
| SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup I2S_Exported_macros I2S Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset I2S handle state
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
|
||||
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_I2S_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Enable the specified SPI peripheral (in I2S mode).
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
|
||||
|
||||
/** @brief Disable the specified SPI peripheral (in I2S mode).
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
|
||||
|
||||
/** @brief Enable the specified I2S interrupts.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg I2S_IT_ERR: Error interrupt enable
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
|
||||
|
||||
/** @brief Disable the specified I2S interrupts.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg I2S_IT_ERR: Error interrupt enable
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
|
||||
|
||||
/** @brief Checks if the specified I2S interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
|
||||
* @param __INTERRUPT__ specifies the I2S interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg I2S_IT_ERR: Error interrupt enable
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Checks whether the specified I2S flag is set or not.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
|
||||
* @arg I2S_FLAG_TXE: Transmit buffer empty flag
|
||||
* @arg I2S_FLAG_UDR: Underrun flag
|
||||
* @arg I2S_FLAG_OVR: Overrun flag
|
||||
* @arg I2S_FLAG_FRE: Frame error flag
|
||||
* @arg I2S_FLAG_CHSIDE: Channel Side flag
|
||||
* @arg I2S_FLAG_BSY: Busy flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clears the I2S OVR pending flag.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
|
||||
__IO uint32_t tmpreg_ovr = 0x00U; \
|
||||
tmpreg_ovr = (__HANDLE__)->Instance->DR; \
|
||||
tmpreg_ovr = (__HANDLE__)->Instance->SR; \
|
||||
UNUSED(tmpreg_ovr); \
|
||||
}while(0U)
|
||||
/** @brief Clears the I2S UDR pending flag.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\
|
||||
__IO uint32_t tmpreg_udr = 0x00U;\
|
||||
tmpreg_udr = ((__HANDLE__)->Instance->SR);\
|
||||
UNUSED(tmpreg_udr); \
|
||||
}while(0U)
|
||||
/** @brief Flush the I2S DR Register.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_FLUSH_RX_DR(__HANDLE__) do{\
|
||||
__IO uint32_t tmpreg_dr = 0x00U;\
|
||||
tmpreg_dr = ((__HANDLE__)->Instance->DR);\
|
||||
UNUSED(tmpreg_dr); \
|
||||
}while(0U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup I2S_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2S_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
|
||||
HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
|
||||
HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
|
||||
pI2S_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2S_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ***************************************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
||||
void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
|
||||
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
|
||||
HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
|
||||
HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
|
||||
|
||||
/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
|
||||
void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2S_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control and State functions ************************************/
|
||||
HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
|
||||
uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup I2S_Private_Macros I2S Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Check whether the specified SPI flag is set or not.
|
||||
* @param __SR__ copy of I2S SR register.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
|
||||
* @arg I2S_FLAG_TXE: Transmit buffer empty flag
|
||||
* @arg I2S_FLAG_UDR: Underrun error flag
|
||||
* @arg I2S_FLAG_OVR: Overrun flag
|
||||
* @arg I2S_FLAG_CHSIDE: Channel side flag
|
||||
* @arg I2S_FLAG_BSY: Busy flag
|
||||
* @retval SET or RESET.
|
||||
*/
|
||||
#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__)\
|
||||
& ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified SPI Interrupt is set or not.
|
||||
* @param __CR2__ copy of I2S CR2 register.
|
||||
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg I2S_IT_ERR: Error interrupt enable
|
||||
* @retval SET or RESET.
|
||||
*/
|
||||
#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__)\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Checks if I2S Mode parameter is in allowed range.
|
||||
* @param __MODE__ specifies the I2S Mode.
|
||||
* This parameter can be a value of @ref I2S_Mode
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \
|
||||
((__MODE__) == I2S_MODE_SLAVE_RX) || \
|
||||
((__MODE__) == I2S_MODE_MASTER_TX) || \
|
||||
((__MODE__) == I2S_MODE_MASTER_RX))
|
||||
|
||||
#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \
|
||||
((__STANDARD__) == I2S_STANDARD_MSB) || \
|
||||
((__STANDARD__) == I2S_STANDARD_LSB) || \
|
||||
((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \
|
||||
((__STANDARD__) == I2S_STANDARD_PCM_LONG))
|
||||
|
||||
#define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) || \
|
||||
((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \
|
||||
((__FORMAT__) == I2S_DATAFORMAT_24B) || \
|
||||
((__FORMAT__) == I2S_DATAFORMAT_32B))
|
||||
|
||||
#define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \
|
||||
((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))
|
||||
|
||||
#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \
|
||||
((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
|
||||
((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
|
||||
|
||||
/** @brief Checks if I2S Serial clock steady state parameter is in allowed range.
|
||||
* @param __CPOL__ specifies the I2S serial clock steady state.
|
||||
* This parameter can be a value of @ref I2S_Clock_Polarity
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \
|
||||
((__CPOL__) == I2S_CPOL_HIGH))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* SPI_I2S_SUPPORT */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F0xx_HAL_I2S_H */
|
||||
|
||||
854
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_irda.h
Normal file
854
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_irda.h
Normal file
@@ -0,0 +1,854 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_irda.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of IRDA HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F0xx_HAL_IRDA_H
|
||||
#define STM32F0xx_HAL_IRDA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(USART_IRDA_SUPPORT)
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IRDA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Exported_Types IRDA Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief IRDA Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate.
|
||||
The baud rate register is computed using the following formula:
|
||||
Baud Rate Register = ((usart_ker_clk) / ((hirda->Init.BaudRate)))
|
||||
where usart_ker_clk is the IRDA input clock */
|
||||
|
||||
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter can be a value of @ref IRDAEx_Word_Length */
|
||||
|
||||
uint32_t Parity; /*!< Specifies the parity mode.
|
||||
This parameter can be a value of @ref IRDA_Parity
|
||||
@note When parity is enabled, the computed parity is inserted
|
||||
at the MSB position of the transmitted data (9th bit when
|
||||
the word length is set to 9 data bits; 8th bit when the
|
||||
word length is set to 8 data bits). */
|
||||
|
||||
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
|
||||
This parameter can be a value of @ref IRDA_Transfer_Mode */
|
||||
|
||||
uint8_t Prescaler; /*!< Specifies the Prescaler value for dividing the UART/USART source clock
|
||||
to achieve low-power frequency.
|
||||
@note Prescaler value 0 is forbidden */
|
||||
|
||||
uint16_t PowerMode; /*!< Specifies the IRDA power mode.
|
||||
This parameter can be a value of @ref IRDA_Low_Power */
|
||||
|
||||
} IRDA_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL IRDA State definition
|
||||
* @note HAL IRDA State value is a combination of 2 different substates:
|
||||
* gState and RxState (see @ref IRDA_State_Definition).
|
||||
* - gState contains IRDA state information related to global Handle management
|
||||
* and also information related to Tx operations.
|
||||
* gState value coding follow below described bitmap :
|
||||
* b7-b6 Error information
|
||||
* 00 : No Error
|
||||
* 01 : (Not Used)
|
||||
* 10 : Timeout
|
||||
* 11 : Error
|
||||
* b5 Peripheral initialization status
|
||||
* 0 : Reset (Peripheral not initialized)
|
||||
* 1 : Init done (Peripheral initialized. HAL IRDA Init function already called)
|
||||
* b4-b3 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b2 Intrinsic process state
|
||||
* 0 : Ready
|
||||
* 1 : Busy (Peripheral busy with some configuration or internal operations)
|
||||
* b1 (not used)
|
||||
* x : Should be set to 0
|
||||
* b0 Tx state
|
||||
* 0 : Ready (no Tx operation ongoing)
|
||||
* 1 : Busy (Tx operation ongoing)
|
||||
* - RxState contains information related to Rx operations.
|
||||
* RxState value coding follow below described bitmap :
|
||||
* b7-b6 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b5 Peripheral initialization status
|
||||
* 0 : Reset (Peripheral not initialized)
|
||||
* 1 : Init done (Peripheral initialized)
|
||||
* b4-b2 (not used)
|
||||
* xxx : Should be set to 000
|
||||
* b1 Rx state
|
||||
* 0 : Ready (no Rx operation ongoing)
|
||||
* 1 : Busy (Rx operation ongoing)
|
||||
* b0 (not used)
|
||||
* x : Should be set to 0.
|
||||
*/
|
||||
typedef uint32_t HAL_IRDA_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IRDA clock sources definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
IRDA_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
|
||||
IRDA_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
|
||||
IRDA_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
|
||||
IRDA_CLOCKSOURCE_LSE = 0x10U, /*!< LSE clock source */
|
||||
IRDA_CLOCKSOURCE_UNDEFINED = 0x20U /*!< Undefined clock source */
|
||||
} IRDA_ClockSourceTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IRDA handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __IRDA_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
{
|
||||
USART_TypeDef *Instance; /*!< USART registers base address */
|
||||
|
||||
IRDA_InitTypeDef Init; /*!< IRDA communication parameters */
|
||||
|
||||
const uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */
|
||||
|
||||
uint16_t TxXferSize; /*!< IRDA Tx Transfer size */
|
||||
|
||||
__IO uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */
|
||||
|
||||
uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */
|
||||
|
||||
uint16_t RxXferSize; /*!< IRDA Rx Transfer size */
|
||||
|
||||
__IO uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */
|
||||
|
||||
uint16_t Mask; /*!< USART RX RDR register mask */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
|
||||
__IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management
|
||||
and also related to Tx operations.
|
||||
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
|
||||
|
||||
__IO HAL_IRDA_StateTypeDef RxState; /*!< IRDA state information related to Rx operations.
|
||||
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< IRDA Error code */
|
||||
|
||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
||||
void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Half Complete Callback */
|
||||
|
||||
void (* TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Complete Callback */
|
||||
|
||||
void (* RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Half Complete Callback */
|
||||
|
||||
void (* RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Complete Callback */
|
||||
|
||||
void (* ErrorCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Error Callback */
|
||||
|
||||
void (* AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Complete Callback */
|
||||
|
||||
void (* AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Transmit Complete Callback */
|
||||
|
||||
void (* AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Receive Complete Callback */
|
||||
|
||||
|
||||
void (* MspInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp Init callback */
|
||||
|
||||
void (* MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp DeInit callback */
|
||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
|
||||
} IRDA_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL IRDA Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_IRDA_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< IRDA Tx Half Complete Callback ID */
|
||||
HAL_IRDA_TX_COMPLETE_CB_ID = 0x01U, /*!< IRDA Tx Complete Callback ID */
|
||||
HAL_IRDA_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< IRDA Rx Half Complete Callback ID */
|
||||
HAL_IRDA_RX_COMPLETE_CB_ID = 0x03U, /*!< IRDA Rx Complete Callback ID */
|
||||
HAL_IRDA_ERROR_CB_ID = 0x04U, /*!< IRDA Error Callback ID */
|
||||
HAL_IRDA_ABORT_COMPLETE_CB_ID = 0x05U, /*!< IRDA Abort Complete Callback ID */
|
||||
HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< IRDA Abort Transmit Complete Callback ID */
|
||||
HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< IRDA Abort Receive Complete Callback ID */
|
||||
|
||||
HAL_IRDA_MSPINIT_CB_ID = 0x08U, /*!< IRDA MspInit callback ID */
|
||||
HAL_IRDA_MSPDEINIT_CB_ID = 0x09U /*!< IRDA MspDeInit callback ID */
|
||||
|
||||
} HAL_IRDA_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL IRDA Callback pointer definition
|
||||
*/
|
||||
typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer to an IRDA callback function */
|
||||
|
||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Exported_Constants IRDA Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_State_Definition IRDA State Code Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_IRDA_STATE_RESET 0x00000000U /*!< Peripheral is not initialized
|
||||
Value is allowed for gState and RxState */
|
||||
#define HAL_IRDA_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use
|
||||
Value is allowed for gState and RxState */
|
||||
#define HAL_IRDA_STATE_BUSY 0x00000024U /*!< An internal process is ongoing
|
||||
Value is allowed for gState only */
|
||||
#define HAL_IRDA_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing
|
||||
Value is allowed for gState only */
|
||||
#define HAL_IRDA_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing
|
||||
Value is allowed for RxState only */
|
||||
#define HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing
|
||||
Not to be used for neither gState nor RxState.
|
||||
Value is result of combination (Or) between
|
||||
gState and RxState values */
|
||||
#define HAL_IRDA_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
|
||||
Value is allowed for gState only */
|
||||
#define HAL_IRDA_STATE_ERROR 0x000000E0U /*!< Error
|
||||
Value is allowed for gState only */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Error_Definition IRDA Error Code Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_IRDA_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_IRDA_ERROR_PE (0x00000001U) /*!< Parity error */
|
||||
#define HAL_IRDA_ERROR_NE (0x00000002U) /*!< Noise error */
|
||||
#define HAL_IRDA_ERROR_FE (0x00000004U) /*!< frame error */
|
||||
#define HAL_IRDA_ERROR_ORE (0x00000008U) /*!< Overrun error */
|
||||
#define HAL_IRDA_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_IRDA_ERROR_BUSY (0x00000020U) /*!< Busy Error */
|
||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_IRDA_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Parity IRDA Parity
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_PARITY_NONE 0x00000000U /*!< No parity */
|
||||
#define IRDA_PARITY_EVEN USART_CR1_PCE /*!< Even parity */
|
||||
#define IRDA_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_MODE_RX USART_CR1_RE /*!< RX mode */
|
||||
#define IRDA_MODE_TX USART_CR1_TE /*!< TX mode */
|
||||
#define IRDA_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Low_Power IRDA Low Power
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_POWERMODE_NORMAL 0x00000000U /*!< IRDA normal power mode */
|
||||
#define IRDA_POWERMODE_LOWPOWER USART_CR3_IRLP /*!< IRDA low power mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_State IRDA State
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_STATE_DISABLE 0x00000000U /*!< IRDA disabled */
|
||||
#define IRDA_STATE_ENABLE USART_CR1_UE /*!< IRDA enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Mode IRDA Mode
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_MODE_DISABLE 0x00000000U /*!< Associated UART disabled in IRDA mode */
|
||||
#define IRDA_MODE_ENABLE USART_CR3_IREN /*!< Associated UART enabled in IRDA mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_One_Bit IRDA One Bit Sampling
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disabled */
|
||||
#define IRDA_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_DMA_Tx IRDA DMA Tx
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_DMA_TX_DISABLE 0x00000000U /*!< IRDA DMA TX disabled */
|
||||
#define IRDA_DMA_TX_ENABLE USART_CR3_DMAT /*!< IRDA DMA TX enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_DMA_Rx IRDA DMA Rx
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_DMA_RX_DISABLE 0x00000000U /*!< IRDA DMA RX disabled */
|
||||
#define IRDA_DMA_RX_ENABLE USART_CR3_DMAR /*!< IRDA DMA RX enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Request_Parameters IRDA Request Parameters
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */
|
||||
#define IRDA_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */
|
||||
#define IRDA_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Flags IRDA Flags
|
||||
* Elements values convention: 0xXXXX
|
||||
* - 0xXXXX : Flag mask in the ISR register
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_FLAG_REACK USART_ISR_REACK /*!< IRDA receive enable acknowledge flag */
|
||||
#define IRDA_FLAG_TEACK USART_ISR_TEACK /*!< IRDA transmit enable acknowledge flag */
|
||||
#define IRDA_FLAG_BUSY USART_ISR_BUSY /*!< IRDA busy flag */
|
||||
#define IRDA_FLAG_ABRF USART_ISR_ABRF /*!< IRDA auto Baud rate flag */
|
||||
#define IRDA_FLAG_ABRE USART_ISR_ABRE /*!< IRDA auto Baud rate error */
|
||||
#define IRDA_FLAG_TXE USART_ISR_TXE /*!< IRDA transmit data register empty */
|
||||
#define IRDA_FLAG_TC USART_ISR_TC /*!< IRDA transmission complete */
|
||||
#define IRDA_FLAG_RXNE USART_ISR_RXNE /*!< IRDA read data register not empty */
|
||||
#define IRDA_FLAG_ORE USART_ISR_ORE /*!< IRDA overrun error */
|
||||
#define IRDA_FLAG_NE USART_ISR_NE /*!< IRDA noise error */
|
||||
#define IRDA_FLAG_FE USART_ISR_FE /*!< IRDA frame error */
|
||||
#define IRDA_FLAG_PE USART_ISR_PE /*!< IRDA parity error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition
|
||||
* Elements values convention: 0000ZZZZ0XXYYYYYb
|
||||
* - YYYYY : Interrupt source position in the XX register (5bits)
|
||||
* - XX : Interrupt source register (2bits)
|
||||
* - 01: CR1 register
|
||||
* - 10: CR2 register
|
||||
* - 11: CR3 register
|
||||
* - ZZZZ : Flag position in the ISR register(4bits)
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_IT_PE 0x0028U /*!< IRDA Parity error interruption */
|
||||
#define IRDA_IT_TXE 0x0727U /*!< IRDA Transmit data register empty interruption */
|
||||
#define IRDA_IT_TC 0x0626U /*!< IRDA Transmission complete interruption */
|
||||
#define IRDA_IT_RXNE 0x0525U /*!< IRDA Read data register not empty interruption */
|
||||
#define IRDA_IT_IDLE 0x0424U /*!< IRDA Idle interruption */
|
||||
|
||||
/* Elements values convention: 000000000XXYYYYYb
|
||||
- YYYYY : Interrupt source position in the XX register (5bits)
|
||||
- XX : Interrupt source register (2bits)
|
||||
- 01: CR1 register
|
||||
- 10: CR2 register
|
||||
- 11: CR3 register */
|
||||
#define IRDA_IT_ERR 0x0060U /*!< IRDA Error interruption */
|
||||
|
||||
/* Elements values convention: 0000ZZZZ00000000b
|
||||
- ZZZZ : Flag position in the ISR register(4bits) */
|
||||
#define IRDA_IT_ORE 0x0300U /*!< IRDA Overrun error interruption */
|
||||
#define IRDA_IT_NE 0x0200U /*!< IRDA Noise error interruption */
|
||||
#define IRDA_IT_FE 0x0100U /*!< IRDA Frame error interruption */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
|
||||
#define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
|
||||
#define IRDA_CLEAR_NEF USART_ICR_NCF /*!< Noise Error detected Clear Flag */
|
||||
#define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
|
||||
#define IRDA_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
|
||||
#define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_IT_MASK 0x001FU /*!< IRDA Interruptions flags mask */
|
||||
#define IRDA_CR_MASK 0x00E0U /*!< IRDA control register mask */
|
||||
#define IRDA_CR_POS 5U /*!< IRDA control register position */
|
||||
#define IRDA_ISR_MASK 0x1F00U /*!< IRDA ISR register mask */
|
||||
#define IRDA_ISR_POS 8U /*!< IRDA ISR register position */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset IRDA handle state.
|
||||
* @param __HANDLE__ IRDA handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
|
||||
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
|
||||
(__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0U)
|
||||
#else
|
||||
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
|
||||
(__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
|
||||
} while(0U)
|
||||
#endif /*USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Flush the IRDA DR register.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \
|
||||
do{ \
|
||||
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
|
||||
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
|
||||
} while(0U)
|
||||
|
||||
/** @brief Clear the specified IRDA pending flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref IRDA_CLEAR_PEF
|
||||
* @arg @ref IRDA_CLEAR_FEF
|
||||
* @arg @ref IRDA_CLEAR_NEF
|
||||
* @arg @ref IRDA_CLEAR_OREF
|
||||
* @arg @ref IRDA_CLEAR_TCF
|
||||
* @arg @ref IRDA_CLEAR_IDLEF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
|
||||
|
||||
/** @brief Clear the IRDA PE pending flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
|
||||
|
||||
|
||||
/** @brief Clear the IRDA FE pending flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
|
||||
|
||||
/** @brief Clear the IRDA NE pending flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
|
||||
|
||||
/** @brief Clear the IRDA ORE pending flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
|
||||
|
||||
/** @brief Clear the IRDA IDLE pending flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
|
||||
|
||||
/** @brief Check whether the specified IRDA flag is set or not.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag
|
||||
* @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag
|
||||
* @arg @ref IRDA_FLAG_BUSY Busy flag
|
||||
* @arg @ref IRDA_FLAG_ABRF Auto Baud rate detection flag
|
||||
* @arg @ref IRDA_FLAG_ABRE Auto Baud rate detection error flag
|
||||
* @arg @ref IRDA_FLAG_TXE Transmit data register empty flag
|
||||
* @arg @ref IRDA_FLAG_TC Transmission Complete flag
|
||||
* @arg @ref IRDA_FLAG_RXNE Receive data register not empty flag
|
||||
* @arg @ref IRDA_FLAG_ORE OverRun Error flag
|
||||
* @arg @ref IRDA_FLAG_NE Noise Error flag
|
||||
* @arg @ref IRDA_FLAG_FE Framing Error flag
|
||||
* @arg @ref IRDA_FLAG_PE Parity Error flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
|
||||
/** @brief Enable the specified IRDA interrupt.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __INTERRUPT__ specifies the IRDA interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
|
||||
* @arg @ref IRDA_IT_TC Transmission complete interrupt
|
||||
* @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
|
||||
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
|
||||
* @arg @ref IRDA_IT_PE Parity Error interrupt
|
||||
* @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
|
||||
((__HANDLE__)->Instance->CR1 |= (1U << \
|
||||
((__INTERRUPT__) & IRDA_IT_MASK))):\
|
||||
((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
|
||||
((__HANDLE__)->Instance->CR2 |= (1U << \
|
||||
((__INTERRUPT__) & IRDA_IT_MASK))):\
|
||||
((__HANDLE__)->Instance->CR3 |= (1U << \
|
||||
((__INTERRUPT__) & IRDA_IT_MASK))))
|
||||
|
||||
/** @brief Disable the specified IRDA interrupt.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __INTERRUPT__ specifies the IRDA interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
|
||||
* @arg @ref IRDA_IT_TC Transmission complete interrupt
|
||||
* @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
|
||||
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
|
||||
* @arg @ref IRDA_IT_PE Parity Error interrupt
|
||||
* @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
|
||||
((__HANDLE__)->Instance->CR1 &= ~ (1U << \
|
||||
((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
|
||||
((__HANDLE__)->Instance->CR2 &= ~ (1U << \
|
||||
((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 &= ~ (1U << \
|
||||
((__INTERRUPT__) & IRDA_IT_MASK))))
|
||||
|
||||
/** @brief Check whether the specified IRDA interrupt has occurred or not.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __INTERRUPT__ specifies the IRDA interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
|
||||
* @arg @ref IRDA_IT_TC Transmission complete interrupt
|
||||
* @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
|
||||
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
|
||||
* @arg @ref IRDA_IT_ORE OverRun Error interrupt
|
||||
* @arg @ref IRDA_IT_NE Noise Error interrupt
|
||||
* @arg @ref IRDA_IT_FE Framing Error interrupt
|
||||
* @arg @ref IRDA_IT_PE Parity Error interrupt
|
||||
* @retval The new state of __IT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) \
|
||||
((((__HANDLE__)->Instance->ISR& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>>IRDA_ISR_POS))) != 0U) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified IRDA interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __INTERRUPT__ specifies the IRDA interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
|
||||
* @arg @ref IRDA_IT_TC Transmission complete interrupt
|
||||
* @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
|
||||
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
|
||||
* @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt
|
||||
* @arg @ref IRDA_IT_PE Parity Error interrupt
|
||||
* @retval The new state of __IT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
|
||||
((((((((__INTERRUPT__) & IRDA_CR_MASK) >>IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 :(((((__INTERRUPT__) \
|
||||
& IRDA_CR_MASK) >> IRDA_CR_POS)== 0x02U)? (__HANDLE__)->Instance->CR2 :(__HANDLE__)->Instance->CR3)) \
|
||||
& (0x01U <<(((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
|
||||
|
||||
/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
|
||||
* to clear the corresponding interrupt
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag
|
||||
* @arg @ref IRDA_CLEAR_FEF Framing Error Clear Flag
|
||||
* @arg @ref IRDA_CLEAR_NEF Noise detected Clear Flag
|
||||
* @arg @ref IRDA_CLEAR_OREF OverRun Error Clear Flag
|
||||
* @arg @ref IRDA_CLEAR_TCF Transmission Complete Clear Flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
|
||||
|
||||
|
||||
/** @brief Set a specific IRDA request flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __REQ__ specifies the request flag to set
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
|
||||
* @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
|
||||
* @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
|
||||
|
||||
/** @brief Enable the IRDA one bit sample method.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
|
||||
|
||||
/** @brief Disable the IRDA one bit sample method.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
|
||||
&= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
|
||||
|
||||
/** @brief Enable UART/USART associated to IRDA Handle.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
|
||||
|
||||
/** @brief Disable UART/USART associated to IRDA Handle.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @addtogroup IRDA_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Ensure that IRDA Baud rate is less or equal to maximum value.
|
||||
* @param __BAUDRATE__ specifies the IRDA Baudrate set by the user.
|
||||
* @retval True or False
|
||||
*/
|
||||
#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)
|
||||
|
||||
/** @brief Ensure that IRDA prescaler value is strictly larger than 0.
|
||||
* @param __PRESCALER__ specifies the IRDA prescaler value set by the user.
|
||||
* @retval True or False
|
||||
*/
|
||||
#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
|
||||
|
||||
/** @brief Ensure that IRDA frame parity is valid.
|
||||
* @param __PARITY__ IRDA frame parity.
|
||||
* @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
|
||||
((__PARITY__) == IRDA_PARITY_EVEN) || \
|
||||
((__PARITY__) == IRDA_PARITY_ODD))
|
||||
|
||||
/** @brief Ensure that IRDA communication mode is valid.
|
||||
* @param __MODE__ IRDA communication mode.
|
||||
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__)\
|
||||
& (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
|
||||
|
||||
/** @brief Ensure that IRDA power mode is valid.
|
||||
* @param __MODE__ IRDA power mode.
|
||||
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
|
||||
((__MODE__) == IRDA_POWERMODE_NORMAL))
|
||||
|
||||
/** @brief Ensure that IRDA state is valid.
|
||||
* @param __STATE__ IRDA state mode.
|
||||
* @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
|
||||
((__STATE__) == IRDA_STATE_ENABLE))
|
||||
|
||||
/** @brief Ensure that IRDA associated UART/USART mode is valid.
|
||||
* @param __MODE__ IRDA associated UART/USART mode.
|
||||
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_MODE(__MODE__) (((__MODE__) == IRDA_MODE_DISABLE) || \
|
||||
((__MODE__) == IRDA_MODE_ENABLE))
|
||||
|
||||
/** @brief Ensure that IRDA sampling rate is valid.
|
||||
* @param __ONEBIT__ IRDA sampling rate.
|
||||
* @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
|
||||
((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))
|
||||
|
||||
/** @brief Ensure that IRDA DMA TX mode is valid.
|
||||
* @param __DMATX__ IRDA DMA TX mode.
|
||||
* @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_DMA_TX(__DMATX__) (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
|
||||
((__DMATX__) == IRDA_DMA_TX_ENABLE))
|
||||
|
||||
/** @brief Ensure that IRDA DMA RX mode is valid.
|
||||
* @param __DMARX__ IRDA DMA RX mode.
|
||||
* @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
|
||||
((__DMARX__) == IRDA_DMA_RX_ENABLE))
|
||||
|
||||
/** @brief Ensure that IRDA request is valid.
|
||||
* @param __PARAM__ IRDA request.
|
||||
* @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
|
||||
((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
|
||||
((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include IRDA HAL Extended module */
|
||||
#include "stm32f0xx_hal_irda_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
|
||||
|
||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID,
|
||||
pIRDA_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
|
||||
/* Transfer Abort functions */
|
||||
HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
|
||||
|
||||
void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
|
||||
/** @addtogroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda);
|
||||
uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USART_IRDA_SUPPORT */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F0xx_HAL_IRDA_H */
|
||||
|
||||
403
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_irda_ex.h
Normal file
403
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_irda_ex.h
Normal file
@@ -0,0 +1,403 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_irda_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of IRDA HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F0xx_HAL_IRDA_EX_H
|
||||
#define STM32F0xx_HAL_IRDA_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(USART_IRDA_SUPPORT)
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IRDAEx IRDAEx
|
||||
* @brief IRDA Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup IRDAEx_Extended_Exported_Constants IRDAEx Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IRDAEx_Word_Length IRDAEx Word Length
|
||||
* @{
|
||||
*/
|
||||
#if defined(USART_CR1_M1)&&defined(USART_CR1_M0)
|
||||
#define IRDA_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long frame */
|
||||
#define IRDA_WORDLENGTH_8B 0x00000000U /*!< 8-bit long frame */
|
||||
#define IRDA_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long frame */
|
||||
#else
|
||||
#if defined(USART_CR1_M)
|
||||
#define IRDA_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long frame */
|
||||
#define IRDA_WORDLENGTH_9B USART_CR1_M /*!< 9-bit long frame */
|
||||
#endif /* USART_CR1_M1 */
|
||||
#endif /* USART_CR1_M1 && USART_CR1_M0 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Report the IRDA clock source.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __CLOCKSOURCE__ output variable.
|
||||
* @retval IRDA clocking source, written in __CLOCKSOURCE__.
|
||||
*/
|
||||
|
||||
#if defined(STM32F031x6) || defined(STM32F038xx)
|
||||
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} while(0)
|
||||
#elif defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F051x8) || defined (STM32F058xx)
|
||||
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0)
|
||||
#elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
|
||||
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART4) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0)
|
||||
#elif defined(STM32F091xC) || defined(STM32F098xx)
|
||||
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART3_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART3CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART4) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART5) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART6) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART7) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART8) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
#endif /* defined(STM32F031x6) || defined(STM32F038xx) */
|
||||
|
||||
|
||||
/** @brief Compute the mask to apply to retrieve the received data
|
||||
* according to the word length and to the parity bits activation.
|
||||
* @note If PCE = 1, the parity bit is not included in the data extracted
|
||||
* by the reception API().
|
||||
* This masking operation is not carried out in the case of
|
||||
* DMA transfers.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.
|
||||
*/
|
||||
#if defined(USART_CR1_M1)&&defined(USART_CR1_M0)
|
||||
#define IRDA_MASK_COMPUTATION(__HANDLE__) \
|
||||
do { \
|
||||
if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x01FFU ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FFU ; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FFU ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007FU ; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007FU ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x003FU ; \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x0000U; \
|
||||
} \
|
||||
} while(0U)
|
||||
#else
|
||||
#if defined(USART_CR1_M)
|
||||
#define IRDA_MASK_COMPUTATION(__HANDLE__) \
|
||||
do { \
|
||||
if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x01FFU ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FFU ; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FFU ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007FU ; \
|
||||
} \
|
||||
} \
|
||||
} while(0U)
|
||||
#endif /* USART_CR1_M */
|
||||
#endif /* USART_CR1_M && USART_CR1_M0 */
|
||||
|
||||
/** @brief Ensure that IRDA frame length is valid.
|
||||
* @param __LENGTH__ IRDA frame length.
|
||||
* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
|
||||
*/
|
||||
#if defined(USART_CR1_M1)&&defined(USART_CR1_M0)
|
||||
#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
|
||||
((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
|
||||
((__LENGTH__) == IRDA_WORDLENGTH_9B))
|
||||
#else
|
||||
#if defined(USART_CR1_M)
|
||||
#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
|
||||
((__LENGTH__) == IRDA_WORDLENGTH_9B))
|
||||
#endif /* USART_CR1_M */
|
||||
#endif /* USART_CR1_M && USART_CR1_M0 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USART_IRDA_SUPPORT */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F0xx_HAL_IRDA_EX_H */
|
||||
|
||||
237
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_iwdg.h
Normal file
237
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_iwdg.h
Normal file
@@ -0,0 +1,237 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_iwdg.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of IWDG HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F0xx_HAL_IWDG_H
|
||||
#define STM32F0xx_HAL_IWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG IWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Exported_Types IWDG Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief IWDG Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
|
||||
This parameter can be a value of @ref IWDG_Prescaler */
|
||||
|
||||
uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
|
||||
|
||||
uint32_t Window; /*!< Specifies the window value to be compared to the down-counter.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
|
||||
|
||||
} IWDG_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IWDG Handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
IWDG_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
IWDG_InitTypeDef Init; /*!< IWDG required parameters */
|
||||
} IWDG_HandleTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Prescaler IWDG Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define IWDG_PRESCALER_4 0x00000000u /*!< IWDG prescaler set to 4 */
|
||||
#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
|
||||
#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
|
||||
#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
|
||||
#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
|
||||
#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
|
||||
#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Window_option IWDG Window option
|
||||
* @{
|
||||
*/
|
||||
#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the IWDG peripheral.
|
||||
* @param __HANDLE__ IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
|
||||
|
||||
/**
|
||||
* @brief Reload IWDG counter with value defined in the reload register
|
||||
* (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled).
|
||||
* @param __HANDLE__ IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/Start functions ********************************************/
|
||||
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Private_Constants IWDG Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief IWDG Key Register BitMask
|
||||
*/
|
||||
#define IWDG_KEY_RELOAD 0x0000AAAAu /*!< IWDG Reload Counter Enable */
|
||||
#define IWDG_KEY_ENABLE 0x0000CCCCu /*!< IWDG Peripheral Enable */
|
||||
#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u /*!< IWDG KR Write Access Enable */
|
||||
#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u /*!< IWDG KR Write Access Disable */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Private_Macros IWDG Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
|
||||
* @param __HANDLE__ IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
|
||||
|
||||
/**
|
||||
* @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
|
||||
* @param __HANDLE__ IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
|
||||
|
||||
/**
|
||||
* @brief Check IWDG prescaler value.
|
||||
* @param __PRESCALER__ IWDG prescaler value
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_8) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_16) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_32) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_64) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_128)|| \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_256))
|
||||
|
||||
/**
|
||||
* @brief Check IWDG reload value.
|
||||
* @param __RELOAD__ IWDG reload value
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
|
||||
|
||||
/**
|
||||
* @brief Check IWDG window value.
|
||||
* @param __WINDOW__ IWDG window value
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F0xx_HAL_IWDG_H */
|
||||
991
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd.h
Normal file
991
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd.h
Normal file
@@ -0,0 +1,991 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_pcd.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of PCD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F0xx_HAL_PCD_H
|
||||
#define STM32F0xx_HAL_PCD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_ll_usb.h"
|
||||
|
||||
#if defined (USB)
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PCD
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup PCD_Exported_Types PCD Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief PCD State structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_PCD_STATE_RESET = 0x00,
|
||||
HAL_PCD_STATE_READY = 0x01,
|
||||
HAL_PCD_STATE_ERROR = 0x02,
|
||||
HAL_PCD_STATE_BUSY = 0x03,
|
||||
HAL_PCD_STATE_TIMEOUT = 0x04
|
||||
} PCD_StateTypeDef;
|
||||
|
||||
/* Device LPM suspend state */
|
||||
typedef enum
|
||||
{
|
||||
LPM_L0 = 0x00, /* on */
|
||||
LPM_L1 = 0x01, /* LPM L1 sleep */
|
||||
LPM_L2 = 0x02, /* suspend */
|
||||
LPM_L3 = 0x03, /* off */
|
||||
} PCD_LPM_StateTypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PCD_LPM_L0_ACTIVE = 0x00, /* on */
|
||||
PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
|
||||
} PCD_LPM_MsgTypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PCD_BCD_ERROR = 0xFF,
|
||||
PCD_BCD_CONTACT_DETECTION = 0xFE,
|
||||
PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD,
|
||||
PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
|
||||
PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB,
|
||||
PCD_BCD_DISCOVERY_COMPLETED = 0x00,
|
||||
|
||||
} PCD_BCD_MsgTypeDef;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
typedef USB_TypeDef PCD_TypeDef;
|
||||
typedef USB_CfgTypeDef PCD_InitTypeDef;
|
||||
typedef USB_EPTypeDef PCD_EPTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief PCD Handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
typedef struct __PCD_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
{
|
||||
PCD_TypeDef *Instance; /*!< Register base address */
|
||||
PCD_InitTypeDef Init; /*!< PCD required parameters */
|
||||
__IO uint8_t USB_Address; /*!< USB Address */
|
||||
PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */
|
||||
PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */
|
||||
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
|
||||
__IO PCD_StateTypeDef State; /*!< PCD communication state */
|
||||
__IO uint32_t ErrorCode; /*!< PCD Error code */
|
||||
uint32_t Setup[12]; /*!< Setup packet buffer */
|
||||
PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
|
||||
uint32_t BESL;
|
||||
|
||||
|
||||
uint32_t lpm_active; /*!< Enable or disable the Link Power Management .
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
|
||||
uint32_t battery_charging_active; /*!< Enable or disable Battery charging.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
void *pData; /*!< Pointer to upper stack Handler */
|
||||
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD SOF callback */
|
||||
void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Setup Stage callback */
|
||||
void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Reset callback */
|
||||
void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Suspend callback */
|
||||
void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Resume callback */
|
||||
void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Connect callback */
|
||||
void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Disconnect callback */
|
||||
|
||||
void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data OUT Stage callback */
|
||||
void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data IN Stage callback */
|
||||
void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO OUT Incomplete callback */
|
||||
void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO IN Incomplete callback */
|
||||
void (* BCDCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< USB OTG PCD BCD callback */
|
||||
void (* LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< USB OTG PCD LPM callback */
|
||||
|
||||
void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp DeInit callback */
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
} PCD_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include PCD HAL Extended module */
|
||||
#include "stm32f0xx_hal_pcd_ex.h"
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup PCD_Exported_Constants PCD Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PCD_Speed PCD Speed
|
||||
* @{
|
||||
*/
|
||||
#define PCD_SPEED_FULL USBD_FS_SPEED
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PCD_PHY_Module PCD PHY Module
|
||||
* @{
|
||||
*/
|
||||
#define PCD_PHY_ULPI 1U
|
||||
#define PCD_PHY_EMBEDDED 2U
|
||||
#define PCD_PHY_UTMI 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PCD_Error_Code_definition PCD Error Code definition
|
||||
* @brief PCD Error Code definition
|
||||
* @{
|
||||
*/
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
#define HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup PCD_Exported_Macros PCD Exported Macros
|
||||
* @brief macros to handle interrupts and specific clock configurations
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
|
||||
#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
|
||||
|
||||
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \
|
||||
((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
|
||||
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR)\
|
||||
&= (uint16_t)(~(__INTERRUPT__)))
|
||||
|
||||
#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE
|
||||
#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup PCD_Exported_Functions PCD Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition
|
||||
* @brief HAL USB OTG PCD Callback ID enumeration definition
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_PCD_SOF_CB_ID = 0x01, /*!< USB PCD SOF callback ID */
|
||||
HAL_PCD_SETUPSTAGE_CB_ID = 0x02, /*!< USB PCD Setup Stage callback ID */
|
||||
HAL_PCD_RESET_CB_ID = 0x03, /*!< USB PCD Reset callback ID */
|
||||
HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */
|
||||
HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */
|
||||
HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */
|
||||
HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
|
||||
|
||||
HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */
|
||||
HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */
|
||||
|
||||
} HAL_PCD_CallbackIDTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition
|
||||
* @brief HAL USB OTG PCD Callback pointer definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd); /*!< pointer to a common USB OTG PCD callback function */
|
||||
typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data OUT Stage callback */
|
||||
typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data IN Stage callback */
|
||||
typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */
|
||||
typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO IN Incomplete callback */
|
||||
typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< pointer to USB OTG PCD LPM callback */
|
||||
typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< pointer to USB OTG PCD BCD callback */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID,
|
||||
pPCD_CallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
|
||||
pPCD_DataOutStageCallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
|
||||
pPCD_DataInStageCallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
|
||||
pPCD_IsoOutIncpltCallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
|
||||
pPCD_IsoInIncpltCallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* I/O operation functions ***************************************************/
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions **********************************************/
|
||||
/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
|
||||
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral State functions ************************************************/
|
||||
/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup PCD_Private_Constants PCD Private Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
#define USB_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PCD_EP0_MPS PCD EP0 MPS
|
||||
* @{
|
||||
*/
|
||||
#define PCD_EP0MPS_64 EP_MPS_64
|
||||
#define PCD_EP0MPS_32 EP_MPS_32
|
||||
#define PCD_EP0MPS_16 EP_MPS_16
|
||||
#define PCD_EP0MPS_08 EP_MPS_8
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PCD_ENDP PCD ENDP
|
||||
* @{
|
||||
*/
|
||||
#define PCD_ENDP0 0U
|
||||
#define PCD_ENDP1 1U
|
||||
#define PCD_ENDP2 2U
|
||||
#define PCD_ENDP3 3U
|
||||
#define PCD_ENDP4 4U
|
||||
#define PCD_ENDP5 5U
|
||||
#define PCD_ENDP6 6U
|
||||
#define PCD_ENDP7 7U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind
|
||||
* @{
|
||||
*/
|
||||
#define PCD_SNG_BUF 0U
|
||||
#define PCD_DBL_BUF 1U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup PCD_Private_Macros PCD Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/******************** Bit definition for USB_COUNTn_RX register *************/
|
||||
#define USB_CNTRX_NBLK_MSK (0x1FU << 10)
|
||||
#define USB_CNTRX_BLSIZE (0x1U << 15)
|
||||
|
||||
/* SetENDPOINT */
|
||||
#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) \
|
||||
(*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))
|
||||
|
||||
/* GetENDPOINT */
|
||||
#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))
|
||||
|
||||
|
||||
/**
|
||||
* @brief sets the type in the endpoint register(bits EP_TYPE[1:0])
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @param wType Endpoint Type.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EPTYPE(USBx, bEpNum, wType) \
|
||||
(PCD_SET_ENDPOINT((USBx), (bEpNum), \
|
||||
((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
|
||||
|
||||
|
||||
/**
|
||||
* @brief gets the type in the endpoint register(bits EP_TYPE[1:0])
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval Endpoint Type
|
||||
*/
|
||||
#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
|
||||
|
||||
/**
|
||||
* @brief free buffer used from the application realizing it to the line
|
||||
* toggles bit SW_BUF in the double buffered endpoint register
|
||||
* @param USBx USB device.
|
||||
* @param bEpNum, bDir
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_FREE_USER_BUFFER(USBx, bEpNum, bDir) \
|
||||
do { \
|
||||
if ((bDir) == 0U) \
|
||||
{ \
|
||||
/* OUT double buffered endpoint */ \
|
||||
PCD_TX_DTOG((USBx), (bEpNum)); \
|
||||
} \
|
||||
else if ((bDir) == 1U) \
|
||||
{ \
|
||||
/* IN double buffered endpoint */ \
|
||||
PCD_RX_DTOG((USBx), (bEpNum)); \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief sets the status for tx transfer (bits STAT_TX[1:0]).
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @param wState new state
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) \
|
||||
do { \
|
||||
uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \
|
||||
/* toggle first bit ? */ \
|
||||
if ((USB_EPTX_DTOG1 & (wState))!= 0U) \
|
||||
{ \
|
||||
_wRegVal ^= USB_EPTX_DTOG1; \
|
||||
} \
|
||||
/* toggle second bit ? */ \
|
||||
if ((USB_EPTX_DTOG2 & (wState))!= 0U) \
|
||||
{ \
|
||||
_wRegVal ^= USB_EPTX_DTOG2; \
|
||||
} \
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
|
||||
} while(0) /* PCD_SET_EP_TX_STATUS */
|
||||
|
||||
/**
|
||||
* @brief sets the status for rx transfer (bits STAT_TX[1:0])
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @param wState new state
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) \
|
||||
do { \
|
||||
uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \
|
||||
/* toggle first bit ? */ \
|
||||
if ((USB_EPRX_DTOG1 & (wState))!= 0U) \
|
||||
{ \
|
||||
_wRegVal ^= USB_EPRX_DTOG1; \
|
||||
} \
|
||||
/* toggle second bit ? */ \
|
||||
if ((USB_EPRX_DTOG2 & (wState))!= 0U) \
|
||||
{ \
|
||||
_wRegVal ^= USB_EPRX_DTOG2; \
|
||||
} \
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
|
||||
} while(0) /* PCD_SET_EP_RX_STATUS */
|
||||
|
||||
/**
|
||||
* @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @param wStaterx new state.
|
||||
* @param wStatetx new state.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) \
|
||||
do { \
|
||||
uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \
|
||||
/* toggle first bit ? */ \
|
||||
if ((USB_EPRX_DTOG1 & (wStaterx))!= 0U) \
|
||||
{ \
|
||||
_wRegVal ^= USB_EPRX_DTOG1; \
|
||||
} \
|
||||
/* toggle second bit ? */ \
|
||||
if ((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \
|
||||
{ \
|
||||
_wRegVal ^= USB_EPRX_DTOG2; \
|
||||
} \
|
||||
/* toggle first bit ? */ \
|
||||
if ((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \
|
||||
{ \
|
||||
_wRegVal ^= USB_EPTX_DTOG1; \
|
||||
} \
|
||||
/* toggle second bit ? */ \
|
||||
if ((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \
|
||||
{ \
|
||||
_wRegVal ^= USB_EPTX_DTOG2; \
|
||||
} \
|
||||
\
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
|
||||
} while(0) /* PCD_SET_EP_TXRX_STATUS */
|
||||
|
||||
/**
|
||||
* @brief gets the status for tx/rx transfer (bits STAT_TX[1:0]
|
||||
* /STAT_RX[1:0])
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval status
|
||||
*/
|
||||
#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
|
||||
#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
|
||||
|
||||
/**
|
||||
* @brief sets directly the VALID tx/rx-status into the endpoint register
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
|
||||
#define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
|
||||
|
||||
/**
|
||||
* @brief checks stall condition in an endpoint.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval TRUE = endpoint in stall condition.
|
||||
*/
|
||||
#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) == USB_EP_TX_STALL)
|
||||
#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) == USB_EP_RX_STALL)
|
||||
|
||||
/**
|
||||
* @brief set & clear EP_KIND bit.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_KIND(USBx, bEpNum) \
|
||||
do { \
|
||||
uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
|
||||
\
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \
|
||||
} while(0) /* PCD_SET_EP_KIND */
|
||||
|
||||
#define PCD_CLEAR_EP_KIND(USBx, bEpNum) \
|
||||
do { \
|
||||
uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \
|
||||
\
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
|
||||
} while(0) /* PCD_CLEAR_EP_KIND */
|
||||
|
||||
/**
|
||||
* @brief Sets/clears directly STATUS_OUT bit in the endpoint register.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
|
||||
#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
|
||||
|
||||
/**
|
||||
* @brief Sets/clears directly EP_KIND bit in the endpoint register.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_BULK_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
|
||||
#define PCD_CLEAR_BULK_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
|
||||
|
||||
/**
|
||||
* @brief Clears bit CTR_RX / CTR_TX in the endpoint register.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) \
|
||||
do { \
|
||||
uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \
|
||||
\
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_TX)); \
|
||||
} while(0) /* PCD_CLEAR_RX_EP_CTR */
|
||||
|
||||
#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) \
|
||||
do { \
|
||||
uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \
|
||||
\
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX)); \
|
||||
} while(0) /* PCD_CLEAR_TX_EP_CTR */
|
||||
|
||||
/**
|
||||
* @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_RX_DTOG(USBx, bEpNum) \
|
||||
do { \
|
||||
uint16_t _wEPVal; \
|
||||
\
|
||||
_wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
|
||||
\
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \
|
||||
} while(0) /* PCD_RX_DTOG */
|
||||
|
||||
#define PCD_TX_DTOG(USBx, bEpNum) \
|
||||
do { \
|
||||
uint16_t _wEPVal; \
|
||||
\
|
||||
_wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
|
||||
\
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_TX)); \
|
||||
} while(0) /* PCD_TX_DTOG */
|
||||
/**
|
||||
* @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) \
|
||||
do { \
|
||||
uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
|
||||
\
|
||||
if ((_wRegVal & USB_EP_DTOG_RX) != 0U)\
|
||||
{ \
|
||||
PCD_RX_DTOG((USBx), (bEpNum)); \
|
||||
} \
|
||||
} while(0) /* PCD_CLEAR_RX_DTOG */
|
||||
|
||||
#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) \
|
||||
do { \
|
||||
uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
|
||||
\
|
||||
if ((_wRegVal & USB_EP_DTOG_TX) != 0U)\
|
||||
{ \
|
||||
PCD_TX_DTOG((USBx), (bEpNum)); \
|
||||
} \
|
||||
} while(0) /* PCD_CLEAR_TX_DTOG */
|
||||
|
||||
/**
|
||||
* @brief Sets address in an endpoint register.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @param bAddr Address.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) \
|
||||
do { \
|
||||
uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \
|
||||
\
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
|
||||
} while(0) /* PCD_SET_EP_ADDRESS */
|
||||
|
||||
/**
|
||||
* @brief Gets address in an endpoint register.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
|
||||
|
||||
#define PCD_EP_TX_CNT(USBx, bEpNum) \
|
||||
((uint16_t *)((((uint32_t)(USBx)->BTABLE + \
|
||||
((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
|
||||
|
||||
#define PCD_EP_RX_CNT(USBx, bEpNum) \
|
||||
((uint16_t *)((((uint32_t)(USBx)->BTABLE + \
|
||||
((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
|
||||
|
||||
|
||||
/**
|
||||
* @brief sets address of the tx/rx buffer.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @param wAddr address to be set (must be word aligned).
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) \
|
||||
do { \
|
||||
__IO uint16_t *_wRegVal; \
|
||||
uint32_t _wRegBase = (uint32_t)USBx; \
|
||||
\
|
||||
_wRegBase += (uint32_t)(USBx)->BTABLE; \
|
||||
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \
|
||||
*_wRegVal = ((wAddr) >> 1) << 1; \
|
||||
} while(0) /* PCD_SET_EP_TX_ADDRESS */
|
||||
|
||||
#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) \
|
||||
do { \
|
||||
__IO uint16_t *_wRegVal; \
|
||||
uint32_t _wRegBase = (uint32_t)USBx; \
|
||||
\
|
||||
_wRegBase += (uint32_t)(USBx)->BTABLE; \
|
||||
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \
|
||||
*_wRegVal = ((wAddr) >> 1) << 1; \
|
||||
} while(0) /* PCD_SET_EP_RX_ADDRESS */
|
||||
|
||||
/**
|
||||
* @brief Gets address of the tx/rx buffer.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval address of the buffer.
|
||||
*/
|
||||
#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
|
||||
#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
|
||||
|
||||
/**
|
||||
* @brief Sets counter of rx buffer with no. of blocks.
|
||||
* @param pdwReg Register pointer
|
||||
* @param wCount Counter.
|
||||
* @param wNBlocks no. of Blocks.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) \
|
||||
do { \
|
||||
(wNBlocks) = (wCount) >> 5; \
|
||||
if (((wCount) & 0x1fU) == 0U) \
|
||||
{ \
|
||||
(wNBlocks)--; \
|
||||
} \
|
||||
*(pdwReg) |= (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \
|
||||
} while(0) /* PCD_CALC_BLK32 */
|
||||
|
||||
#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) \
|
||||
do { \
|
||||
(wNBlocks) = (wCount) >> 1; \
|
||||
if (((wCount) & 0x1U) != 0U) \
|
||||
{ \
|
||||
(wNBlocks)++; \
|
||||
} \
|
||||
*(pdwReg) |= (uint16_t)((wNBlocks) << 10); \
|
||||
} while(0) /* PCD_CALC_BLK2 */
|
||||
|
||||
#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) \
|
||||
do { \
|
||||
uint32_t wNBlocks; \
|
||||
\
|
||||
*(pdwReg) &= 0x3FFU; \
|
||||
\
|
||||
if ((wCount) == 0U) \
|
||||
{ \
|
||||
*(pdwReg) |= USB_CNTRX_BLSIZE; \
|
||||
} \
|
||||
else if ((wCount) <= 62U) \
|
||||
{ \
|
||||
PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
|
||||
} \
|
||||
} while(0) /* PCD_SET_EP_CNT_RX_REG */
|
||||
|
||||
#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) \
|
||||
do { \
|
||||
uint32_t _wRegBase = (uint32_t)(USBx); \
|
||||
__IO uint16_t *pdwReg; \
|
||||
\
|
||||
_wRegBase += (uint32_t)(USBx)->BTABLE; \
|
||||
pdwReg = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
|
||||
PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief sets counter for the tx/rx buffer.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @param wCount Counter value.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) \
|
||||
do { \
|
||||
uint32_t _wRegBase = (uint32_t)(USBx); \
|
||||
__IO uint16_t *_wRegVal; \
|
||||
\
|
||||
_wRegBase += (uint32_t)(USBx)->BTABLE; \
|
||||
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
|
||||
*_wRegVal = (uint16_t)(wCount); \
|
||||
} while(0)
|
||||
|
||||
#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) \
|
||||
do { \
|
||||
uint32_t _wRegBase = (uint32_t)(USBx); \
|
||||
__IO uint16_t *_wRegVal; \
|
||||
\
|
||||
_wRegBase += (uint32_t)(USBx)->BTABLE; \
|
||||
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
|
||||
PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief gets counter of the tx buffer.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval Counter value
|
||||
*/
|
||||
#define PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU)
|
||||
#define PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU)
|
||||
|
||||
/**
|
||||
* @brief Sets buffer 0/1 address in a double buffer endpoint.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @param wBuf0Addr buffer 0 address.
|
||||
* @retval Counter value
|
||||
*/
|
||||
#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) \
|
||||
do { \
|
||||
PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \
|
||||
} while(0) /* PCD_SET_EP_DBUF0_ADDR */
|
||||
|
||||
#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) \
|
||||
do { \
|
||||
PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \
|
||||
} while(0) /* PCD_SET_EP_DBUF1_ADDR */
|
||||
|
||||
/**
|
||||
* @brief Sets addresses in a double buffer endpoint.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @param wBuf0Addr: buffer 0 address.
|
||||
* @param wBuf1Addr = buffer 1 address.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) \
|
||||
do { \
|
||||
PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \
|
||||
PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \
|
||||
} while(0) /* PCD_SET_EP_DBUF_ADDR */
|
||||
|
||||
/**
|
||||
* @brief Gets buffer 0/1 address of a double buffer endpoint.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
|
||||
#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
|
||||
|
||||
/**
|
||||
* @brief Gets buffer 0/1 address of a double buffer endpoint.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @param bDir endpoint dir EP_DBUF_OUT = OUT
|
||||
* EP_DBUF_IN = IN
|
||||
* @param wCount: Counter value
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) \
|
||||
do { \
|
||||
if ((bDir) == 0U) \
|
||||
/* OUT endpoint */ \
|
||||
{ \
|
||||
PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum), (wCount)); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
if ((bDir) == 1U) \
|
||||
{ \
|
||||
/* IN endpoint */ \
|
||||
PCD_SET_EP_TX_CNT((USBx), (bEpNum), (wCount)); \
|
||||
} \
|
||||
} \
|
||||
} while(0) /* SetEPDblBuf0Count*/
|
||||
|
||||
#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) \
|
||||
do { \
|
||||
uint32_t _wBase = (uint32_t)(USBx); \
|
||||
__IO uint16_t *_wEPRegVal; \
|
||||
\
|
||||
if ((bDir) == 0U) \
|
||||
{ \
|
||||
/* OUT endpoint */ \
|
||||
PCD_SET_EP_RX_CNT((USBx), (bEpNum), (wCount)); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
if ((bDir) == 1U) \
|
||||
{ \
|
||||
/* IN endpoint */ \
|
||||
_wBase += (uint32_t)(USBx)->BTABLE; \
|
||||
_wEPRegVal = (__IO uint16_t *)(_wBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
|
||||
*_wEPRegVal = (uint16_t)(wCount); \
|
||||
} \
|
||||
} \
|
||||
} while(0) /* SetEPDblBuf1Count */
|
||||
|
||||
#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) \
|
||||
do { \
|
||||
PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
|
||||
PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
|
||||
} while(0) /* PCD_SET_EP_DBUF_CNT */
|
||||
|
||||
/**
|
||||
* @brief Gets buffer 0/1 rx/tx counter for double buffering.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
|
||||
#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* defined (USB) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F0xx_HAL_PCD_H */
|
||||
88
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd_ex.h
Normal file
88
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd_ex.h
Normal file
@@ -0,0 +1,88 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_pcd_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of PCD HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F0xx_HAL_PCD_EX_H
|
||||
#define STM32F0xx_HAL_PCD_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
#if defined (USB)
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PCDEx
|
||||
* @{
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
|
||||
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
|
||||
uint16_t ep_kind, uint32_t pmaadress);
|
||||
|
||||
|
||||
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
|
||||
HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
|
||||
void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* defined (USB) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
|
||||
#endif /* STM32F0xx_HAL_PCD_EX_H */
|
||||
185
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h
Normal file
185
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h
Normal file
@@ -0,0 +1,185 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_pwr.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of PWR HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0xx_HAL_PWR_H
|
||||
#define __STM32F0xx_HAL_PWR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR PWR
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWR_Exported_Constants PWR Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in STOP mode
|
||||
* @{
|
||||
*/
|
||||
#define PWR_MAINREGULATOR_ON (0x00000000U)
|
||||
#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
|
||||
|
||||
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
|
||||
((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
|
||||
* @{
|
||||
*/
|
||||
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U)
|
||||
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U)
|
||||
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
|
||||
* @{
|
||||
*/
|
||||
#define PWR_STOPENTRY_WFI ((uint8_t)0x01U)
|
||||
#define PWR_STOPENTRY_WFE ((uint8_t)0x02U)
|
||||
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup PWR_Exported_Macro PWR Exported Macro
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Check PWR flag is set or not.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
|
||||
* was received from the WKUP pin or from the RTC alarm (Alarm A),
|
||||
* RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
|
||||
* An additional wakeup event is detected if the WKUP pin is enabled
|
||||
* (by setting the EWUP bit) when the WKUP pin level is already high.
|
||||
* @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
|
||||
* resumed from StandBy mode.
|
||||
* @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
|
||||
* by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
|
||||
* For this reason, this bit is equal to 0 after Standby or reset
|
||||
* until the PVDE bit is set.
|
||||
* Warning: this Flag is not available on STM32F030x8 products
|
||||
* @arg PWR_FLAG_VREFINTRDY: This flag indicates that the internal reference
|
||||
* voltage VREFINT is ready.
|
||||
* Warning: this Flag is not available on STM32F030x8 products
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the PWR's pending flags.
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_FLAG_WU: Wake Up flag
|
||||
* @arg PWR_FLAG_SB: StandBy flag
|
||||
*/
|
||||
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include PWR HAL Extension module */
|
||||
#include "stm32f0xx_hal_pwr_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup PWR_Exported_Functions PWR Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
void HAL_PWR_DeInit(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions **********************************************/
|
||||
void HAL_PWR_EnableBkUpAccess(void);
|
||||
void HAL_PWR_DisableBkUpAccess(void);
|
||||
|
||||
/* WakeUp pins configuration functions ****************************************/
|
||||
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
|
||||
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
|
||||
|
||||
/* Low Power modes configuration functions ************************************/
|
||||
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
|
||||
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
|
||||
void HAL_PWR_EnterSTANDBYMode(void);
|
||||
|
||||
void HAL_PWR_EnableSleepOnExit(void);
|
||||
void HAL_PWR_DisableSleepOnExit(void);
|
||||
void HAL_PWR_EnableSEVOnPend(void);
|
||||
void HAL_PWR_DisableSEVOnPend(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F0xx_HAL_PWR_H */
|
||||
455
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h
Normal file
455
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h
Normal file
@@ -0,0 +1,455 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_pwr_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of PWR HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0xx_HAL_PWR_EX_H
|
||||
#define __STM32F0xx_HAL_PWR_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWREx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWREx_Exported_Types PWREx Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
|
||||
defined (STM32F071xB) || defined (STM32F072xB) || \
|
||||
defined (STM32F091xC)
|
||||
|
||||
/**
|
||||
* @brief PWR PVD configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level
|
||||
This parameter can be a value of @ref PWREx_PVD_detection_level */
|
||||
|
||||
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref PWREx_PVD_Mode */
|
||||
}PWR_PVDTypeDef;
|
||||
|
||||
#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
|
||||
/* defined (STM32F071xB) || defined (STM32F072xB) || */
|
||||
/* defined (STM32F091xC) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup PWREx_WakeUp_Pins PWREx Wakeup Pins
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
|
||||
defined (STM32F091xC) || defined (STM32F098xx)
|
||||
#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1)
|
||||
#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2)
|
||||
#define PWR_WAKEUP_PIN3 ((uint32_t)PWR_CSR_EWUP3)
|
||||
#define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4)
|
||||
#define PWR_WAKEUP_PIN5 ((uint32_t)PWR_CSR_EWUP5)
|
||||
#define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6)
|
||||
#define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7)
|
||||
#define PWR_WAKEUP_PIN8 ((uint32_t)PWR_CSR_EWUP8)
|
||||
|
||||
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
|
||||
((PIN) == PWR_WAKEUP_PIN2) || \
|
||||
((PIN) == PWR_WAKEUP_PIN3) || \
|
||||
((PIN) == PWR_WAKEUP_PIN4) || \
|
||||
((PIN) == PWR_WAKEUP_PIN5) || \
|
||||
((PIN) == PWR_WAKEUP_PIN6) || \
|
||||
((PIN) == PWR_WAKEUP_PIN7) || \
|
||||
((PIN) == PWR_WAKEUP_PIN8))
|
||||
|
||||
#elif defined(STM32F030xC) || defined (STM32F070xB)
|
||||
#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1)
|
||||
#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2)
|
||||
#define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4)
|
||||
#define PWR_WAKEUP_PIN5 ((uint32_t)PWR_CSR_EWUP5)
|
||||
#define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6)
|
||||
#define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7)
|
||||
|
||||
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
|
||||
((PIN) == PWR_WAKEUP_PIN2) || \
|
||||
((PIN) == PWR_WAKEUP_PIN4) || \
|
||||
((PIN) == PWR_WAKEUP_PIN5) || \
|
||||
((PIN) == PWR_WAKEUP_PIN6) || \
|
||||
((PIN) == PWR_WAKEUP_PIN7))
|
||||
|
||||
#elif defined(STM32F042x6) || defined (STM32F048xx)
|
||||
#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1)
|
||||
#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2)
|
||||
#define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4)
|
||||
#define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6)
|
||||
#define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7)
|
||||
|
||||
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
|
||||
((PIN) == PWR_WAKEUP_PIN2) || \
|
||||
((PIN) == PWR_WAKEUP_PIN4) || \
|
||||
((PIN) == PWR_WAKEUP_PIN6) || \
|
||||
((PIN) == PWR_WAKEUP_PIN7))
|
||||
|
||||
#else
|
||||
#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1)
|
||||
#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2)
|
||||
|
||||
|
||||
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
|
||||
((PIN) == PWR_WAKEUP_PIN2))
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_EXTI_Line PWREx EXTI Line
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
|
||||
defined (STM32F071xB) || defined (STM32F072xB) || \
|
||||
defined (STM32F091xC)
|
||||
|
||||
#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
|
||||
|
||||
#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
|
||||
/* defined (STM32F071xB) || defined (STM32F072xB) || */
|
||||
/* defined (STM32F091xC) */
|
||||
|
||||
#if defined (STM32F042x6) || defined (STM32F048xx) || \
|
||||
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
|
||||
defined (STM32F091xC) || defined (STM32F098xx)
|
||||
|
||||
#define PWR_EXTI_LINE_VDDIO2 ((uint32_t)EXTI_IMR_MR31) /*!< External interrupt line 31 Connected to the Vddio2 Monitor EXTI Line */
|
||||
|
||||
#endif /* defined (STM32F042x6) || defined (STM32F048xx) ||\
|
||||
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
|
||||
defined (STM32F091xC) || defined (STM32F098xx) ||*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
|
||||
defined (STM32F071xB) || defined (STM32F072xB) || \
|
||||
defined (STM32F091xC)
|
||||
/** @defgroup PWREx_PVD_detection_level PWREx PVD detection level
|
||||
* @{
|
||||
*/
|
||||
#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
|
||||
#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
|
||||
#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
|
||||
#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
|
||||
#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
|
||||
#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
|
||||
#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
|
||||
#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7
|
||||
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_PVD_Mode PWREx PVD Mode
|
||||
* @{
|
||||
*/
|
||||
#define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< basic mode is used */
|
||||
#define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
#define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */
|
||||
#define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */
|
||||
#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */
|
||||
|
||||
#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
|
||||
((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
|
||||
((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
|
||||
((MODE) == PWR_PVD_MODE_NORMAL))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
|
||||
/* defined (STM32F071xB) || defined (STM32F072xB) || */
|
||||
/* defined (STM32F091xC) */
|
||||
|
||||
/** @defgroup PWREx_Flag PWREx Flag
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
|
||||
defined (STM32F071xB) || defined (STM32F072xB) || \
|
||||
defined (STM32F091xC)
|
||||
|
||||
#define PWR_FLAG_WU PWR_CSR_WUF
|
||||
#define PWR_FLAG_SB PWR_CSR_SBF
|
||||
#define PWR_FLAG_PVDO PWR_CSR_PVDO
|
||||
#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
|
||||
#elif defined (STM32F070x6) || defined (STM32F070xB) || defined (STM32F030xC)
|
||||
#define PWR_FLAG_WU PWR_CSR_WUF
|
||||
#define PWR_FLAG_SB PWR_CSR_SBF
|
||||
#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
|
||||
#else
|
||||
#define PWR_FLAG_WU PWR_CSR_WUF
|
||||
#define PWR_FLAG_SB PWR_CSR_SBF
|
||||
|
||||
#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
|
||||
/* defined (STM32F071xB) || defined (STM32F072xB) || */
|
||||
/* defined (STM32F091xC) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup PWREx_Exported_Macros PWREx Exported Macros
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
|
||||
defined (STM32F071xB) || defined (STM32F072xB) || \
|
||||
defined (STM32F091xC)
|
||||
/**
|
||||
* @brief Enable interrupt on PVD Exti Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
|
||||
|
||||
/**
|
||||
* @brief Disable interrupt on PVD Exti Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
|
||||
|
||||
/**
|
||||
* @brief Enable event on PVD Exti Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
|
||||
|
||||
/**
|
||||
* @brief Disable event on PVD Exti Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Rising Trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Falling Trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
|
||||
|
||||
|
||||
/**
|
||||
* @brief PVD EXTI line configuration: set falling edge trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief PVD EXTI line configuration: set rising edge trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() EXTI->RTSR |= (PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVD Extended Interrupt Rising & Falling Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified PVD EXTI interrupt flag is set or not.
|
||||
* @retval EXTI PVD Line Status.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
|
||||
|
||||
/**
|
||||
* @brief Clear the PVD EXTI flag.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
|
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on selected EXTI line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
|
||||
|
||||
#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
|
||||
/* defined (STM32F071xB) || defined (STM32F072xB) || */
|
||||
/* defined (STM32F091xC) */
|
||||
|
||||
|
||||
#if defined (STM32F042x6) || defined (STM32F048xx) || \
|
||||
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
|
||||
defined (STM32F091xC) || defined (STM32F098xx)
|
||||
/**
|
||||
* @brief Enable interrupt on Vddio2 Monitor Exti Line 31.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_VDDIO2_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_VDDIO2))
|
||||
|
||||
/**
|
||||
* @brief Disable interrupt on Vddio2 Monitor Exti Line 31.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_VDDIO2_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_VDDIO2))
|
||||
|
||||
/**
|
||||
* @brief Vddio2 Monitor EXTI line configuration: clear falling edge and rising edge trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE() \
|
||||
do{ \
|
||||
EXTI->FTSR &= ~(PWR_EXTI_LINE_VDDIO2); \
|
||||
EXTI->RTSR &= ~(PWR_EXTI_LINE_VDDIO2); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Vddio2 Monitor EXTI line configuration: set falling edge trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_VDDIO2)
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified VDDIO2 monitor EXTI interrupt flag is set or not.
|
||||
* @retval EXTI VDDIO2 Monitor Line Status.
|
||||
*/
|
||||
#define __HAL_PWR_VDDIO2_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_VDDIO2))
|
||||
|
||||
/**
|
||||
* @brief Clear the VDDIO2 Monitor EXTI flag.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_VDDIO2_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_VDDIO2))
|
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on selected EXTI line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_VDDIO2_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_VDDIO2))
|
||||
|
||||
|
||||
#endif /* defined (STM32F042x6) || defined (STM32F048xx) ||\
|
||||
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
|
||||
defined (STM32F091xC) || defined (STM32F098xx) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWREx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ***************************************************/
|
||||
#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
|
||||
defined (STM32F071xB) || defined (STM32F072xB) || \
|
||||
defined (STM32F091xC)
|
||||
void HAL_PWR_PVD_IRQHandler(void);
|
||||
void HAL_PWR_PVDCallback(void);
|
||||
#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
|
||||
/* defined (STM32F071xB) || defined (STM32F072xB) || */
|
||||
/* defined (STM32F091xC) */
|
||||
|
||||
#if defined (STM32F042x6) || defined (STM32F048xx) || \
|
||||
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
|
||||
defined (STM32F091xC) || defined (STM32F098xx)
|
||||
void HAL_PWREx_Vddio2Monitor_IRQHandler(void);
|
||||
void HAL_PWREx_Vddio2MonitorCallback(void);
|
||||
#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
|
||||
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
|
||||
defined (STM32F091xC) || defined (STM32F098xx) */
|
||||
|
||||
/* Peripheral Control functions **********************************************/
|
||||
#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
|
||||
defined (STM32F071xB) || defined (STM32F072xB) || \
|
||||
defined (STM32F091xC)
|
||||
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
|
||||
void HAL_PWR_EnablePVD(void);
|
||||
void HAL_PWR_DisablePVD(void);
|
||||
#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
|
||||
/* defined (STM32F071xB) || defined (STM32F072xB) || */
|
||||
/* defined (STM32F091xC) */
|
||||
|
||||
#if defined (STM32F042x6) || defined (STM32F048xx) || \
|
||||
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
|
||||
defined (STM32F091xC) || defined (STM32F098xx)
|
||||
void HAL_PWREx_EnableVddio2Monitor(void);
|
||||
void HAL_PWREx_DisableVddio2Monitor(void);
|
||||
#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
|
||||
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
|
||||
defined (STM32F091xC) || defined (STM32F098xx) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0xx_HAL_PWR_EX_H */
|
||||
1683
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h
Normal file
1683
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h
Normal file
File diff suppressed because it is too large
Load Diff
2082
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h
Normal file
2082
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h
Normal file
File diff suppressed because it is too large
Load Diff
920
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rtc.h
Normal file
920
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rtc.h
Normal file
@@ -0,0 +1,920 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_rtc.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of RTC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F0xx_HAL_RTC_H
|
||||
#define STM32F0xx_HAL_RTC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RTC_Exported_Types RTC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */
|
||||
HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */
|
||||
HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */
|
||||
HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */
|
||||
HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */
|
||||
} HAL_RTCStateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t HourFormat; /*!< Specifies the RTC Hour Format.
|
||||
This parameter can be a value of @ref RTC_Hour_Formats */
|
||||
|
||||
uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
|
||||
|
||||
uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FFF */
|
||||
|
||||
uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output.
|
||||
This parameter can be a value of @ref RTC_Output_selection_Definitions */
|
||||
|
||||
uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal.
|
||||
This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
|
||||
|
||||
uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode.
|
||||
This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
|
||||
} RTC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Time structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t Hours; /*!< Specifies the RTC Time Hour.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
|
||||
|
||||
uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
|
||||
|
||||
uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
|
||||
|
||||
uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
|
||||
This parameter can be a value of @ref RTC_AM_PM_Definitions */
|
||||
|
||||
uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content.
|
||||
This parameter corresponds to a time unit range between [0-1] Second
|
||||
with [1 Sec / SecondFraction +1] granularity */
|
||||
|
||||
uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content
|
||||
corresponding to Synchronous prescaler factor value (PREDIV_S)
|
||||
This parameter corresponds to a time unit range between [0-1] Second
|
||||
with [1 Sec / SecondFraction +1] granularity.
|
||||
This field will be used only by HAL_RTC_GetTime function */
|
||||
|
||||
uint32_t DayLightSaving; /*!< This interface is deprecated. To manage Daylight
|
||||
Saving Time, please use HAL_RTC_DST_xxx functions */
|
||||
|
||||
uint32_t StoreOperation; /*!< This interface is deprecated. To manage Daylight
|
||||
Saving Time, please use HAL_RTC_DST_xxx functions */
|
||||
} RTC_TimeTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Date structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
|
||||
This parameter can be a value of @ref RTC_WeekDay_Definitions */
|
||||
|
||||
uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
|
||||
This parameter can be a value of @ref RTC_Month_Date_Definitions */
|
||||
|
||||
uint8_t Date; /*!< Specifies the RTC Date.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
|
||||
|
||||
uint8_t Year; /*!< Specifies the RTC Date Year.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
|
||||
|
||||
} RTC_DateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Alarm structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */
|
||||
|
||||
uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
|
||||
This parameter can be a value of @ref RTC_AlarmMask_Definitions */
|
||||
|
||||
uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks.
|
||||
This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
|
||||
|
||||
uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
|
||||
This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
|
||||
|
||||
uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
|
||||
If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
|
||||
If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
|
||||
|
||||
uint32_t Alarm; /*!< Specifies the alarm .
|
||||
This parameter can be a value of @ref RTC_Alarms_Definitions */
|
||||
} RTC_AlarmTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __RTC_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
|
||||
{
|
||||
RTC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
RTC_InitTypeDef Init; /*!< RTC required parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< RTC locking object */
|
||||
|
||||
__IO HAL_RTCStateTypeDef State; /*!< Time communication state */
|
||||
|
||||
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
|
||||
void (* AlarmAEventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm A Event callback */
|
||||
|
||||
void (* TimeStampEventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Timestamp Event callback */
|
||||
|
||||
#if defined(RTC_WAKEUP_SUPPORT)
|
||||
void (* WakeUpTimerEventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC WakeUpTimer Event callback */
|
||||
#endif /* RTC_WAKEUP_SUPPORT */
|
||||
|
||||
void (* Tamper1EventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 1 Event callback */
|
||||
|
||||
void (* Tamper2EventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 2 Event callback */
|
||||
|
||||
#if defined(RTC_TAMPER3_SUPPORT)
|
||||
void (* Tamper3EventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 3 Event callback */
|
||||
#endif /* RTC_TAMPER3_SUPPORT */
|
||||
|
||||
void (* MspInitCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp Init callback */
|
||||
|
||||
void (* MspDeInitCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp DeInit callback */
|
||||
|
||||
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
|
||||
|
||||
} RTC_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL RTC Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00U, /*!< RTC Alarm A Event Callback ID */
|
||||
HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02U, /*!< RTC Timestamp Event Callback ID */
|
||||
#if defined(RTC_WAKEUP_SUPPORT)
|
||||
HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03U, /*!< RTC Wakeup Timer Event Callback ID */
|
||||
#endif /* RTC_WAKEUP_SUPPORT */
|
||||
HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04U, /*!< RTC Tamper 1 Callback ID */
|
||||
HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05U, /*!< RTC Tamper 2 Callback ID */
|
||||
#if defined(RTC_TAMPER3_SUPPORT)
|
||||
HAL_RTC_TAMPER3_EVENT_CB_ID = 0x06U, /*!< RTC Tamper 3 Callback ID */
|
||||
#endif /* RTC_TAMPER3_SUPPORT */
|
||||
HAL_RTC_MSPINIT_CB_ID = 0x0EU, /*!< RTC Msp Init callback ID */
|
||||
HAL_RTC_MSPDEINIT_CB_ID = 0x0FU /*!< RTC Msp DeInit callback ID */
|
||||
} HAL_RTC_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL RTC Callback pointer definition
|
||||
*/
|
||||
typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to an RTC callback function */
|
||||
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RTC_Exported_Constants RTC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Hour_Formats RTC Hour Formats
|
||||
* @{
|
||||
*/
|
||||
#define RTC_HOURFORMAT_24 0x00000000U
|
||||
#define RTC_HOURFORMAT_12 RTC_CR_FMT
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Output_selection_Definitions RTC Output Selection Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OUTPUT_DISABLE 0x00000000U
|
||||
#define RTC_OUTPUT_ALARMA RTC_CR_OSEL_0
|
||||
#if defined(RTC_WAKEUP_SUPPORT)
|
||||
#define RTC_OUTPUT_WAKEUP RTC_CR_OSEL
|
||||
#endif /* RTC_WAKEUP_SUPPORT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OUTPUT_POLARITY_HIGH 0x00000000U
|
||||
#define RTC_OUTPUT_POLARITY_LOW RTC_CR_POL
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OUTPUT_TYPE_OPENDRAIN 0x00000000U
|
||||
#define RTC_OUTPUT_TYPE_PUSHPULL RTC_TAFCR_ALARMOUTTYPE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_HOURFORMAT12_AM ((uint8_t)0x00)
|
||||
#define RTC_HOURFORMAT12_PM ((uint8_t)0x01)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H
|
||||
#define RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H
|
||||
#define RTC_DAYLIGHTSAVING_NONE 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_STOREOPERATION_RESET 0x00000000U
|
||||
#define RTC_STOREOPERATION_SET RTC_CR_BKP
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_FORMAT_BIN 0x00000000U
|
||||
#define RTC_FORMAT_BCD 0x00000001U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions (in BCD format)
|
||||
* @{
|
||||
*/
|
||||
#define RTC_MONTH_JANUARY ((uint8_t)0x01)
|
||||
#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)
|
||||
#define RTC_MONTH_MARCH ((uint8_t)0x03)
|
||||
#define RTC_MONTH_APRIL ((uint8_t)0x04)
|
||||
#define RTC_MONTH_MAY ((uint8_t)0x05)
|
||||
#define RTC_MONTH_JUNE ((uint8_t)0x06)
|
||||
#define RTC_MONTH_JULY ((uint8_t)0x07)
|
||||
#define RTC_MONTH_AUGUST ((uint8_t)0x08)
|
||||
#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
|
||||
#define RTC_MONTH_OCTOBER ((uint8_t)0x10)
|
||||
#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)
|
||||
#define RTC_MONTH_DECEMBER ((uint8_t)0x12)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
|
||||
#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
|
||||
#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
|
||||
#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
|
||||
#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
|
||||
#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
|
||||
#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000U
|
||||
#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_ALARMMASK_NONE 0x00000000U
|
||||
#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
|
||||
#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
|
||||
#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
|
||||
#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
|
||||
#define RTC_ALARMMASK_ALL (RTC_ALARMMASK_DATEWEEKDAY | \
|
||||
RTC_ALARMMASK_HOURS | \
|
||||
RTC_ALARMMASK_MINUTES | \
|
||||
RTC_ALARMMASK_SECONDS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_ALARM_A RTC_CR_ALRAE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
|
||||
* @{
|
||||
*/
|
||||
/*!< All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm */
|
||||
#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000U
|
||||
/*!< SS[14:1] are don't care in Alarm comparison. Only SS[0] is compared. */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0
|
||||
/*!< SS[14:2] are don't care in Alarm comparison. Only SS[1:0] are compared. */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1
|
||||
/*!< SS[14:3] are don't care in Alarm comparison. Only SS[2:0] are compared. */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1)
|
||||
/*!< SS[14:4] are don't care in Alarm comparison. Only SS[3:0] are compared. */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2
|
||||
/*!< SS[14:5] are don't care in Alarm comparison. Only SS[4:0] are compared. */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2)
|
||||
/*!< SS[14:6] are don't care in Alarm comparison. Only SS[5:0] are compared. */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)
|
||||
/*!< SS[14:7] are don't care in Alarm comparison. Only SS[6:0] are compared. */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)
|
||||
/*!< SS[14:8] are don't care in Alarm comparison. Only SS[7:0] are compared. */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3
|
||||
/*!< SS[14:9] are don't care in Alarm comparison. Only SS[8:0] are compared. */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3)
|
||||
/*!< SS[14:10] are don't care in Alarm comparison. Only SS[9:0] are compared. */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)
|
||||
/*!< SS[14:11] are don't care in Alarm comparison. Only SS[10:0] are compared. */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)
|
||||
/*!< SS[14:12] are don't care in Alarm comparison. Only SS[11:0] are compared. */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
|
||||
/*!< SS[14:13] are don't care in Alarm comparison. Only SS[12:0] are compared. */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
|
||||
/*!< SS[14] is don't care in Alarm comparison. Only SS[13:0] are compared. */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
|
||||
/*!< SS[14:0] are compared and must match to activate alarm. */
|
||||
#define RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_IT_TS RTC_CR_TSIE /*!< Enable Timestamp Interrupt */
|
||||
#if defined(RTC_WAKEUP_SUPPORT)
|
||||
#define RTC_IT_WUT RTC_CR_WUTIE /*!< Enable Wakeup timer Interrupt */
|
||||
#endif /* RTC_WAKEUP_SUPPORT */
|
||||
#define RTC_IT_ALRA RTC_CR_ALRAIE /*!< Enable Alarm A Interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_FLAG_RECALPF RTC_ISR_RECALPF /*!< Recalibration pending flag */
|
||||
#if defined(RTC_TAMPER3_SUPPORT)
|
||||
#define RTC_FLAG_TAMP3F RTC_ISR_TAMP3F /*!< Tamper 3 event flag */
|
||||
#endif /* RTC_TAMPER3_SUPPORT */
|
||||
#define RTC_FLAG_TAMP2F RTC_ISR_TAMP2F /*!< Tamper 2 event flag */
|
||||
#define RTC_FLAG_TAMP1F RTC_ISR_TAMP1F /*!< Tamper 1 event flag */
|
||||
#define RTC_FLAG_TSOVF RTC_ISR_TSOVF /*!< Timestamp overflow flag */
|
||||
#define RTC_FLAG_TSF RTC_ISR_TSF /*!< Timestamp event flag */
|
||||
#if defined(RTC_WAKEUP_SUPPORT)
|
||||
#define RTC_FLAG_WUTF RTC_ISR_WUTF /*!< Wakeup timer event flag */
|
||||
#endif /* RTC_WAKEUP_SUPPORT */
|
||||
#define RTC_FLAG_ALRAF RTC_ISR_ALRAF /*!< Alarm A event flag */
|
||||
#define RTC_FLAG_INITF RTC_ISR_INITF /*!< RTC in initialization mode flag */
|
||||
#define RTC_FLAG_RSF RTC_ISR_RSF /*!< Register synchronization flag */
|
||||
#define RTC_FLAG_INITS RTC_ISR_INITS /*!< RTC initialization status flag */
|
||||
#define RTC_FLAG_SHPF RTC_ISR_SHPF /*!< Shift operation pending flag */
|
||||
#if defined(RTC_WAKEUP_SUPPORT)
|
||||
#define RTC_FLAG_WUTWF RTC_ISR_WUTWF /*!< WUTR register write allowance flag */
|
||||
#endif /* RTC_WAKEUP_SUPPORT */
|
||||
#define RTC_FLAG_ALRAWF RTC_ISR_ALRAWF /*!< ALRMAR register write allowance flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RTC_Exported_Macros RTC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset RTC handle state
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_RTC_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0U)
|
||||
#else
|
||||
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
|
||||
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Disable the write protection for RTC registers.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) do { \
|
||||
(__HANDLE__)->Instance->WPR = 0xCAU; \
|
||||
(__HANDLE__)->Instance->WPR = 0x53U; \
|
||||
} while(0U)
|
||||
|
||||
/**
|
||||
* @brief Enable the write protection for RTC registers.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) do { \
|
||||
(__HANDLE__)->Instance->WPR = 0xFFU; \
|
||||
} while(0U)
|
||||
|
||||
/**
|
||||
* @brief Check whether the RTC Calendar is initialized.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) (((((__HANDLE__)->Instance->ISR) & (RTC_FLAG_INITS)) == RTC_FLAG_INITS) ? 1U : 0U)
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC ALARMA peripheral.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC ALARMA peripheral.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC Alarm interrupt.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_IT_ALRA: Alarm A interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC Alarm interrupt.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_IT_ALRA: Alarm A interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC Alarm interrupt has occurred or not.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __INTERRUPT__ specifies the RTC Alarm interrupt to check.
|
||||
* This parameter can be:
|
||||
* @arg RTC_IT_ALRA: Alarm A interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4U)) != 0U) ? 1U : 0U)
|
||||
|
||||
/**
|
||||
* @brief Get the selected RTC Alarm's flag status.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __FLAG__ specifies the RTC Alarm Flag to check.
|
||||
* This parameter can be:
|
||||
* @arg RTC_FLAG_ALRAF: Alarm A interrupt flag
|
||||
* @arg RTC_FLAG_ALRAWF: Alarm A 'write allowed' flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)
|
||||
|
||||
/**
|
||||
* @brief Clear the RTC Alarm's pending flags.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __FLAG__ specifies the RTC Alarm flag to be cleared.
|
||||
* This parameter can be:
|
||||
* @arg RTC_FLAG_ALRAF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC Alarm interrupt has been enabled or not.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
|
||||
* This parameter can be:
|
||||
* @arg RTC_IT_ALRA: Alarm A interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
|
||||
|
||||
/**
|
||||
* @brief Enable interrupt on the RTC Alarm associated EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable interrupt on the RTC Alarm associated EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Enable event on the RTC Alarm associated EXTI line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable event on the RTC Alarm associated EXTI line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Enable falling edge trigger on the RTC Alarm associated EXTI line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable falling edge trigger on the RTC Alarm associated EXTI line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Enable rising edge trigger on the RTC Alarm associated EXTI line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable rising edge trigger on the RTC Alarm associated EXTI line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Enable rising & falling edge trigger on the RTC Alarm associated EXTI line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
|
||||
__HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \
|
||||
__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \
|
||||
} while(0U)
|
||||
|
||||
/**
|
||||
* @brief Disable rising & falling edge trigger on the RTC Alarm associated EXTI line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
|
||||
__HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE(); \
|
||||
__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \
|
||||
} while(0U)
|
||||
|
||||
/**
|
||||
* @brief Check whether the RTC Alarm associated EXTI line interrupt flag is set or not.
|
||||
* @retval Line Status.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Clear the RTC Alarm associated EXTI line flag.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on RTC Alarm associated EXTI line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include RTC HAL Extended module */
|
||||
#include "stm32f0xx_hal_rtc_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup RTC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* RTC Time and Date functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* RTC Alarm functions ********************************************************/
|
||||
HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
|
||||
HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
|
||||
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
|
||||
void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc);
|
||||
|
||||
/* RTC Daylight Saving Time functions *****************************************/
|
||||
void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc);
|
||||
uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Exported_Functions_Group5
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions *************************************************/
|
||||
HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RTC_Private_Constants RTC Private Constants
|
||||
* @{
|
||||
*/
|
||||
/* Masks Definition */
|
||||
#define RTC_TR_RESERVED_MASK ((uint32_t)(RTC_TR_HT | RTC_TR_HU | \
|
||||
RTC_TR_MNT | RTC_TR_MNU | \
|
||||
RTC_TR_ST | RTC_TR_SU | \
|
||||
RTC_TR_PM))
|
||||
#define RTC_DR_RESERVED_MASK ((uint32_t)(RTC_DR_YT | RTC_DR_YU | \
|
||||
RTC_DR_MT | RTC_DR_MU | \
|
||||
RTC_DR_DT | RTC_DR_DU | \
|
||||
RTC_DR_WDU))
|
||||
#define RTC_ISR_RESERVED_MASK ((uint32_t)(RTC_FLAGS_MASK | RTC_ISR_INIT))
|
||||
#define RTC_INIT_MASK 0xFFFFFFFFU
|
||||
#define RTC_RSF_MASK ((uint32_t)~(RTC_ISR_INIT | RTC_ISR_RSF))
|
||||
#if defined(RTC_WAKEUP_SUPPORT)
|
||||
#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_INITF | RTC_FLAG_INITS | \
|
||||
RTC_FLAG_ALRAF | RTC_FLAG_ALRAWF | \
|
||||
RTC_FLAG_WUTF | RTC_FLAG_WUTWF | \
|
||||
RTC_FLAG_RECALPF | RTC_FLAG_SHPF | \
|
||||
RTC_FLAG_TSF | RTC_FLAG_TSOVF | \
|
||||
RTC_FLAG_RSF | RTC_TAMPER_FLAGS_MASK))
|
||||
#else /* RTC_WAKEUP_SUPPORT */
|
||||
#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_INITF | RTC_FLAG_INITS | \
|
||||
RTC_FLAG_ALRAF | RTC_FLAG_ALRAWF | \
|
||||
RTC_FLAG_RECALPF | RTC_FLAG_SHPF | \
|
||||
RTC_FLAG_TSF | RTC_FLAG_TSOVF | \
|
||||
RTC_FLAG_RSF | RTC_TAMPER_FLAGS_MASK))
|
||||
#endif /* RTC_WAKEUP_SUPPORT */
|
||||
|
||||
#define RTC_TIMEOUT_VALUE 1000U
|
||||
|
||||
#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR_MR17 /*!< External interrupt line 17 connected to the RTC Alarm event */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RTC_Private_Macros RTC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \
|
||||
((FORMAT) == RTC_HOURFORMAT_24))
|
||||
|
||||
#if defined(RTC_WAKEUP_SUPPORT)
|
||||
#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
|
||||
((OUTPUT) == RTC_OUTPUT_ALARMA) || \
|
||||
((OUTPUT) == RTC_OUTPUT_WAKEUP))
|
||||
#else /* RTC_WAKEUP_SUPPORT */
|
||||
#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
|
||||
((OUTPUT) == RTC_OUTPUT_ALARMA))
|
||||
#endif /* RTC_WAKEUP_SUPPORT */
|
||||
|
||||
#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
|
||||
((POL) == RTC_OUTPUT_POLARITY_LOW))
|
||||
|
||||
#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
|
||||
((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
|
||||
|
||||
#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FU)
|
||||
#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFFU)
|
||||
|
||||
#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0U) && ((HOUR) <= 12U))
|
||||
#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U)
|
||||
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U)
|
||||
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U)
|
||||
|
||||
#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || \
|
||||
((PM) == RTC_HOURFORMAT12_PM))
|
||||
|
||||
#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
|
||||
((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
|
||||
((SAVE) == RTC_DAYLIGHTSAVING_NONE))
|
||||
|
||||
#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
|
||||
((OPERATION) == RTC_STOREOPERATION_SET))
|
||||
|
||||
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
|
||||
|
||||
#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99U)
|
||||
#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U))
|
||||
#define IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U))
|
||||
|
||||
#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
|
||||
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0U) && ((DATE) <= 31U))
|
||||
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
|
||||
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
|
||||
((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
|
||||
|
||||
#define IS_RTC_ALARM_MASK(MASK) (((MASK) & ((uint32_t)~RTC_ALARMMASK_ALL)) == 0U)
|
||||
|
||||
#define IS_RTC_ALARM(ALARM) ((ALARM) == RTC_ALARM_A)
|
||||
|
||||
#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS)
|
||||
|
||||
#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_NONE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RTC_Private_Functions RTC Private Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc);
|
||||
uint8_t RTC_ByteToBcd2(uint8_t number);
|
||||
uint8_t RTC_Bcd2ToByte(uint8_t number);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F0xx_HAL_RTC_H */
|
||||
1028
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rtc_ex.h
Normal file
1028
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rtc_ex.h
Normal file
File diff suppressed because it is too large
Load Diff
1057
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_smartcard.h
Normal file
1057
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_smartcard.h
Normal file
File diff suppressed because it is too large
Load Diff
569
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_smartcard_ex.h
Normal file
569
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_smartcard_ex.h
Normal file
@@ -0,0 +1,569 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_smartcard_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of SMARTCARD HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F0xx_HAL_SMARTCARD_EX_H
|
||||
#define STM32F0xx_HAL_SMARTCARD_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) \
|
||||
&& !defined(STM32F070xB) && !defined(STM32F030xC)
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SMARTCARDEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup SMARTCARDEx_Exported_Constants SMARTCARD Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARDEx_Transmission_Completion_Indication SMARTCARD Transmission Completion Indication
|
||||
* @{
|
||||
*/
|
||||
#if defined(USART_TCBGT_SUPPORT)
|
||||
#define SMARTCARD_TCBGT SMARTCARD_IT_TCBGT /*!< SMARTCARD transmission complete before guard time */
|
||||
#endif /* USART_TCBGT_SUPPORT */
|
||||
#define SMARTCARD_TC SMARTCARD_IT_TC /*!< SMARTCARD transmission complete (flag raised when guard time has elapsed) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARDEx_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */
|
||||
#define SMARTCARD_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */
|
||||
#define SMARTCARD_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */
|
||||
#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */
|
||||
#define SMARTCARD_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */
|
||||
#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */
|
||||
#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */
|
||||
#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */
|
||||
#if defined(USART_TCBGT_SUPPORT)
|
||||
#define SMARTCARD_ADVFEATURE_TXCOMPLETION 0x00000100U /*!< TX completion indication before of after guard time */
|
||||
#endif /* USART_TCBGT_SUPPORT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARDEx_Flags SMARTCARD Flags
|
||||
* Elements values convention: 0xXXXX
|
||||
* - 0xXXXX : Flag mask in the ISR register
|
||||
* @{
|
||||
*/
|
||||
#if defined(USART_TCBGT_SUPPORT)
|
||||
#define SMARTCARD_FLAG_TCBGT USART_ISR_TCBGT /*!< SMARTCARD transmission complete before guard time completion */
|
||||
#endif /* USART_TCBGT_SUPPORT */
|
||||
#define SMARTCARD_FLAG_REACK USART_ISR_REACK /*!< SMARTCARD receive enable acknowledge flag */
|
||||
#define SMARTCARD_FLAG_TEACK USART_ISR_TEACK /*!< SMARTCARD transmit enable acknowledge flag */
|
||||
#define SMARTCARD_FLAG_BUSY USART_ISR_BUSY /*!< SMARTCARD busy flag */
|
||||
#define SMARTCARD_FLAG_EOBF USART_ISR_EOBF /*!< SMARTCARD end of block flag */
|
||||
#define SMARTCARD_FLAG_RTOF USART_ISR_RTOF /*!< SMARTCARD receiver timeout flag */
|
||||
#define SMARTCARD_FLAG_TXE USART_ISR_TXE /*!< SMARTCARD transmit data register empty */
|
||||
#define SMARTCARD_FLAG_TC USART_ISR_TC /*!< SMARTCARD transmission complete */
|
||||
#define SMARTCARD_FLAG_RXNE USART_ISR_RXNE /*!< SMARTCARD read data register not empty */
|
||||
#define SMARTCARD_FLAG_IDLE USART_ISR_IDLE /*!< SMARTCARD idle line detection */
|
||||
#define SMARTCARD_FLAG_ORE USART_ISR_ORE /*!< SMARTCARD overrun error */
|
||||
#define SMARTCARD_FLAG_NE USART_ISR_NE /*!< SMARTCARD noise error */
|
||||
#define SMARTCARD_FLAG_FE USART_ISR_FE /*!< SMARTCARD frame error */
|
||||
#define SMARTCARD_FLAG_PE USART_ISR_PE /*!< SMARTCARD parity error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARDEx_Interrupt_definition SMARTCARD Interrupts Definition
|
||||
* Elements values convention: 000ZZZZZ0XXYYYYYb
|
||||
* - YYYYY : Interrupt source position in the XX register (5 bits)
|
||||
* - XX : Interrupt source register (2 bits)
|
||||
* - 01: CR1 register
|
||||
* - 10: CR2 register
|
||||
* - 11: CR3 register
|
||||
* - ZZZZZ : Flag position in the ISR register(5 bits)
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_IT_PE 0x0028U /*!< SMARTCARD parity error interruption */
|
||||
#define SMARTCARD_IT_TXE 0x0727U /*!< SMARTCARD transmit data register empty interruption */
|
||||
#define SMARTCARD_IT_TC 0x0626U /*!< SMARTCARD transmission complete interruption */
|
||||
#define SMARTCARD_IT_RXNE 0x0525U /*!< SMARTCARD read data register not empty interruption */
|
||||
#define SMARTCARD_IT_IDLE 0x0424U /*!< SMARTCARD idle line detection interruption */
|
||||
|
||||
#define SMARTCARD_IT_ERR 0x0060U /*!< SMARTCARD error interruption */
|
||||
#define SMARTCARD_IT_ORE 0x0300U /*!< SMARTCARD overrun error interruption */
|
||||
#define SMARTCARD_IT_NE 0x0200U /*!< SMARTCARD noise error interruption */
|
||||
#define SMARTCARD_IT_FE 0x0100U /*!< SMARTCARD frame error interruption */
|
||||
|
||||
#define SMARTCARD_IT_EOB 0x0C3BU /*!< SMARTCARD end of block interruption */
|
||||
#define SMARTCARD_IT_RTO 0x0B3AU /*!< SMARTCARD receiver timeout interruption */
|
||||
#if defined(USART_TCBGT_SUPPORT)
|
||||
#define SMARTCARD_IT_TCBGT 0x1978U /*!< SMARTCARD transmission complete before guard time completion interruption */
|
||||
#endif /* USART_TCBGT_SUPPORT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARDEx_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< SMARTCARD parity error clear flag */
|
||||
#define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< SMARTCARD framing error clear flag */
|
||||
#define SMARTCARD_CLEAR_NEF USART_ICR_NCF /*!< SMARTCARD noise error detected clear flag */
|
||||
#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< SMARTCARD overrun error clear flag */
|
||||
#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF /*!< SMARTCARD idle line detected clear flag */
|
||||
#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< SMARTCARD transmission complete clear flag */
|
||||
#if defined(USART_TCBGT_SUPPORT)
|
||||
#define SMARTCARD_CLEAR_TCBGTF USART_ICR_TCBGTCF /*!< SMARTCARD transmission complete before guard time completion clear flag */
|
||||
#endif /* USART_TCBGT_SUPPORT */
|
||||
#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< SMARTCARD receiver time out clear flag */
|
||||
#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< SMARTCARD end of block clear flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Report the SMARTCARD clock source.
|
||||
* @param __HANDLE__ specifies the SMARTCARD Handle.
|
||||
* @param __CLOCKSOURCE__ output variable.
|
||||
* @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
|
||||
*/
|
||||
#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx)
|
||||
#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} while(0)
|
||||
#elif defined (STM32F030x8) || defined (STM32F070x6) || defined (STM32F042x6) || defined (STM32F048xx) \
|
||||
|| defined (STM32F051x8) || defined (STM32F058xx)
|
||||
#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0)
|
||||
#elif defined (STM32F070xB)
|
||||
#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART4) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0)
|
||||
#elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
|
||||
#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART4) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0)
|
||||
#elif defined(STM32F091xC) || defined (STM32F098xx)
|
||||
#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART3_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART3CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART4) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART5) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART6) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART7) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART8) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0)
|
||||
#elif defined(STM32F030xC)
|
||||
#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART4) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART5) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART6) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0)
|
||||
#endif /* defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) */
|
||||
|
||||
/** @brief Set the Transmission Completion flag
|
||||
* @param __HANDLE__ specifies the SMARTCARD Handle.
|
||||
* @note If TCBGT (Transmission Complete Before Guard Time) flag is not available or if
|
||||
* AdvancedInit.TxCompletionIndication is not already filled, the latter is forced
|
||||
* to SMARTCARD_TC (transmission completion indication when guard time has elapsed).
|
||||
* @retval None
|
||||
*/
|
||||
#if defined(USART_TCBGT_SUPPORT)
|
||||
#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__) \
|
||||
do { \
|
||||
if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION)) \
|
||||
{ \
|
||||
(__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \
|
||||
} \
|
||||
} while(0U)
|
||||
#else
|
||||
#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__) \
|
||||
do { \
|
||||
(__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \
|
||||
} while(0U)
|
||||
#endif /* USART_TCBGT_SUPPORT */
|
||||
|
||||
/** @brief Return the transmission completion flag.
|
||||
* @param __HANDLE__ specifies the SMARTCARD Handle.
|
||||
* @note Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag.
|
||||
* When TCBGT flag (Transmission Complete Before Guard Time) is not available, TC flag is
|
||||
* reported.
|
||||
* @retval Transmission completion flag
|
||||
*/
|
||||
#if defined(USART_TCBGT_SUPPORT)
|
||||
#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) \
|
||||
(((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT))
|
||||
#else
|
||||
#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) (SMARTCARD_FLAG_TC)
|
||||
#endif /* USART_TCBGT_SUPPORT */
|
||||
|
||||
|
||||
/** @brief Ensure that SMARTCARD frame transmission completion used flag is valid.
|
||||
* @param __TXCOMPLETE__ SMARTCARD frame transmission completion used flag.
|
||||
* @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid)
|
||||
*/
|
||||
#if defined(USART_TCBGT_SUPPORT)
|
||||
#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) (((__TXCOMPLETE__) == SMARTCARD_TCBGT) || \
|
||||
((__TXCOMPLETE__) == SMARTCARD_TC))
|
||||
#else
|
||||
#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) ((__TXCOMPLETE__) == SMARTCARD_TC)
|
||||
#endif /* USART_TCBGT_SUPPORT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup SMARTCARDEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
/* IO operation methods *******************************************************/
|
||||
|
||||
/** @addtogroup SMARTCARDEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength);
|
||||
void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue);
|
||||
HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup SMARTCARDEx_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* !STM32F030x6 && !STM32F030x8 && !STM32F070x6 && !STM32F070xB && !STM32F030xC */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F0xx_HAL_SMARTCARD_EX_H */
|
||||
|
||||
787
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_smbus.h
Normal file
787
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_smbus.h
Normal file
@@ -0,0 +1,787 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_smbus.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of SMBUS HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F0xx_HAL_SMBUS_H
|
||||
#define STM32F0xx_HAL_SMBUS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SMBUS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup SMBUS_Exported_Types SMBUS Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition
|
||||
* @brief SMBUS Configuration Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value.
|
||||
This parameter calculated by referring to SMBUS initialization section
|
||||
in Reference manual */
|
||||
uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not.
|
||||
This parameter can be a value of @ref SMBUS_Analog_Filter */
|
||||
|
||||
uint32_t OwnAddress1; /*!< Specifies the first device own address.
|
||||
This parameter can be a 7-bit or 10-bit address. */
|
||||
|
||||
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
|
||||
This parameter can be a value of @ref SMBUS_addressing_mode */
|
||||
|
||||
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
|
||||
This parameter can be a value of @ref SMBUS_dual_addressing_mode */
|
||||
|
||||
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
|
||||
This parameter can be a 7-bit address. */
|
||||
|
||||
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address
|
||||
if dual addressing mode is selected
|
||||
This parameter can be a value of @ref SMBUS_own_address2_masks. */
|
||||
|
||||
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
|
||||
This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
|
||||
|
||||
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
|
||||
This parameter can be a value of @ref SMBUS_nostretch_mode */
|
||||
|
||||
uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected.
|
||||
This parameter can be a value of @ref SMBUS_packet_error_check_mode */
|
||||
|
||||
uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected.
|
||||
This parameter can be a value of @ref SMBUS_peripheral_mode */
|
||||
|
||||
uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
|
||||
(Enable bits and different timeout values)
|
||||
This parameter calculated by referring to SMBUS initialization section
|
||||
in Reference manual */
|
||||
} SMBUS_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_state_definition HAL state definition
|
||||
* @brief HAL State definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_SMBUS_STATE_RESET (0x00000000U) /*!< SMBUS not yet initialized or disabled */
|
||||
#define HAL_SMBUS_STATE_READY (0x00000001U) /*!< SMBUS initialized and ready for use */
|
||||
#define HAL_SMBUS_STATE_BUSY (0x00000002U) /*!< SMBUS internal process is ongoing */
|
||||
#define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */
|
||||
#define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */
|
||||
#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */
|
||||
#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */
|
||||
#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition
|
||||
* @brief SMBUS Error Code definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_SMBUS_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_SMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */
|
||||
#define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */
|
||||
#define HAL_SMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */
|
||||
#define HAL_SMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */
|
||||
#define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */
|
||||
#define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */
|
||||
#define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */
|
||||
#define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */
|
||||
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
|
||||
#define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition
|
||||
* @brief SMBUS handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __SMBUS_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
|
||||
{
|
||||
I2C_TypeDef *Instance; /*!< SMBUS registers base address */
|
||||
|
||||
SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */
|
||||
|
||||
uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */
|
||||
|
||||
uint16_t XferSize; /*!< SMBUS transfer size */
|
||||
|
||||
__IO uint16_t XferCount; /*!< SMBUS transfer counter */
|
||||
|
||||
__IO uint32_t XferOptions; /*!< SMBUS transfer options */
|
||||
|
||||
__IO uint32_t PreviousState; /*!< SMBUS communication Previous state */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< SMBUS locking object */
|
||||
|
||||
__IO uint32_t State; /*!< SMBUS communication state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< SMBUS Error code */
|
||||
|
||||
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
|
||||
void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
|
||||
/*!< SMBUS Master Tx Transfer completed callback */
|
||||
void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
|
||||
/*!< SMBUS Master Rx Transfer completed callback */
|
||||
void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
|
||||
/*!< SMBUS Slave Tx Transfer completed callback */
|
||||
void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
|
||||
/*!< SMBUS Slave Rx Transfer completed callback */
|
||||
void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
|
||||
/*!< SMBUS Listen Complete callback */
|
||||
void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
|
||||
/*!< SMBUS Error callback */
|
||||
|
||||
void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
|
||||
/*!< SMBUS Slave Address Match callback */
|
||||
|
||||
void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
|
||||
/*!< SMBUS Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
|
||||
/*!< SMBUS Msp DeInit callback */
|
||||
|
||||
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
|
||||
} SMBUS_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL SMBUS Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< SMBUS Master Tx Transfer completed callback ID */
|
||||
HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< SMBUS Master Rx Transfer completed callback ID */
|
||||
HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< SMBUS Slave Tx Transfer completed callback ID */
|
||||
HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< SMBUS Slave Rx Transfer completed callback ID */
|
||||
HAL_SMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< SMBUS Listen Complete callback ID */
|
||||
HAL_SMBUS_ERROR_CB_ID = 0x05U, /*!< SMBUS Error callback ID */
|
||||
|
||||
HAL_SMBUS_MSPINIT_CB_ID = 0x06U, /*!< SMBUS Msp Init callback ID */
|
||||
HAL_SMBUS_MSPDEINIT_CB_ID = 0x07U /*!< SMBUS Msp DeInit callback ID */
|
||||
|
||||
} HAL_SMBUS_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL SMBUS Callback pointer definition
|
||||
*/
|
||||
typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus);
|
||||
/*!< pointer to an SMBUS callback function */
|
||||
typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection,
|
||||
uint16_t AddrMatchCode);
|
||||
/*!< pointer to an SMBUS Address Match callback function */
|
||||
|
||||
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
|
||||
* @{
|
||||
*/
|
||||
#define SMBUS_ANALOGFILTER_ENABLE (0x00000000U)
|
||||
#define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_addressing_mode SMBUS addressing mode
|
||||
* @{
|
||||
*/
|
||||
#define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
|
||||
#define SMBUS_ADDRESSINGMODE_10BIT (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SMBUS_DUALADDRESS_DISABLE (0x00000000U)
|
||||
#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SMBUS_OA2_NOMASK ((uint8_t)0x00U)
|
||||
#define SMBUS_OA2_MASK01 ((uint8_t)0x01U)
|
||||
#define SMBUS_OA2_MASK02 ((uint8_t)0x02U)
|
||||
#define SMBUS_OA2_MASK03 ((uint8_t)0x03U)
|
||||
#define SMBUS_OA2_MASK04 ((uint8_t)0x04U)
|
||||
#define SMBUS_OA2_MASK05 ((uint8_t)0x05U)
|
||||
#define SMBUS_OA2_MASK06 ((uint8_t)0x06U)
|
||||
#define SMBUS_OA2_MASK07 ((uint8_t)0x07U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
|
||||
* @{
|
||||
*/
|
||||
#define SMBUS_GENERALCALL_DISABLE (0x00000000U)
|
||||
#define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
|
||||
* @{
|
||||
*/
|
||||
#define SMBUS_NOSTRETCH_DISABLE (0x00000000U)
|
||||
#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
|
||||
* @{
|
||||
*/
|
||||
#define SMBUS_PEC_DISABLE (0x00000000U)
|
||||
#define SMBUS_PEC_ENABLE I2C_CR1_PECEN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
|
||||
* @{
|
||||
*/
|
||||
#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN
|
||||
#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)
|
||||
#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SMBUS_SOFTEND_MODE (0x00000000U)
|
||||
#define SMBUS_RELOAD_MODE I2C_CR2_RELOAD
|
||||
#define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
|
||||
#define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SMBUS_NO_STARTSTOP (0x00000000U)
|
||||
#define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
|
||||
#define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
|
||||
#define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* List of XferOptions in usage of :
|
||||
* 1- Restart condition when direction change
|
||||
* 2- No Restart condition in other use cases
|
||||
*/
|
||||
#define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE
|
||||
#define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
|
||||
#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
|
||||
#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
|
||||
#define SMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE))
|
||||
#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
|
||||
#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
|
||||
|
||||
/* List of XferOptions in usage of :
|
||||
* 1- Restart condition in all use cases (direction change or not)
|
||||
*/
|
||||
#define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)
|
||||
#define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)
|
||||
#define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)
|
||||
#define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
|
||||
* @brief SMBUS Interrupt definition
|
||||
* Elements values convention: 0xXXXXXXXX
|
||||
* - XXXXXXXX : Interrupt control mask
|
||||
* @{
|
||||
*/
|
||||
#define SMBUS_IT_ERRI I2C_CR1_ERRIE
|
||||
#define SMBUS_IT_TCI I2C_CR1_TCIE
|
||||
#define SMBUS_IT_STOPI I2C_CR1_STOPIE
|
||||
#define SMBUS_IT_NACKI I2C_CR1_NACKIE
|
||||
#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE
|
||||
#define SMBUS_IT_RXI I2C_CR1_RXIE
|
||||
#define SMBUS_IT_TXI I2C_CR1_TXIE
|
||||
#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | \
|
||||
SMBUS_IT_NACKI | SMBUS_IT_TXI)
|
||||
#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | \
|
||||
SMBUS_IT_RXI)
|
||||
#define SMBUS_IT_ALERT (SMBUS_IT_ERRI)
|
||||
#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_Flag_definition SMBUS Flag definition
|
||||
* @brief Flag definition
|
||||
* Elements values convention: 0xXXXXYYYY
|
||||
* - XXXXXXXX : Flag mask
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SMBUS_FLAG_TXE I2C_ISR_TXE
|
||||
#define SMBUS_FLAG_TXIS I2C_ISR_TXIS
|
||||
#define SMBUS_FLAG_RXNE I2C_ISR_RXNE
|
||||
#define SMBUS_FLAG_ADDR I2C_ISR_ADDR
|
||||
#define SMBUS_FLAG_AF I2C_ISR_NACKF
|
||||
#define SMBUS_FLAG_STOPF I2C_ISR_STOPF
|
||||
#define SMBUS_FLAG_TC I2C_ISR_TC
|
||||
#define SMBUS_FLAG_TCR I2C_ISR_TCR
|
||||
#define SMBUS_FLAG_BERR I2C_ISR_BERR
|
||||
#define SMBUS_FLAG_ARLO I2C_ISR_ARLO
|
||||
#define SMBUS_FLAG_OVR I2C_ISR_OVR
|
||||
#define SMBUS_FLAG_PECERR I2C_ISR_PECERR
|
||||
#define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
|
||||
#define SMBUS_FLAG_ALERT I2C_ISR_ALERT
|
||||
#define SMBUS_FLAG_BUSY I2C_ISR_BUSY
|
||||
#define SMBUS_FLAG_DIR I2C_ISR_DIR
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros ------------------------------------------------------------*/
|
||||
/** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset SMBUS handle state.
|
||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
|
||||
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Enable the specified SMBUS interrupts.
|
||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref SMBUS_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref SMBUS_IT_RXI RX interrupt enable
|
||||
* @arg @ref SMBUS_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable the specified SMBUS interrupts.
|
||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref SMBUS_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref SMBUS_IT_RXI RX interrupt enable
|
||||
* @arg @ref SMBUS_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Check whether the specified SMBUS interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
||||
* @param __INTERRUPT__ specifies the SMBUS interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref SMBUS_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref SMBUS_IT_RXI RX interrupt enable
|
||||
* @arg @ref SMBUS_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval The new state of __IT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
|
||||
((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified SMBUS flag is set or not.
|
||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref SMBUS_FLAG_TXE Transmit data register empty
|
||||
* @arg @ref SMBUS_FLAG_TXIS Transmit interrupt status
|
||||
* @arg @ref SMBUS_FLAG_RXNE Receive data register not empty
|
||||
* @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode)
|
||||
* @arg @ref SMBUS_FLAG_AF NACK received flag
|
||||
* @arg @ref SMBUS_FLAG_STOPF STOP detection flag
|
||||
* @arg @ref SMBUS_FLAG_TC Transfer complete (master mode)
|
||||
* @arg @ref SMBUS_FLAG_TCR Transfer complete reload
|
||||
* @arg @ref SMBUS_FLAG_BERR Bus error
|
||||
* @arg @ref SMBUS_FLAG_ARLO Arbitration lost
|
||||
* @arg @ref SMBUS_FLAG_OVR Overrun/Underrun
|
||||
* @arg @ref SMBUS_FLAG_PECERR PEC error in reception
|
||||
* @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
|
||||
* @arg @ref SMBUS_FLAG_ALERT SMBus alert
|
||||
* @arg @ref SMBUS_FLAG_BUSY Bus busy
|
||||
* @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode)
|
||||
*
|
||||
* @retval The new state of __FLAG__ (SET or RESET).
|
||||
*/
|
||||
#define SMBUS_FLAG_MASK (0x0001FFFFU)
|
||||
#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) \
|
||||
(((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
|
||||
((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
|
||||
|
||||
/** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
|
||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref SMBUS_FLAG_TXE Transmit data register empty
|
||||
* @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode)
|
||||
* @arg @ref SMBUS_FLAG_AF NACK received flag
|
||||
* @arg @ref SMBUS_FLAG_STOPF STOP detection flag
|
||||
* @arg @ref SMBUS_FLAG_BERR Bus error
|
||||
* @arg @ref SMBUS_FLAG_ARLO Arbitration lost
|
||||
* @arg @ref SMBUS_FLAG_OVR Overrun/Underrun
|
||||
* @arg @ref SMBUS_FLAG_PECERR PEC error in reception
|
||||
* @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
|
||||
* @arg @ref SMBUS_FLAG_ALERT SMBus alert
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == SMBUS_FLAG_TXE) ? \
|
||||
((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
|
||||
((__HANDLE__)->Instance->ICR = (__FLAG__)))
|
||||
|
||||
/** @brief Enable the specified SMBUS peripheral.
|
||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
|
||||
|
||||
/** @brief Disable the specified SMBUS peripheral.
|
||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
|
||||
|
||||
/** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
|
||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup SMBUS_Private_Macro SMBUS Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
|
||||
((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
|
||||
|
||||
#define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
|
||||
|
||||
#define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \
|
||||
((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
|
||||
|
||||
#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
|
||||
((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
|
||||
|
||||
#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \
|
||||
((MASK) == SMBUS_OA2_MASK01) || \
|
||||
((MASK) == SMBUS_OA2_MASK02) || \
|
||||
((MASK) == SMBUS_OA2_MASK03) || \
|
||||
((MASK) == SMBUS_OA2_MASK04) || \
|
||||
((MASK) == SMBUS_OA2_MASK05) || \
|
||||
((MASK) == SMBUS_OA2_MASK06) || \
|
||||
((MASK) == SMBUS_OA2_MASK07))
|
||||
|
||||
#define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
|
||||
((CALL) == SMBUS_GENERALCALL_ENABLE))
|
||||
|
||||
#define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
|
||||
((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
|
||||
|
||||
#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \
|
||||
((PEC) == SMBUS_PEC_ENABLE))
|
||||
|
||||
#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \
|
||||
((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
|
||||
((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
|
||||
|
||||
#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
|
||||
((MODE) == SMBUS_AUTOEND_MODE) || \
|
||||
((MODE) == SMBUS_SOFTEND_MODE) || \
|
||||
((MODE) == SMBUS_SENDPEC_MODE) || \
|
||||
((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
|
||||
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
|
||||
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
|
||||
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | \
|
||||
SMBUS_RELOAD_MODE )))
|
||||
|
||||
|
||||
#define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \
|
||||
((REQUEST) == SMBUS_GENERATE_START_READ) || \
|
||||
((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
|
||||
((REQUEST) == SMBUS_NO_STARTSTOP))
|
||||
|
||||
|
||||
#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
|
||||
((REQUEST) == SMBUS_FIRST_FRAME) || \
|
||||
((REQUEST) == SMBUS_NEXT_FRAME) || \
|
||||
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
|
||||
((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
|
||||
((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \
|
||||
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
|
||||
((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
|
||||
|
||||
#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \
|
||||
((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
|
||||
((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \
|
||||
((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
|
||||
|
||||
#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \
|
||||
(uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | \
|
||||
I2C_CR1_PECEN)))
|
||||
#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
|
||||
(uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
|
||||
I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
|
||||
I2C_CR2_RD_WRN)))
|
||||
|
||||
#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
|
||||
(I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
|
||||
(~I2C_CR2_RD_WRN)) : \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & \
|
||||
(I2C_CR2_SADD)) | (I2C_CR2_ADD10) | \
|
||||
(I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
|
||||
|
||||
#define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
|
||||
#define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
|
||||
#define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
|
||||
#define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
|
||||
#define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
|
||||
|
||||
#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
|
||||
((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
|
||||
#define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
|
||||
|
||||
#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
|
||||
#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
|
||||
HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
|
||||
HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter);
|
||||
HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus,
|
||||
HAL_SMBUS_CallbackIDTypeDef CallbackID,
|
||||
pSMBUS_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus,
|
||||
HAL_SMBUS_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus,
|
||||
pSMBUS_AddrCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus);
|
||||
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
/** @addtogroup Blocking_mode_Polling Blocking mode Polling
|
||||
* @{
|
||||
*/
|
||||
/******* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials,
|
||||
uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
|
||||
* @{
|
||||
*/
|
||||
/******* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
|
||||
uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
|
||||
uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
|
||||
HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
|
||||
HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
|
||||
HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
|
||||
HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
|
||||
HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
|
||||
* @{
|
||||
*/
|
||||
/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
|
||||
void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
|
||||
void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral State and Errors functions **************************************************/
|
||||
uint32_t HAL_SMBUS_GetState(const SMBUS_HandleTypeDef *hsmbus);
|
||||
uint32_t HAL_SMBUS_GetError(const SMBUS_HandleTypeDef *hsmbus);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Functions ---------------------------------------------------------*/
|
||||
/** @defgroup SMBUS_Private_Functions SMBUS Private Functions
|
||||
* @{
|
||||
*/
|
||||
/* Private functions are defined in stm32f0xx_hal_smbus.c file */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32F0xx_HAL_SMBUS_H */
|
||||
851
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_spi.h
Normal file
851
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_spi.h
Normal file
@@ -0,0 +1,851 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_spi.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of SPI HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F0xx_HAL_SPI_H
|
||||
#define STM32F0xx_HAL_SPI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup SPI_Exported_Types SPI Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief SPI Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Mode; /*!< Specifies the SPI operating mode.
|
||||
This parameter can be a value of @ref SPI_Mode */
|
||||
|
||||
uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
|
||||
This parameter can be a value of @ref SPI_Direction */
|
||||
|
||||
uint32_t DataSize; /*!< Specifies the SPI data size.
|
||||
This parameter can be a value of @ref SPI_Data_Size */
|
||||
|
||||
uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
|
||||
This parameter can be a value of @ref SPI_Clock_Polarity */
|
||||
|
||||
uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
|
||||
This parameter can be a value of @ref SPI_Clock_Phase */
|
||||
|
||||
uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
|
||||
hardware (NSS pin) or by software using the SSI bit.
|
||||
This parameter can be a value of @ref SPI_Slave_Select_management */
|
||||
|
||||
uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
|
||||
used to configure the transmit and receive SCK clock.
|
||||
This parameter can be a value of @ref SPI_BaudRate_Prescaler
|
||||
@note The communication clock is derived from the master
|
||||
clock. The slave clock does not need to be set. */
|
||||
|
||||
uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
|
||||
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
|
||||
|
||||
uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
|
||||
This parameter can be a value of @ref SPI_TI_mode */
|
||||
|
||||
uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
|
||||
This parameter can be a value of @ref SPI_CRC_Calculation */
|
||||
|
||||
uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
|
||||
This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */
|
||||
|
||||
uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
|
||||
CRC Length is only used with Data8 and Data16, not other data size
|
||||
This parameter can be a value of @ref SPI_CRC_length */
|
||||
|
||||
uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
|
||||
This parameter can be a value of @ref SPI_NSSP_Mode
|
||||
This mode is activated by the NSSP bit in the SPIx_CR2 register and
|
||||
it takes effect only if the SPI interface is configured as Motorola SPI
|
||||
master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
|
||||
CPOL setting is ignored).. */
|
||||
} SPI_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL SPI State structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
|
||||
HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
|
||||
HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
|
||||
HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
|
||||
HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
|
||||
HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */
|
||||
HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */
|
||||
} HAL_SPI_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief SPI handle Structure definition
|
||||
*/
|
||||
typedef struct __SPI_HandleTypeDef
|
||||
{
|
||||
SPI_TypeDef *Instance; /*!< SPI registers base address */
|
||||
|
||||
SPI_InitTypeDef Init; /*!< SPI communication parameters */
|
||||
|
||||
uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
|
||||
|
||||
uint16_t TxXferSize; /*!< SPI Tx Transfer size */
|
||||
|
||||
__IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
|
||||
|
||||
uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
|
||||
|
||||
uint16_t RxXferSize; /*!< SPI Rx Transfer size */
|
||||
|
||||
__IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
|
||||
|
||||
uint32_t CRCSize; /*!< SPI CRC size used for the transfer */
|
||||
|
||||
void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */
|
||||
|
||||
void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
|
||||
__IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< SPI Error code */
|
||||
|
||||
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
|
||||
void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */
|
||||
void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */
|
||||
void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */
|
||||
void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */
|
||||
void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */
|
||||
void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */
|
||||
void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */
|
||||
void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */
|
||||
void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */
|
||||
|
||||
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
||||
} SPI_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
|
||||
/**
|
||||
* @brief HAL SPI Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, /*!< SPI Tx Completed callback ID */
|
||||
HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, /*!< SPI Rx Completed callback ID */
|
||||
HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< SPI TxRx Completed callback ID */
|
||||
HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< SPI Tx Half Completed callback ID */
|
||||
HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< SPI Rx Half Completed callback ID */
|
||||
HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< SPI TxRx Half Completed callback ID */
|
||||
HAL_SPI_ERROR_CB_ID = 0x06U, /*!< SPI Error callback ID */
|
||||
HAL_SPI_ABORT_CB_ID = 0x07U, /*!< SPI Abort callback ID */
|
||||
HAL_SPI_MSPINIT_CB_ID = 0x08U, /*!< SPI Msp Init callback ID */
|
||||
HAL_SPI_MSPDEINIT_CB_ID = 0x09U /*!< SPI Msp DeInit callback ID */
|
||||
|
||||
} HAL_SPI_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL SPI Callback pointer definition
|
||||
*/
|
||||
typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */
|
||||
|
||||
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup SPI_Exported_Constants SPI Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Error_Code SPI Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */
|
||||
#define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */
|
||||
#define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */
|
||||
#define HAL_SPI_ERROR_FRE (0x00000008U) /*!< FRE error */
|
||||
#define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
|
||||
#define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */
|
||||
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
|
||||
#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Mode SPI Mode
|
||||
* @{
|
||||
*/
|
||||
#define SPI_MODE_SLAVE (0x00000000U)
|
||||
#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Direction SPI Direction Mode
|
||||
* @{
|
||||
*/
|
||||
#define SPI_DIRECTION_2LINES (0x00000000U)
|
||||
#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
|
||||
#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Data_Size SPI Data Size
|
||||
* @{
|
||||
*/
|
||||
#define SPI_DATASIZE_4BIT (0x00000300U)
|
||||
#define SPI_DATASIZE_5BIT (0x00000400U)
|
||||
#define SPI_DATASIZE_6BIT (0x00000500U)
|
||||
#define SPI_DATASIZE_7BIT (0x00000600U)
|
||||
#define SPI_DATASIZE_8BIT (0x00000700U)
|
||||
#define SPI_DATASIZE_9BIT (0x00000800U)
|
||||
#define SPI_DATASIZE_10BIT (0x00000900U)
|
||||
#define SPI_DATASIZE_11BIT (0x00000A00U)
|
||||
#define SPI_DATASIZE_12BIT (0x00000B00U)
|
||||
#define SPI_DATASIZE_13BIT (0x00000C00U)
|
||||
#define SPI_DATASIZE_14BIT (0x00000D00U)
|
||||
#define SPI_DATASIZE_15BIT (0x00000E00U)
|
||||
#define SPI_DATASIZE_16BIT (0x00000F00U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
|
||||
* @{
|
||||
*/
|
||||
#define SPI_POLARITY_LOW (0x00000000U)
|
||||
#define SPI_POLARITY_HIGH SPI_CR1_CPOL
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Clock_Phase SPI Clock Phase
|
||||
* @{
|
||||
*/
|
||||
#define SPI_PHASE_1EDGE (0x00000000U)
|
||||
#define SPI_PHASE_2EDGE SPI_CR1_CPHA
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Slave_Select_management SPI Slave Select Management
|
||||
* @{
|
||||
*/
|
||||
#define SPI_NSS_SOFT SPI_CR1_SSM
|
||||
#define SPI_NSS_HARD_INPUT (0x00000000U)
|
||||
#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
|
||||
* @{
|
||||
*/
|
||||
#define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP
|
||||
#define SPI_NSS_PULSE_DISABLE (0x00000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define SPI_BAUDRATEPRESCALER_2 (0x00000000U)
|
||||
#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)
|
||||
#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)
|
||||
#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
|
||||
#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)
|
||||
#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
|
||||
#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
|
||||
#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
|
||||
* @{
|
||||
*/
|
||||
#define SPI_FIRSTBIT_MSB (0x00000000U)
|
||||
#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_TI_mode SPI TI Mode
|
||||
* @{
|
||||
*/
|
||||
#define SPI_TIMODE_DISABLE (0x00000000U)
|
||||
#define SPI_TIMODE_ENABLE SPI_CR2_FRF
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
|
||||
* @{
|
||||
*/
|
||||
#define SPI_CRCCALCULATION_DISABLE (0x00000000U)
|
||||
#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_CRC_length SPI CRC Length
|
||||
* @{
|
||||
* This parameter can be one of the following values:
|
||||
* SPI_CRC_LENGTH_DATASIZE: aligned with the data size
|
||||
* SPI_CRC_LENGTH_8BIT : CRC 8bit
|
||||
* SPI_CRC_LENGTH_16BIT : CRC 16bit
|
||||
*/
|
||||
#define SPI_CRC_LENGTH_DATASIZE (0x00000000U)
|
||||
#define SPI_CRC_LENGTH_8BIT (0x00000001U)
|
||||
#define SPI_CRC_LENGTH_16BIT (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold
|
||||
* @{
|
||||
* This parameter can be one of the following values:
|
||||
* SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
|
||||
* RXNE event is generated if the FIFO
|
||||
* level is greater or equal to 1/4(8-bits).
|
||||
* SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
|
||||
* level is greater or equal to 1/2(16 bits). */
|
||||
#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
|
||||
#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
|
||||
#define SPI_RXFIFO_THRESHOLD_HF (0x00000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
|
||||
* @{
|
||||
*/
|
||||
#define SPI_IT_TXE SPI_CR2_TXEIE
|
||||
#define SPI_IT_RXNE SPI_CR2_RXNEIE
|
||||
#define SPI_IT_ERR SPI_CR2_ERRIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Flags_definition SPI Flags Definition
|
||||
* @{
|
||||
*/
|
||||
#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
|
||||
#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
|
||||
#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
|
||||
#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
|
||||
#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
|
||||
#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
|
||||
#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
|
||||
#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
|
||||
#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
|
||||
#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\
|
||||
| SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_FTLVL | SPI_SR_FRLVL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level
|
||||
* @{
|
||||
*/
|
||||
#define SPI_FTLVL_EMPTY (0x00000000U)
|
||||
#define SPI_FTLVL_QUARTER_FULL (0x00000800U)
|
||||
#define SPI_FTLVL_HALF_FULL (0x00001000U)
|
||||
#define SPI_FTLVL_FULL (0x00001800U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
|
||||
* @{
|
||||
*/
|
||||
#define SPI_FRLVL_EMPTY (0x00000000U)
|
||||
#define SPI_FRLVL_QUARTER_FULL (0x00000200U)
|
||||
#define SPI_FRLVL_HALF_FULL (0x00000400U)
|
||||
#define SPI_FRLVL_FULL (0x00000600U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup SPI_Exported_Macros SPI Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset SPI handle state.
|
||||
* @param __HANDLE__ specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
|
||||
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_SPI_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
|
||||
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Enable the specified SPI interrupts.
|
||||
* @param __HANDLE__ specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg SPI_IT_ERR: Error interrupt enable
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable the specified SPI interrupts.
|
||||
* @param __HANDLE__ specifies the SPI handle.
|
||||
* This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg SPI_IT_ERR: Error interrupt enable
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
|
||||
|
||||
/** @brief Check whether the specified SPI interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg SPI_IT_ERR: Error interrupt enable
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified SPI flag is set or not.
|
||||
* @param __HANDLE__ specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_FLAG_RXNE: Receive buffer not empty flag
|
||||
* @arg SPI_FLAG_TXE: Transmit buffer empty flag
|
||||
* @arg SPI_FLAG_CRCERR: CRC error flag
|
||||
* @arg SPI_FLAG_MODF: Mode fault flag
|
||||
* @arg SPI_FLAG_OVR: Overrun flag
|
||||
* @arg SPI_FLAG_BSY: Busy flag
|
||||
* @arg SPI_FLAG_FRE: Frame format error flag
|
||||
* @arg SPI_FLAG_FTLVL: SPI fifo transmission level
|
||||
* @arg SPI_FLAG_FRLVL: SPI fifo reception level
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the SPI CRCERR pending flag.
|
||||
* @param __HANDLE__ specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
|
||||
|
||||
/** @brief Clear the SPI MODF pending flag.
|
||||
* @param __HANDLE__ specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
|
||||
do{ \
|
||||
__IO uint32_t tmpreg_modf = 0x00U; \
|
||||
tmpreg_modf = (__HANDLE__)->Instance->SR; \
|
||||
CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
|
||||
UNUSED(tmpreg_modf); \
|
||||
} while(0U)
|
||||
|
||||
/** @brief Clear the SPI OVR pending flag.
|
||||
* @param __HANDLE__ specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
|
||||
do{ \
|
||||
__IO uint32_t tmpreg_ovr = 0x00U; \
|
||||
tmpreg_ovr = (__HANDLE__)->Instance->DR; \
|
||||
tmpreg_ovr = (__HANDLE__)->Instance->SR; \
|
||||
UNUSED(tmpreg_ovr); \
|
||||
} while(0U)
|
||||
|
||||
/** @brief Clear the SPI FRE pending flag.
|
||||
* @param __HANDLE__ specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
|
||||
do{ \
|
||||
__IO uint32_t tmpreg_fre = 0x00U; \
|
||||
tmpreg_fre = (__HANDLE__)->Instance->SR; \
|
||||
UNUSED(tmpreg_fre); \
|
||||
}while(0U)
|
||||
|
||||
/** @brief Enable the SPI peripheral.
|
||||
* @param __HANDLE__ specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
|
||||
|
||||
/** @brief Disable the SPI peripheral.
|
||||
* @param __HANDLE__ specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup SPI_Private_Macros SPI Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Set the SPI transmit-only mode.
|
||||
* @param __HANDLE__ specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
|
||||
|
||||
/** @brief Set the SPI receive-only mode.
|
||||
* @param __HANDLE__ specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
|
||||
|
||||
/** @brief Reset the CRC calculation of the SPI.
|
||||
* @param __HANDLE__ specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
|
||||
SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
|
||||
|
||||
/** @brief Check whether the specified SPI flag is set or not.
|
||||
* @param __SR__ copy of SPI SR register.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_FLAG_RXNE: Receive buffer not empty flag
|
||||
* @arg SPI_FLAG_TXE: Transmit buffer empty flag
|
||||
* @arg SPI_FLAG_CRCERR: CRC error flag
|
||||
* @arg SPI_FLAG_MODF: Mode fault flag
|
||||
* @arg SPI_FLAG_OVR: Overrun flag
|
||||
* @arg SPI_FLAG_BSY: Busy flag
|
||||
* @arg SPI_FLAG_FRE: Frame format error flag
|
||||
* @arg SPI_FLAG_FTLVL: SPI fifo transmission level
|
||||
* @arg SPI_FLAG_FRLVL: SPI fifo reception level
|
||||
* @retval SET or RESET.
|
||||
*/
|
||||
#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \
|
||||
((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified SPI Interrupt is set or not.
|
||||
* @param __CR2__ copy of SPI CR2 register.
|
||||
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg SPI_IT_ERR: Error interrupt enable
|
||||
* @retval SET or RESET.
|
||||
*/
|
||||
#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \
|
||||
(__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Checks if SPI Mode parameter is in allowed range.
|
||||
* @param __MODE__ specifies the SPI Mode.
|
||||
* This parameter can be a value of @ref SPI_Mode
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \
|
||||
((__MODE__) == SPI_MODE_MASTER))
|
||||
|
||||
/** @brief Checks if SPI Direction Mode parameter is in allowed range.
|
||||
* @param __MODE__ specifies the SPI Direction Mode.
|
||||
* This parameter can be a value of @ref SPI_Direction
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
|
||||
((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \
|
||||
((__MODE__) == SPI_DIRECTION_1LINE))
|
||||
|
||||
/** @brief Checks if SPI Direction Mode parameter is 2 lines.
|
||||
* @param __MODE__ specifies the SPI Direction Mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
|
||||
|
||||
/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines.
|
||||
* @param __MODE__ specifies the SPI Direction Mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
|
||||
((__MODE__) == SPI_DIRECTION_1LINE))
|
||||
|
||||
/** @brief Checks if SPI Data Size parameter is in allowed range.
|
||||
* @param __DATASIZE__ specifies the SPI Data Size.
|
||||
* This parameter can be a value of @ref SPI_Data_Size
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \
|
||||
((__DATASIZE__) == SPI_DATASIZE_15BIT) || \
|
||||
((__DATASIZE__) == SPI_DATASIZE_14BIT) || \
|
||||
((__DATASIZE__) == SPI_DATASIZE_13BIT) || \
|
||||
((__DATASIZE__) == SPI_DATASIZE_12BIT) || \
|
||||
((__DATASIZE__) == SPI_DATASIZE_11BIT) || \
|
||||
((__DATASIZE__) == SPI_DATASIZE_10BIT) || \
|
||||
((__DATASIZE__) == SPI_DATASIZE_9BIT) || \
|
||||
((__DATASIZE__) == SPI_DATASIZE_8BIT) || \
|
||||
((__DATASIZE__) == SPI_DATASIZE_7BIT) || \
|
||||
((__DATASIZE__) == SPI_DATASIZE_6BIT) || \
|
||||
((__DATASIZE__) == SPI_DATASIZE_5BIT) || \
|
||||
((__DATASIZE__) == SPI_DATASIZE_4BIT))
|
||||
|
||||
/** @brief Checks if SPI Serial clock steady state parameter is in allowed range.
|
||||
* @param __CPOL__ specifies the SPI serial clock steady state.
|
||||
* This parameter can be a value of @ref SPI_Clock_Polarity
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
|
||||
((__CPOL__) == SPI_POLARITY_HIGH))
|
||||
|
||||
/** @brief Checks if SPI Clock Phase parameter is in allowed range.
|
||||
* @param __CPHA__ specifies the SPI Clock Phase.
|
||||
* This parameter can be a value of @ref SPI_Clock_Phase
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
|
||||
((__CPHA__) == SPI_PHASE_2EDGE))
|
||||
|
||||
/** @brief Checks if SPI Slave Select parameter is in allowed range.
|
||||
* @param __NSS__ specifies the SPI Slave Select management parameter.
|
||||
* This parameter can be a value of @ref SPI_Slave_Select_management
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \
|
||||
((__NSS__) == SPI_NSS_HARD_INPUT) || \
|
||||
((__NSS__) == SPI_NSS_HARD_OUTPUT))
|
||||
|
||||
/** @brief Checks if SPI NSS Pulse parameter is in allowed range.
|
||||
* @param __NSSP__ specifies the SPI NSS Pulse Mode parameter.
|
||||
* This parameter can be a value of @ref SPI_NSSP_Mode
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \
|
||||
((__NSSP__) == SPI_NSS_PULSE_DISABLE))
|
||||
|
||||
/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range.
|
||||
* @param __PRESCALER__ specifies the SPI Baudrate prescaler.
|
||||
* This parameter can be a value of @ref SPI_BaudRate_Prescaler
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \
|
||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \
|
||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \
|
||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \
|
||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \
|
||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \
|
||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \
|
||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))
|
||||
|
||||
/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range.
|
||||
* @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit).
|
||||
* This parameter can be a value of @ref SPI_MSB_LSB_transmission
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
|
||||
((__BIT__) == SPI_FIRSTBIT_LSB))
|
||||
|
||||
/** @brief Checks if SPI TI mode parameter is in allowed range.
|
||||
* @param __MODE__ specifies the SPI TI mode.
|
||||
* This parameter can be a value of @ref SPI_TI_mode
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \
|
||||
((__MODE__) == SPI_TIMODE_ENABLE))
|
||||
|
||||
/** @brief Checks if SPI CRC calculation enabled state is in allowed range.
|
||||
* @param __CALCULATION__ specifies the SPI CRC calculation enable state.
|
||||
* This parameter can be a value of @ref SPI_CRC_Calculation
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \
|
||||
((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))
|
||||
|
||||
/** @brief Checks if SPI CRC length is in allowed range.
|
||||
* @param __LENGTH__ specifies the SPI CRC length.
|
||||
* This parameter can be a value of @ref SPI_CRC_length
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) || \
|
||||
((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \
|
||||
((__LENGTH__) == SPI_CRC_LENGTH_16BIT))
|
||||
|
||||
/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
|
||||
* @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation.
|
||||
* This parameter must be a number between Min_Data = 0 and Max_Data = 65535
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \
|
||||
((__POLYNOMIAL__) <= 0xFFFFU) && \
|
||||
(((__POLYNOMIAL__)&0x1U) != 0U))
|
||||
|
||||
/** @brief Checks if DMA handle is valid.
|
||||
* @param __HANDLE__ specifies a DMA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include SPI HAL Extended module */
|
||||
#include "stm32f0xx_hal_spi_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup SPI_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
|
||||
HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
|
||||
HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
|
||||
pSPI_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ***************************************************/
|
||||
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
|
||||
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
|
||||
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
|
||||
/* Transfer Abort functions */
|
||||
HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
|
||||
HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
|
||||
|
||||
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
|
||||
uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F0xx_HAL_SPI_H */
|
||||
|
||||
73
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_spi_ex.h
Normal file
73
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_spi_ex.h
Normal file
@@ -0,0 +1,73 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_spi_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of SPI HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F0xx_HAL_SPI_EX_H
|
||||
#define STM32F0xx_HAL_SPI_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SPIEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup SPIEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
/* IO operation functions *****************************************************/
|
||||
/** @addtogroup SPIEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F0xx_HAL_SPI_EX_H */
|
||||
|
||||
2157
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h
Normal file
2157
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h
Normal file
File diff suppressed because it is too large
Load Diff
267
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h
Normal file
267
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h
Normal file
@@ -0,0 +1,267 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_tim_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of TIM HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F0xx_HAL_TIM_EX_H
|
||||
#define STM32F0xx_HAL_TIM_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief TIM Hall sensor Configuration Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
|
||||
|
||||
uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
|
||||
|
||||
uint32_t IC1Filter; /*!< Specifies the input capture filter.
|
||||
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
|
||||
|
||||
uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
|
||||
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
|
||||
} TIM_HallSensor_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported types -----------------------------------------------------*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_Remap TIM Extended Remapping
|
||||
* @{
|
||||
*/
|
||||
#define TIM_TIM14_GPIO (0x00000000U) /*!< TIM14 TI1 is connected to GPIO */
|
||||
#define TIM_TIM14_RTC (0x00000001U) /*!< TIM14 TI1 is connected to RTC_clock */
|
||||
#define TIM_TIM14_HSE (0x00000002U) /*!< TIM14 TI1 is connected to HSE/32U */
|
||||
#define TIM_TIM14_MCO (0x00000003U) /*!< TIM14 TI1 is connected to MCO */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported constants -------------------------------------------------*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported macro -----------------------------------------------------*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \
|
||||
(((__INSTANCE__) == TIM14) && (((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of private macro ------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
|
||||
* @brief Timer Hall Sensor functions
|
||||
* @{
|
||||
*/
|
||||
/* Timer Hall Sensor functions **********************************************/
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig);
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
|
||||
|
||||
void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
|
||||
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
|
||||
* @brief Timer Complementary Output Compare functions
|
||||
* @{
|
||||
*/
|
||||
/* Timer Complementary Output Compare functions *****************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
|
||||
uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
|
||||
* @brief Timer Complementary PWM functions
|
||||
* @{
|
||||
*/
|
||||
/* Timer Complementary PWM functions ****************************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
|
||||
uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
|
||||
* @brief Timer Complementary One Pulse functions
|
||||
* @{
|
||||
*/
|
||||
/* Timer Complementary One Pulse functions **********************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
|
||||
* @brief Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
/* Extended Control functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
|
||||
uint32_t CommutationSource);
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
|
||||
uint32_t CommutationSource);
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
|
||||
uint32_t CommutationSource);
|
||||
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
|
||||
const TIM_MasterConfigTypeDef *sMasterConfig);
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
|
||||
const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
|
||||
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
|
||||
* @brief Extended Callbacks functions
|
||||
* @{
|
||||
*/
|
||||
/* Extended Callback **********************************************************/
|
||||
void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
|
||||
* @brief Extended Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
/* Extended Peripheral State functions ***************************************/
|
||||
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported functions -------------------------------------------------*/
|
||||
|
||||
/* Private functions----------------------------------------------------------*/
|
||||
/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions
|
||||
* @{
|
||||
*/
|
||||
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
|
||||
void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of private functions --------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32F0xx_HAL_TIM_EX_H */
|
||||
832
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tsc.h
Normal file
832
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tsc.h
Normal file
@@ -0,0 +1,832 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_tsc.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of TSC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F0xx_HAL_TSC_H
|
||||
#define STM32F0xx_HAL_TSC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
#if defined(TSC)
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup TSC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup TSC_Exported_Types TSC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief TSC state structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_TSC_STATE_RESET = 0x00UL, /*!< TSC registers have their reset value */
|
||||
HAL_TSC_STATE_READY = 0x01UL, /*!< TSC registers are initialized or acquisition is completed with success */
|
||||
HAL_TSC_STATE_BUSY = 0x02UL, /*!< TSC initialization or acquisition is on-going */
|
||||
HAL_TSC_STATE_ERROR = 0x03UL /*!< Acquisition is completed with max count error */
|
||||
} HAL_TSC_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief TSC group status structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TSC_GROUP_ONGOING = 0x00UL, /*!< Acquisition on group is on-going or not started */
|
||||
TSC_GROUP_COMPLETED = 0x01UL /*!< Acquisition on group is completed with success (no max count error) */
|
||||
} TSC_GroupStatusTypeDef;
|
||||
|
||||
/**
|
||||
* @brief TSC init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t CTPulseHighLength; /*!< Charge-transfer high pulse length
|
||||
This parameter can be a value of @ref TSC_CTPulseHL_Config */
|
||||
uint32_t CTPulseLowLength; /*!< Charge-transfer low pulse length
|
||||
This parameter can be a value of @ref TSC_CTPulseLL_Config */
|
||||
FunctionalState SpreadSpectrum; /*!< Spread spectrum activation
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 127 */
|
||||
uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler
|
||||
This parameter can be a value of @ref TSC_SpreadSpec_Prescaler */
|
||||
uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler
|
||||
This parameter can be a value of @ref TSC_PulseGenerator_Prescaler */
|
||||
uint32_t MaxCountValue; /*!< Max count value
|
||||
This parameter can be a value of @ref TSC_MaxCount_Value */
|
||||
uint32_t IODefaultMode; /*!< IO default mode
|
||||
This parameter can be a value of @ref TSC_IO_Default_Mode */
|
||||
uint32_t SynchroPinPolarity; /*!< Synchro pin polarity
|
||||
This parameter can be a value of @ref TSC_Synchro_Pin_Polarity */
|
||||
uint32_t AcquisitionMode; /*!< Acquisition mode
|
||||
This parameter can be a value of @ref TSC_Acquisition_Mode */
|
||||
FunctionalState MaxCountInterrupt;/*!< Max count interrupt activation
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
uint32_t ChannelIOs; /*!< Channel IOs mask */
|
||||
uint32_t ShieldIOs; /*!< Shield IOs mask */
|
||||
uint32_t SamplingIOs; /*!< Sampling IOs mask */
|
||||
} TSC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief TSC IOs configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ChannelIOs; /*!< Channel IOs mask */
|
||||
uint32_t ShieldIOs; /*!< Shield IOs mask */
|
||||
uint32_t SamplingIOs; /*!< Sampling IOs mask */
|
||||
} TSC_IOConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @brief TSC handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __TSC_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
|
||||
{
|
||||
TSC_TypeDef *Instance; /*!< Register base address */
|
||||
TSC_InitTypeDef Init; /*!< Initialization parameters */
|
||||
__IO HAL_TSC_StateTypeDef State; /*!< Peripheral state */
|
||||
HAL_LockTypeDef Lock; /*!< Lock feature */
|
||||
__IO uint32_t ErrorCode; /*!< TSC Error code */
|
||||
|
||||
#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
|
||||
void (* ConvCpltCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Conversion complete callback */
|
||||
void (* ErrorCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Error callback */
|
||||
|
||||
void (* MspInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp DeInit callback */
|
||||
|
||||
#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
|
||||
} TSC_HandleTypeDef;
|
||||
|
||||
enum
|
||||
{
|
||||
TSC_GROUP1_IDX = 0x00UL,
|
||||
TSC_GROUP2_IDX,
|
||||
TSC_GROUP3_IDX,
|
||||
TSC_GROUP4_IDX,
|
||||
TSC_GROUP5_IDX,
|
||||
TSC_GROUP6_IDX,
|
||||
TSC_GROUP7_IDX,
|
||||
TSC_GROUP8_IDX,
|
||||
TSC_NB_OF_GROUPS
|
||||
};
|
||||
|
||||
#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL TSC Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_TSC_CONV_COMPLETE_CB_ID = 0x00UL, /*!< TSC Conversion completed callback ID */
|
||||
HAL_TSC_ERROR_CB_ID = 0x01UL, /*!< TSC Error callback ID */
|
||||
|
||||
HAL_TSC_MSPINIT_CB_ID = 0x02UL, /*!< TSC Msp Init callback ID */
|
||||
HAL_TSC_MSPDEINIT_CB_ID = 0x03UL /*!< TSC Msp DeInit callback ID */
|
||||
|
||||
} HAL_TSC_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL TSC Callback pointer definition
|
||||
*/
|
||||
typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to an TSC callback function */
|
||||
|
||||
#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup TSC_Exported_Constants TSC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup TSC_Error_Code_definition TSC Error Code definition
|
||||
* @brief TSC Error Code definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_TSC_ERROR_NONE 0x00000000UL /*!< No error */
|
||||
#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_TSC_ERROR_INVALID_CALLBACK 0x00000001UL /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TSC_CTPulseHL_Config CTPulse High Length
|
||||
* @{
|
||||
*/
|
||||
#define TSC_CTPH_1CYCLE 0x00000000UL
|
||||
/*!< Charge transfer pulse high during 1 cycle (PGCLK) */
|
||||
#define TSC_CTPH_2CYCLES TSC_CR_CTPH_0
|
||||
/*!< Charge transfer pulse high during 2 cycles (PGCLK) */
|
||||
#define TSC_CTPH_3CYCLES TSC_CR_CTPH_1
|
||||
/*!< Charge transfer pulse high during 3 cycles (PGCLK) */
|
||||
#define TSC_CTPH_4CYCLES (TSC_CR_CTPH_1 | TSC_CR_CTPH_0)
|
||||
/*!< Charge transfer pulse high during 4 cycles (PGCLK) */
|
||||
#define TSC_CTPH_5CYCLES TSC_CR_CTPH_2
|
||||
/*!< Charge transfer pulse high during 5 cycles (PGCLK) */
|
||||
#define TSC_CTPH_6CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_0)
|
||||
/*!< Charge transfer pulse high during 6 cycles (PGCLK) */
|
||||
#define TSC_CTPH_7CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1)
|
||||
/*!< Charge transfer pulse high during 7 cycles (PGCLK) */
|
||||
#define TSC_CTPH_8CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0)
|
||||
/*!< Charge transfer pulse high during 8 cycles (PGCLK) */
|
||||
#define TSC_CTPH_9CYCLES TSC_CR_CTPH_3
|
||||
/*!< Charge transfer pulse high during 9 cycles (PGCLK) */
|
||||
#define TSC_CTPH_10CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_0)
|
||||
/*!< Charge transfer pulse high during 10 cycles (PGCLK) */
|
||||
#define TSC_CTPH_11CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1)
|
||||
/*!< Charge transfer pulse high during 11 cycles (PGCLK) */
|
||||
#define TSC_CTPH_12CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0)
|
||||
/*!< Charge transfer pulse high during 12 cycles (PGCLK) */
|
||||
#define TSC_CTPH_13CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2)
|
||||
/*!< Charge transfer pulse high during 13 cycles (PGCLK) */
|
||||
#define TSC_CTPH_14CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_0)
|
||||
/*!< Charge transfer pulse high during 14 cycles (PGCLK) */
|
||||
#define TSC_CTPH_15CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1)
|
||||
/*!< Charge transfer pulse high during 15 cycles (PGCLK) */
|
||||
#define TSC_CTPH_16CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0)
|
||||
/*!< Charge transfer pulse high during 16 cycles (PGCLK) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TSC_CTPulseLL_Config CTPulse Low Length
|
||||
* @{
|
||||
*/
|
||||
#define TSC_CTPL_1CYCLE 0x00000000UL
|
||||
/*!< Charge transfer pulse low during 1 cycle (PGCLK) */
|
||||
#define TSC_CTPL_2CYCLES TSC_CR_CTPL_0
|
||||
/*!< Charge transfer pulse low during 2 cycles (PGCLK) */
|
||||
#define TSC_CTPL_3CYCLES TSC_CR_CTPL_1
|
||||
/*!< Charge transfer pulse low during 3 cycles (PGCLK) */
|
||||
#define TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0)
|
||||
/*!< Charge transfer pulse low during 4 cycles (PGCLK) */
|
||||
#define TSC_CTPL_5CYCLES TSC_CR_CTPL_2
|
||||
/*!< Charge transfer pulse low during 5 cycles (PGCLK) */
|
||||
#define TSC_CTPL_6CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_0)
|
||||
/*!< Charge transfer pulse low during 6 cycles (PGCLK) */
|
||||
#define TSC_CTPL_7CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1)
|
||||
/*!< Charge transfer pulse low during 7 cycles (PGCLK) */
|
||||
#define TSC_CTPL_8CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0)
|
||||
/*!< Charge transfer pulse low during 8 cycles (PGCLK) */
|
||||
#define TSC_CTPL_9CYCLES TSC_CR_CTPL_3
|
||||
/*!< Charge transfer pulse low during 9 cycles (PGCLK) */
|
||||
#define TSC_CTPL_10CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_0)
|
||||
/*!< Charge transfer pulse low during 10 cycles (PGCLK) */
|
||||
#define TSC_CTPL_11CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1)
|
||||
/*!< Charge transfer pulse low during 11 cycles (PGCLK) */
|
||||
#define TSC_CTPL_12CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0)
|
||||
/*!< Charge transfer pulse low during 12 cycles (PGCLK) */
|
||||
#define TSC_CTPL_13CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2)
|
||||
/*!< Charge transfer pulse low during 13 cycles (PGCLK) */
|
||||
#define TSC_CTPL_14CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0)
|
||||
/*!< Charge transfer pulse low during 14 cycles (PGCLK) */
|
||||
#define TSC_CTPL_15CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1)
|
||||
/*!< Charge transfer pulse low during 15 cycles (PGCLK) */
|
||||
#define TSC_CTPL_16CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0)
|
||||
/*!< Charge transfer pulse low during 16 cycles (PGCLK) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TSC_SpreadSpec_Prescaler Spread Spectrum Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define TSC_SS_PRESC_DIV1 0x00000000UL /*!< Spread Spectrum Prescaler Div1 */
|
||||
#define TSC_SS_PRESC_DIV2 TSC_CR_SSPSC /*!< Spread Spectrum Prescaler Div2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TSC_PulseGenerator_Prescaler Pulse Generator Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define TSC_PG_PRESC_DIV1 0x00000000UL /*!< Pulse Generator HCLK Div1 */
|
||||
#define TSC_PG_PRESC_DIV2 TSC_CR_PGPSC_0 /*!< Pulse Generator HCLK Div2 */
|
||||
#define TSC_PG_PRESC_DIV4 TSC_CR_PGPSC_1 /*!< Pulse Generator HCLK Div4 */
|
||||
#define TSC_PG_PRESC_DIV8 (TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div8 */
|
||||
#define TSC_PG_PRESC_DIV16 TSC_CR_PGPSC_2 /*!< Pulse Generator HCLK Div16 */
|
||||
#define TSC_PG_PRESC_DIV32 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div32 */
|
||||
#define TSC_PG_PRESC_DIV64 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1) /*!< Pulse Generator HCLK Div64 */
|
||||
#define TSC_PG_PRESC_DIV128 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div128 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TSC_MaxCount_Value Max Count Value
|
||||
* @{
|
||||
*/
|
||||
#define TSC_MCV_255 0x00000000UL /*!< 255 maximum number of charge transfer pulses */
|
||||
#define TSC_MCV_511 TSC_CR_MCV_0 /*!< 511 maximum number of charge transfer pulses */
|
||||
#define TSC_MCV_1023 TSC_CR_MCV_1 /*!< 1023 maximum number of charge transfer pulses */
|
||||
#define TSC_MCV_2047 (TSC_CR_MCV_1 | TSC_CR_MCV_0) /*!< 2047 maximum number of charge transfer pulses */
|
||||
#define TSC_MCV_4095 TSC_CR_MCV_2 /*!< 4095 maximum number of charge transfer pulses */
|
||||
#define TSC_MCV_8191 (TSC_CR_MCV_2 | TSC_CR_MCV_0) /*!< 8191 maximum number of charge transfer pulses */
|
||||
#define TSC_MCV_16383 (TSC_CR_MCV_2 | TSC_CR_MCV_1) /*!< 16383 maximum number of charge transfer pulses */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TSC_IO_Default_Mode IO Default Mode
|
||||
* @{
|
||||
*/
|
||||
#define TSC_IODEF_OUT_PP_LOW 0x00000000UL /*!< I/Os are forced to output push-pull low */
|
||||
#define TSC_IODEF_IN_FLOAT TSC_CR_IODEF /*!< I/Os are in input floating */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TSC_Synchro_Pin_Polarity Synchro Pin Polarity
|
||||
* @{
|
||||
*/
|
||||
#define TSC_SYNC_POLARITY_FALLING 0x00000000UL /*!< Falling edge only */
|
||||
#define TSC_SYNC_POLARITY_RISING TSC_CR_SYNCPOL /*!< Rising edge and high level */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TSC_Acquisition_Mode Acquisition Mode
|
||||
* @{
|
||||
*/
|
||||
#define TSC_ACQ_MODE_NORMAL 0x00000000UL
|
||||
/*!< Normal acquisition mode (acquisition starts as soon as START bit is set) */
|
||||
#define TSC_ACQ_MODE_SYNCHRO TSC_CR_AM
|
||||
/*!< Synchronized acquisition mode (acquisition starts if START bit is set and
|
||||
when the selected signal is detected on the SYNC input pin) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TSC_interrupts_definition Interrupts definition
|
||||
* @{
|
||||
*/
|
||||
#define TSC_IT_EOA TSC_IER_EOAIE /*!< End of acquisition interrupt enable */
|
||||
#define TSC_IT_MCE TSC_IER_MCEIE /*!< Max count error interrupt enable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TSC_flags_definition Flags definition
|
||||
* @{
|
||||
*/
|
||||
#define TSC_FLAG_EOA TSC_ISR_EOAF /*!< End of acquisition flag */
|
||||
#define TSC_FLAG_MCE TSC_ISR_MCEF /*!< Max count error flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TSC_Group_definition Group definition
|
||||
* @{
|
||||
*/
|
||||
#define TSC_GROUP1 (0x1UL << TSC_GROUP1_IDX)
|
||||
#define TSC_GROUP2 (0x1UL << TSC_GROUP2_IDX)
|
||||
#define TSC_GROUP3 (0x1UL << TSC_GROUP3_IDX)
|
||||
#define TSC_GROUP4 (0x1UL << TSC_GROUP4_IDX)
|
||||
#define TSC_GROUP5 (0x1UL << TSC_GROUP5_IDX)
|
||||
#define TSC_GROUP6 (0x1UL << TSC_GROUP6_IDX)
|
||||
#define TSC_GROUP7 (0x1UL << TSC_GROUP7_IDX)
|
||||
#define TSC_GROUP8 (0x1UL << TSC_GROUP8_IDX)
|
||||
|
||||
#define TSC_GROUP1_IO1 TSC_IOCCR_G1_IO1 /*!< TSC Group1 IO1 */
|
||||
#define TSC_GROUP1_IO2 TSC_IOCCR_G1_IO2 /*!< TSC Group1 IO2 */
|
||||
#define TSC_GROUP1_IO3 TSC_IOCCR_G1_IO3 /*!< TSC Group1 IO3 */
|
||||
#define TSC_GROUP1_IO4 TSC_IOCCR_G1_IO4 /*!< TSC Group1 IO4 */
|
||||
|
||||
#define TSC_GROUP2_IO1 TSC_IOCCR_G2_IO1 /*!< TSC Group2 IO1 */
|
||||
#define TSC_GROUP2_IO2 TSC_IOCCR_G2_IO2 /*!< TSC Group2 IO2 */
|
||||
#define TSC_GROUP2_IO3 TSC_IOCCR_G2_IO3 /*!< TSC Group2 IO3 */
|
||||
#define TSC_GROUP2_IO4 TSC_IOCCR_G2_IO4 /*!< TSC Group2 IO4 */
|
||||
|
||||
#define TSC_GROUP3_IO1 TSC_IOCCR_G3_IO1 /*!< TSC Group3 IO1 */
|
||||
#define TSC_GROUP3_IO2 TSC_IOCCR_G3_IO2 /*!< TSC Group3 IO2 */
|
||||
#define TSC_GROUP3_IO3 TSC_IOCCR_G3_IO3 /*!< TSC Group3 IO3 */
|
||||
#define TSC_GROUP3_IO4 TSC_IOCCR_G3_IO4 /*!< TSC Group3 IO4 */
|
||||
|
||||
#define TSC_GROUP4_IO1 TSC_IOCCR_G4_IO1 /*!< TSC Group4 IO1 */
|
||||
#define TSC_GROUP4_IO2 TSC_IOCCR_G4_IO2 /*!< TSC Group4 IO2 */
|
||||
#define TSC_GROUP4_IO3 TSC_IOCCR_G4_IO3 /*!< TSC Group4 IO3 */
|
||||
#define TSC_GROUP4_IO4 TSC_IOCCR_G4_IO4 /*!< TSC Group4 IO4 */
|
||||
|
||||
#define TSC_GROUP5_IO1 TSC_IOCCR_G5_IO1 /*!< TSC Group5 IO1 */
|
||||
#define TSC_GROUP5_IO2 TSC_IOCCR_G5_IO2 /*!< TSC Group5 IO2 */
|
||||
#define TSC_GROUP5_IO3 TSC_IOCCR_G5_IO3 /*!< TSC Group5 IO3 */
|
||||
#define TSC_GROUP5_IO4 TSC_IOCCR_G5_IO4 /*!< TSC Group5 IO4 */
|
||||
|
||||
#define TSC_GROUP6_IO1 TSC_IOCCR_G6_IO1 /*!< TSC Group6 IO1 */
|
||||
#define TSC_GROUP6_IO2 TSC_IOCCR_G6_IO2 /*!< TSC Group6 IO2 */
|
||||
#define TSC_GROUP6_IO3 TSC_IOCCR_G6_IO3 /*!< TSC Group6 IO3 */
|
||||
#define TSC_GROUP6_IO4 TSC_IOCCR_G6_IO4 /*!< TSC Group6 IO4 */
|
||||
|
||||
#define TSC_GROUP7_IO1 TSC_IOCCR_G7_IO1 /*!< TSC Group7 IO1 */
|
||||
#define TSC_GROUP7_IO2 TSC_IOCCR_G7_IO2 /*!< TSC Group7 IO2 */
|
||||
#define TSC_GROUP7_IO3 TSC_IOCCR_G7_IO3 /*!< TSC Group7 IO3 */
|
||||
#define TSC_GROUP7_IO4 TSC_IOCCR_G7_IO4 /*!< TSC Group7 IO4 */
|
||||
|
||||
#define TSC_GROUP8_IO1 TSC_IOCCR_G8_IO1 /*!< TSC Group8 IO1 */
|
||||
#define TSC_GROUP8_IO2 TSC_IOCCR_G8_IO2 /*!< TSC Group8 IO2 */
|
||||
#define TSC_GROUP8_IO3 TSC_IOCCR_G8_IO3 /*!< TSC Group8 IO3 */
|
||||
#define TSC_GROUP8_IO4 TSC_IOCCR_G8_IO4 /*!< TSC Group8 IO4 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup TSC_Exported_Macros TSC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset TSC handle state.
|
||||
* @param __HANDLE__ TSC handle
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_TSC_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET)
|
||||
#endif /* (USE_HAL_TSC_REGISTER_CALLBACKS == 1) */
|
||||
|
||||
/**
|
||||
* @brief Enable the TSC peripheral.
|
||||
* @param __HANDLE__ TSC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE)
|
||||
|
||||
/**
|
||||
* @brief Disable the TSC peripheral.
|
||||
* @param __HANDLE__ TSC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_TSCE))
|
||||
|
||||
/**
|
||||
* @brief Start acquisition.
|
||||
* @param __HANDLE__ TSC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START)
|
||||
|
||||
/**
|
||||
* @brief Stop acquisition.
|
||||
* @param __HANDLE__ TSC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_START))
|
||||
|
||||
/**
|
||||
* @brief Set IO default mode to output push-pull low.
|
||||
* @param __HANDLE__ TSC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_IODEF))
|
||||
|
||||
/**
|
||||
* @brief Set IO default mode to input floating.
|
||||
* @param __HANDLE__ TSC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF)
|
||||
|
||||
/**
|
||||
* @brief Set synchronization polarity to falling edge.
|
||||
* @param __HANDLE__ TSC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_SYNCPOL))
|
||||
|
||||
/**
|
||||
* @brief Set synchronization polarity to rising edge and high level.
|
||||
* @param __HANDLE__ TSC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL)
|
||||
|
||||
/**
|
||||
* @brief Enable TSC interrupt.
|
||||
* @param __HANDLE__ TSC handle
|
||||
* @param __INTERRUPT__ TSC interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable TSC interrupt.
|
||||
* @param __HANDLE__ TSC handle
|
||||
* @param __INTERRUPT__ TSC interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Check whether the specified TSC interrupt source is enabled or not.
|
||||
* @param __HANDLE__ TSC Handle
|
||||
* @param __INTERRUPT__ TSC interrupt
|
||||
* @retval SET or RESET
|
||||
*/
|
||||
#define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET :\
|
||||
RESET)
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified TSC flag is set or not.
|
||||
* @param __HANDLE__ TSC handle
|
||||
* @param __FLAG__ TSC flag
|
||||
* @retval SET or RESET
|
||||
*/
|
||||
#define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR\
|
||||
& (__FLAG__)) == (__FLAG__)) ? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Clear the TSC's pending flag.
|
||||
* @param __HANDLE__ TSC handle
|
||||
* @param __FLAG__ TSC flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Enable schmitt trigger hysteresis on a group of IOs.
|
||||
* @param __HANDLE__ TSC handle
|
||||
* @param __GX_IOY_MASK__ IOs mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__))
|
||||
|
||||
/**
|
||||
* @brief Disable schmitt trigger hysteresis on a group of IOs.
|
||||
* @param __HANDLE__ TSC handle
|
||||
* @param __GX_IOY_MASK__ IOs mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR\
|
||||
&= (~(__GX_IOY_MASK__)))
|
||||
|
||||
/**
|
||||
* @brief Open analog switch on a group of IOs.
|
||||
* @param __HANDLE__ TSC handle
|
||||
* @param __GX_IOY_MASK__ IOs mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR\
|
||||
&= (~(__GX_IOY_MASK__)))
|
||||
|
||||
/**
|
||||
* @brief Close analog switch on a group of IOs.
|
||||
* @param __HANDLE__ TSC handle
|
||||
* @param __GX_IOY_MASK__ IOs mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__))
|
||||
|
||||
/**
|
||||
* @brief Enable a group of IOs in channel mode.
|
||||
* @param __HANDLE__ TSC handle
|
||||
* @param __GX_IOY_MASK__ IOs mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__))
|
||||
|
||||
/**
|
||||
* @brief Disable a group of channel IOs.
|
||||
* @param __HANDLE__ TSC handle
|
||||
* @param __GX_IOY_MASK__ IOs mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR\
|
||||
&= (~(__GX_IOY_MASK__)))
|
||||
|
||||
/**
|
||||
* @brief Enable a group of IOs in sampling mode.
|
||||
* @param __HANDLE__ TSC handle
|
||||
* @param __GX_IOY_MASK__ IOs mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__))
|
||||
|
||||
/**
|
||||
* @brief Disable a group of sampling IOs.
|
||||
* @param __HANDLE__ TSC handle
|
||||
* @param __GX_IOY_MASK__ IOs mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (~(__GX_IOY_MASK__)))
|
||||
|
||||
/**
|
||||
* @brief Enable acquisition groups.
|
||||
* @param __HANDLE__ TSC handle
|
||||
* @param __GX_MASK__ Groups mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__))
|
||||
|
||||
/**
|
||||
* @brief Disable acquisition groups.
|
||||
* @param __HANDLE__ TSC handle
|
||||
* @param __GX_MASK__ Groups mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (~(__GX_MASK__)))
|
||||
|
||||
/** @brief Gets acquisition group status.
|
||||
* @param __HANDLE__ TSC Handle
|
||||
* @param __GX_INDEX__ Group index
|
||||
* @retval SET or RESET
|
||||
*/
|
||||
#define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \
|
||||
((((__HANDLE__)->Instance->IOGCSR & (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) == \
|
||||
(uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup TSC_Private_Macros TSC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_TSC_CTPH(__VALUE__) (((__VALUE__) == TSC_CTPH_1CYCLE) || \
|
||||
((__VALUE__) == TSC_CTPH_2CYCLES) || \
|
||||
((__VALUE__) == TSC_CTPH_3CYCLES) || \
|
||||
((__VALUE__) == TSC_CTPH_4CYCLES) || \
|
||||
((__VALUE__) == TSC_CTPH_5CYCLES) || \
|
||||
((__VALUE__) == TSC_CTPH_6CYCLES) || \
|
||||
((__VALUE__) == TSC_CTPH_7CYCLES) || \
|
||||
((__VALUE__) == TSC_CTPH_8CYCLES) || \
|
||||
((__VALUE__) == TSC_CTPH_9CYCLES) || \
|
||||
((__VALUE__) == TSC_CTPH_10CYCLES) || \
|
||||
((__VALUE__) == TSC_CTPH_11CYCLES) || \
|
||||
((__VALUE__) == TSC_CTPH_12CYCLES) || \
|
||||
((__VALUE__) == TSC_CTPH_13CYCLES) || \
|
||||
((__VALUE__) == TSC_CTPH_14CYCLES) || \
|
||||
((__VALUE__) == TSC_CTPH_15CYCLES) || \
|
||||
((__VALUE__) == TSC_CTPH_16CYCLES))
|
||||
|
||||
#define IS_TSC_CTPL(__VALUE__) (((__VALUE__) == TSC_CTPL_1CYCLE) || \
|
||||
((__VALUE__) == TSC_CTPL_2CYCLES) || \
|
||||
((__VALUE__) == TSC_CTPL_3CYCLES) || \
|
||||
((__VALUE__) == TSC_CTPL_4CYCLES) || \
|
||||
((__VALUE__) == TSC_CTPL_5CYCLES) || \
|
||||
((__VALUE__) == TSC_CTPL_6CYCLES) || \
|
||||
((__VALUE__) == TSC_CTPL_7CYCLES) || \
|
||||
((__VALUE__) == TSC_CTPL_8CYCLES) || \
|
||||
((__VALUE__) == TSC_CTPL_9CYCLES) || \
|
||||
((__VALUE__) == TSC_CTPL_10CYCLES) || \
|
||||
((__VALUE__) == TSC_CTPL_11CYCLES) || \
|
||||
((__VALUE__) == TSC_CTPL_12CYCLES) || \
|
||||
((__VALUE__) == TSC_CTPL_13CYCLES) || \
|
||||
((__VALUE__) == TSC_CTPL_14CYCLES) || \
|
||||
((__VALUE__) == TSC_CTPL_15CYCLES) || \
|
||||
((__VALUE__) == TSC_CTPL_16CYCLES))
|
||||
|
||||
#define IS_TSC_SS(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE)\
|
||||
|| ((FunctionalState)(__VALUE__) == ENABLE))
|
||||
|
||||
#define IS_TSC_SSD(__VALUE__) (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < 128UL)))
|
||||
|
||||
#define IS_TSC_SS_PRESC(__VALUE__) (((__VALUE__) == TSC_SS_PRESC_DIV1) || ((__VALUE__) == TSC_SS_PRESC_DIV2))
|
||||
|
||||
#define IS_TSC_PG_PRESC(__VALUE__) (((__VALUE__) == TSC_PG_PRESC_DIV1) || \
|
||||
((__VALUE__) == TSC_PG_PRESC_DIV2) || \
|
||||
((__VALUE__) == TSC_PG_PRESC_DIV4) || \
|
||||
((__VALUE__) == TSC_PG_PRESC_DIV8) || \
|
||||
((__VALUE__) == TSC_PG_PRESC_DIV16) || \
|
||||
((__VALUE__) == TSC_PG_PRESC_DIV32) || \
|
||||
((__VALUE__) == TSC_PG_PRESC_DIV64) || \
|
||||
((__VALUE__) == TSC_PG_PRESC_DIV128))
|
||||
|
||||
#define IS_TSC_PG_PRESC_VS_CTPL(__PGPSC__, __CTPL__) ((((__PGPSC__) == TSC_PG_PRESC_DIV1) && \
|
||||
((__CTPL__) > TSC_CTPL_2CYCLES)) || \
|
||||
(((__PGPSC__) == TSC_PG_PRESC_DIV2) && \
|
||||
((__CTPL__) > TSC_CTPL_1CYCLE)) || \
|
||||
(((__PGPSC__) > TSC_PG_PRESC_DIV2) && \
|
||||
(((__CTPL__) == TSC_CTPL_1CYCLE) || \
|
||||
((__CTPL__) > TSC_CTPL_1CYCLE))))
|
||||
|
||||
#define IS_TSC_MCV(__VALUE__) (((__VALUE__) == TSC_MCV_255) || \
|
||||
((__VALUE__) == TSC_MCV_511) || \
|
||||
((__VALUE__) == TSC_MCV_1023) || \
|
||||
((__VALUE__) == TSC_MCV_2047) || \
|
||||
((__VALUE__) == TSC_MCV_4095) || \
|
||||
((__VALUE__) == TSC_MCV_8191) || \
|
||||
((__VALUE__) == TSC_MCV_16383))
|
||||
|
||||
#define IS_TSC_IODEF(__VALUE__) (((__VALUE__) == TSC_IODEF_OUT_PP_LOW) || ((__VALUE__) == TSC_IODEF_IN_FLOAT))
|
||||
|
||||
#define IS_TSC_SYNC_POL(__VALUE__) (((__VALUE__) == TSC_SYNC_POLARITY_FALLING)\
|
||||
|| ((__VALUE__) == TSC_SYNC_POLARITY_RISING))
|
||||
|
||||
#define IS_TSC_ACQ_MODE(__VALUE__) (((__VALUE__) == TSC_ACQ_MODE_NORMAL) || ((__VALUE__) == TSC_ACQ_MODE_SYNCHRO))
|
||||
|
||||
#define IS_TSC_MCE_IT(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE)\
|
||||
|| ((FunctionalState)(__VALUE__) == ENABLE))
|
||||
|
||||
#define IS_TSC_GROUP_INDEX(__VALUE__) (((__VALUE__) == 0UL)\
|
||||
|| (((__VALUE__) > 0UL) && ((__VALUE__) < (uint32_t)TSC_NB_OF_GROUPS)))
|
||||
|
||||
#define IS_TSC_GROUP(__VALUE__) (((__VALUE__) == 0UL) ||\
|
||||
(((__VALUE__) & TSC_GROUP1_IO1) == TSC_GROUP1_IO1) ||\
|
||||
(((__VALUE__) & TSC_GROUP1_IO2) == TSC_GROUP1_IO2) ||\
|
||||
(((__VALUE__) & TSC_GROUP1_IO3) == TSC_GROUP1_IO3) ||\
|
||||
(((__VALUE__) & TSC_GROUP1_IO4) == TSC_GROUP1_IO4) ||\
|
||||
(((__VALUE__) & TSC_GROUP2_IO1) == TSC_GROUP2_IO1) ||\
|
||||
(((__VALUE__) & TSC_GROUP2_IO2) == TSC_GROUP2_IO2) ||\
|
||||
(((__VALUE__) & TSC_GROUP2_IO3) == TSC_GROUP2_IO3) ||\
|
||||
(((__VALUE__) & TSC_GROUP2_IO4) == TSC_GROUP2_IO4) ||\
|
||||
(((__VALUE__) & TSC_GROUP3_IO1) == TSC_GROUP3_IO1) ||\
|
||||
(((__VALUE__) & TSC_GROUP3_IO2) == TSC_GROUP3_IO2) ||\
|
||||
(((__VALUE__) & TSC_GROUP3_IO3) == TSC_GROUP3_IO3) ||\
|
||||
(((__VALUE__) & TSC_GROUP3_IO4) == TSC_GROUP3_IO4) ||\
|
||||
(((__VALUE__) & TSC_GROUP4_IO1) == TSC_GROUP4_IO1) ||\
|
||||
(((__VALUE__) & TSC_GROUP4_IO2) == TSC_GROUP4_IO2) ||\
|
||||
(((__VALUE__) & TSC_GROUP4_IO3) == TSC_GROUP4_IO3) ||\
|
||||
(((__VALUE__) & TSC_GROUP4_IO4) == TSC_GROUP4_IO4) ||\
|
||||
(((__VALUE__) & TSC_GROUP5_IO1) == TSC_GROUP5_IO1) ||\
|
||||
(((__VALUE__) & TSC_GROUP5_IO2) == TSC_GROUP5_IO2) ||\
|
||||
(((__VALUE__) & TSC_GROUP5_IO3) == TSC_GROUP5_IO3) ||\
|
||||
(((__VALUE__) & TSC_GROUP5_IO4) == TSC_GROUP5_IO4) ||\
|
||||
(((__VALUE__) & TSC_GROUP6_IO1) == TSC_GROUP6_IO1) ||\
|
||||
(((__VALUE__) & TSC_GROUP6_IO2) == TSC_GROUP6_IO2) ||\
|
||||
(((__VALUE__) & TSC_GROUP6_IO3) == TSC_GROUP6_IO3) ||\
|
||||
(((__VALUE__) & TSC_GROUP6_IO4) == TSC_GROUP6_IO4) ||\
|
||||
(((__VALUE__) & TSC_GROUP7_IO1) == TSC_GROUP7_IO1) ||\
|
||||
(((__VALUE__) & TSC_GROUP7_IO2) == TSC_GROUP7_IO2) ||\
|
||||
(((__VALUE__) & TSC_GROUP7_IO3) == TSC_GROUP7_IO3) ||\
|
||||
(((__VALUE__) & TSC_GROUP7_IO4) == TSC_GROUP7_IO4) ||\
|
||||
(((__VALUE__) & TSC_GROUP8_IO1) == TSC_GROUP8_IO1) ||\
|
||||
(((__VALUE__) & TSC_GROUP8_IO2) == TSC_GROUP8_IO2) ||\
|
||||
(((__VALUE__) & TSC_GROUP8_IO3) == TSC_GROUP8_IO3) ||\
|
||||
(((__VALUE__) & TSC_GROUP8_IO4) == TSC_GROUP8_IO4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup TSC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef *htsc);
|
||||
HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc);
|
||||
void HAL_TSC_MspInit(TSC_HandleTypeDef *htsc);
|
||||
void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID,
|
||||
pTSC_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_TSC_UnRegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TSC_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef *htsc);
|
||||
HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef *htsc);
|
||||
HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef *htsc);
|
||||
HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef *htsc);
|
||||
HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc);
|
||||
TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(const TSC_HandleTypeDef *htsc, uint32_t gx_index);
|
||||
uint32_t HAL_TSC_GroupGetValue(const TSC_HandleTypeDef *htsc, uint32_t gx_index);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TSC_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, const TSC_IOConfigTypeDef *config);
|
||||
HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, FunctionalState choice);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef *htsc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
|
||||
* @{
|
||||
*/
|
||||
/******* TSC IRQHandler and Callbacks used in Interrupt mode */
|
||||
void HAL_TSC_IRQHandler(TSC_HandleTypeDef *htsc);
|
||||
void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef *htsc);
|
||||
void HAL_TSC_ErrorCallback(TSC_HandleTypeDef *htsc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* TSC */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F0xx_HAL_TSC_H */
|
||||
1672
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h
Normal file
1672
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h
Normal file
File diff suppressed because it is too large
Load Diff
593
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h
Normal file
593
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h
Normal file
@@ -0,0 +1,593 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_uart_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of UART HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F0xx_HAL_UART_EX_H
|
||||
#define STM32F0xx_HAL_UART_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup UARTEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup UARTEx_Exported_Types UARTEx Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(USART_CR1_UESM)
|
||||
/**
|
||||
* @brief UART wake up from stop mode parameters
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF).
|
||||
This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
|
||||
If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
|
||||
be filled up. */
|
||||
|
||||
uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long.
|
||||
This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */
|
||||
|
||||
uint8_t Address; /*!< UART/USART node address (7-bit long max). */
|
||||
} UART_WakeUpTypeDef;
|
||||
|
||||
#endif /* USART_CR1_UESM */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UARTEx_Word_Length UARTEx Word Length
|
||||
* @{
|
||||
*/
|
||||
#if defined(USART_CR1_M1)
|
||||
#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */
|
||||
#endif /* USART_CR1_M1 */
|
||||
#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */
|
||||
#if defined (USART_CR1_M0)
|
||||
#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */
|
||||
#else
|
||||
#define UART_WORDLENGTH_9B USART_CR1_M /*!< 9-bit long UART frame */
|
||||
#endif /* USART_CR1_M0 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length
|
||||
* @{
|
||||
*/
|
||||
#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */
|
||||
#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup UARTEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup UARTEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
|
||||
uint32_t DeassertionTime);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup UARTEx_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(USART_CR1_UESM)
|
||||
void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
|
||||
|
||||
#endif /* USART_CR1_UESM */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup UARTEx_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions **********************************************/
|
||||
#if defined(USART_CR1_UESM)
|
||||
HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
|
||||
HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
|
||||
HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
|
||||
|
||||
#endif /* USART_CR1_UESM */
|
||||
HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
|
||||
|
||||
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup UARTEx_Private_Macros UARTEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Report the UART clock source.
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* @param __CLOCKSOURCE__ output variable.
|
||||
* @retval UART clocking source, written in __CLOCKSOURCE__.
|
||||
*/
|
||||
|
||||
#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx)
|
||||
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} while(0)
|
||||
#elif defined (STM32F030x8) || defined (STM32F070x6) || defined (STM32F042x6) || defined (STM32F048xx) \
|
||||
|| defined (STM32F051x8) || defined (STM32F058xx)
|
||||
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0)
|
||||
#elif defined(STM32F070xB)
|
||||
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART4) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0)
|
||||
#elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
|
||||
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART4) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0)
|
||||
#elif defined(STM32F091xC) || defined (STM32F098xx)
|
||||
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART3_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART3CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART4) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART5) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART6) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART7) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART8) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0)
|
||||
#elif defined(STM32F030xC)
|
||||
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART4) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART5) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART6) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
#endif /* defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) */
|
||||
|
||||
/** @brief Report the UART mask to apply to retrieve the received data
|
||||
* according to the word length and to the parity bits activation.
|
||||
* @note If PCE = 1, the parity bit is not included in the data extracted
|
||||
* by the reception API().
|
||||
* This masking operation is not carried out in the case of
|
||||
* DMA transfers.
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
|
||||
*/
|
||||
#if defined (USART_CR1_M1)
|
||||
#define UART_MASK_COMPUTATION(__HANDLE__) \
|
||||
do { \
|
||||
if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x01FFU ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FFU ; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FFU ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007FU ; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007FU ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x003FU ; \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x0000U; \
|
||||
} \
|
||||
} while(0U)
|
||||
|
||||
#else
|
||||
#define UART_MASK_COMPUTATION(__HANDLE__) \
|
||||
do { \
|
||||
if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x01FFU ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FFU ; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FFU ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007FU ; \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x0000U; \
|
||||
} \
|
||||
} while(0U)
|
||||
|
||||
#endif /* USART_CR1_M1 */
|
||||
|
||||
/**
|
||||
* @brief Ensure that UART frame length is valid.
|
||||
* @param __LENGTH__ UART frame length.
|
||||
* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
|
||||
*/
|
||||
#if defined (USART_CR1_M1)
|
||||
#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
|
||||
((__LENGTH__) == UART_WORDLENGTH_8B) || \
|
||||
((__LENGTH__) == UART_WORDLENGTH_9B))
|
||||
#else
|
||||
#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_8B) || \
|
||||
((__LENGTH__) == UART_WORDLENGTH_9B))
|
||||
#endif /* USART_CR1_M1 */
|
||||
|
||||
/**
|
||||
* @brief Ensure that UART wake-up address length is valid.
|
||||
* @param __ADDRESS__ UART wake-up address length.
|
||||
* @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
|
||||
*/
|
||||
#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
|
||||
((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F0xx_HAL_UART_EX_H */
|
||||
|
||||
793
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_usart.h
Normal file
793
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_usart.h
Normal file
@@ -0,0 +1,793 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_usart.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of USART HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F0xx_HAL_USART_H
|
||||
#define STM32F0xx_HAL_USART_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USART
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup USART_Exported_Types USART Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief USART Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
|
||||
The baud rate is computed using the following formula:
|
||||
Baud Rate Register[15:4] = ((2 * fclk_pres) /
|
||||
((huart->Init.BaudRate)))[15:4]
|
||||
Baud Rate Register[3] = 0
|
||||
Baud Rate Register[2:0] = (((2 * fclk_pres) /
|
||||
((huart->Init.BaudRate)))[3:0]) >> 1
|
||||
where fclk_pres is the USART input clock frequency
|
||||
@note Oversampling by 8 is systematically applied to
|
||||
achieve high baud rates. */
|
||||
|
||||
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter can be a value of @ref USARTEx_Word_Length. */
|
||||
|
||||
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
|
||||
This parameter can be a value of @ref USART_Stop_Bits. */
|
||||
|
||||
uint32_t Parity; /*!< Specifies the parity mode.
|
||||
This parameter can be a value of @ref USART_Parity
|
||||
@note When parity is enabled, the computed parity is inserted
|
||||
at the MSB position of the transmitted data (9th bit when
|
||||
the word length is set to 9 data bits; 8th bit when the
|
||||
word length is set to 8 data bits). */
|
||||
|
||||
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
|
||||
This parameter can be a value of @ref USART_Mode. */
|
||||
|
||||
uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
|
||||
This parameter can be a value of @ref USART_Clock_Polarity. */
|
||||
|
||||
uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
|
||||
This parameter can be a value of @ref USART_Clock_Phase. */
|
||||
|
||||
uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
|
||||
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
|
||||
This parameter can be a value of @ref USART_Last_Bit. */
|
||||
|
||||
} USART_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL USART State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_USART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */
|
||||
HAL_USART_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_USART_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
|
||||
HAL_USART_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
|
||||
HAL_USART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
|
||||
HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */
|
||||
HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
|
||||
HAL_USART_STATE_ERROR = 0x04U /*!< Error */
|
||||
} HAL_USART_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief USART clock sources definitions
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
|
||||
USART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
|
||||
USART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
|
||||
USART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
|
||||
USART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */
|
||||
} USART_ClockSourceTypeDef;
|
||||
|
||||
/**
|
||||
* @brief USART handle Structure definition
|
||||
*/
|
||||
typedef struct __USART_HandleTypeDef
|
||||
{
|
||||
USART_TypeDef *Instance; /*!< USART registers base address */
|
||||
|
||||
USART_InitTypeDef Init; /*!< USART communication parameters */
|
||||
|
||||
const uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */
|
||||
|
||||
uint16_t TxXferSize; /*!< USART Tx Transfer size */
|
||||
|
||||
__IO uint16_t TxXferCount; /*!< USART Tx Transfer Counter */
|
||||
|
||||
uint8_t *pRxBuffPtr; /*!< Pointer to USART Rx transfer Buffer */
|
||||
|
||||
uint16_t RxXferSize; /*!< USART Rx Transfer size */
|
||||
|
||||
__IO uint16_t RxXferCount; /*!< USART Rx Transfer Counter */
|
||||
|
||||
uint16_t Mask; /*!< USART Rx RDR register mask */
|
||||
|
||||
void (*RxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Rx IRQ handler */
|
||||
|
||||
void (*TxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Tx IRQ handler */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
|
||||
__IO HAL_USART_StateTypeDef State; /*!< USART communication state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< USART Error code */
|
||||
|
||||
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
|
||||
void (* TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Half Complete Callback */
|
||||
void (* TxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Complete Callback */
|
||||
void (* RxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Half Complete Callback */
|
||||
void (* RxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Complete Callback */
|
||||
void (* TxRxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Rx Complete Callback */
|
||||
void (* ErrorCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Error Callback */
|
||||
void (* AbortCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Abort Complete Callback */
|
||||
|
||||
void (* MspInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp DeInit callback */
|
||||
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
|
||||
|
||||
} USART_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL USART Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_USART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< USART Tx Half Complete Callback ID */
|
||||
HAL_USART_TX_COMPLETE_CB_ID = 0x01U, /*!< USART Tx Complete Callback ID */
|
||||
HAL_USART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< USART Rx Half Complete Callback ID */
|
||||
HAL_USART_RX_COMPLETE_CB_ID = 0x03U, /*!< USART Rx Complete Callback ID */
|
||||
HAL_USART_TX_RX_COMPLETE_CB_ID = 0x04U, /*!< USART Tx Rx Complete Callback ID */
|
||||
HAL_USART_ERROR_CB_ID = 0x05U, /*!< USART Error Callback ID */
|
||||
HAL_USART_ABORT_COMPLETE_CB_ID = 0x06U, /*!< USART Abort Complete Callback ID */
|
||||
|
||||
HAL_USART_MSPINIT_CB_ID = 0x09U, /*!< USART MspInit callback ID */
|
||||
HAL_USART_MSPDEINIT_CB_ID = 0x0AU /*!< USART MspDeInit callback ID */
|
||||
|
||||
} HAL_USART_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL USART Callback pointer definition
|
||||
*/
|
||||
typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< pointer to an USART callback function */
|
||||
|
||||
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup USART_Exported_Constants USART Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Error_Definition USART Error Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_USART_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_USART_ERROR_PE (0x00000001U) /*!< Parity error */
|
||||
#define HAL_USART_ERROR_NE (0x00000002U) /*!< Noise error */
|
||||
#define HAL_USART_ERROR_FE (0x00000004U) /*!< Frame error */
|
||||
#define HAL_USART_ERROR_ORE (0x00000008U) /*!< Overrun error */
|
||||
#define HAL_USART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
|
||||
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_USART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
|
||||
#define HAL_USART_ERROR_RTO (0x00000080U) /*!< Receiver Timeout error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Stop_Bits USART Number of Stop Bits
|
||||
* @{
|
||||
*/
|
||||
#if defined(USART_SMARTCARD_SUPPORT)
|
||||
#define USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< USART frame with 0.5 stop bit */
|
||||
#define USART_STOPBITS_1 0x00000000U /*!< USART frame with 1 stop bit */
|
||||
#define USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< USART frame with 1.5 stop bits */
|
||||
#define USART_STOPBITS_2 USART_CR2_STOP_1 /*!< USART frame with 2 stop bits */
|
||||
#else
|
||||
#define USART_STOPBITS_1 (0x00000000U) /*!< USART frame with 1 stop bit */
|
||||
#define USART_STOPBITS_2 (USART_CR2_STOP_1) /*!< USART frame with 2 stop bits */
|
||||
#endif /* USART_SMARTCARD_SUPPORT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Parity USART Parity
|
||||
* @{
|
||||
*/
|
||||
#define USART_PARITY_NONE 0x00000000U /*!< No parity */
|
||||
#define USART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */
|
||||
#define USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Mode USART Mode
|
||||
* @{
|
||||
*/
|
||||
#define USART_MODE_RX USART_CR1_RE /*!< RX mode */
|
||||
#define USART_MODE_TX USART_CR1_TE /*!< TX mode */
|
||||
#define USART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock USART Clock
|
||||
* @{
|
||||
*/
|
||||
#define USART_CLOCK_DISABLE 0x00000000U /*!< USART clock disable */
|
||||
#define USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< USART clock enable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock_Polarity USART Clock Polarity
|
||||
* @{
|
||||
*/
|
||||
#define USART_POLARITY_LOW 0x00000000U /*!< Driver enable signal is active high */
|
||||
#define USART_POLARITY_HIGH USART_CR2_CPOL /*!< Driver enable signal is active low */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock_Phase USART Clock Phase
|
||||
* @{
|
||||
*/
|
||||
#define USART_PHASE_1EDGE 0x00000000U /*!< USART frame phase on first clock transition */
|
||||
#define USART_PHASE_2EDGE USART_CR2_CPHA /*!< USART frame phase on second clock transition */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Last_Bit USART Last Bit
|
||||
* @{
|
||||
*/
|
||||
#define USART_LASTBIT_DISABLE 0x00000000U /*!< USART frame last data bit clock pulse not output to SCLK pin */
|
||||
#define USART_LASTBIT_ENABLE USART_CR2_LBCL /*!< USART frame last data bit clock pulse output to SCLK pin */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USART_Request_Parameters USART Request Parameters
|
||||
* @{
|
||||
*/
|
||||
#define USART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */
|
||||
#if defined(USART_RQR_TXFRQ)
|
||||
#define USART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */
|
||||
#endif /* USART_RQR_TXFRQ */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Flags USART Flags
|
||||
* Elements values convention: 0xXXXX
|
||||
* - 0xXXXX : Flag mask in the ISR register
|
||||
* @{
|
||||
*/
|
||||
#define USART_FLAG_REACK USART_ISR_REACK /*!< USART receive enable acknowledge flag */
|
||||
#define USART_FLAG_TEACK USART_ISR_TEACK /*!< USART transmit enable acknowledge flag */
|
||||
#define USART_FLAG_BUSY USART_ISR_BUSY /*!< USART busy flag */
|
||||
#define USART_FLAG_TXE USART_ISR_TXE /*!< USART transmit data register empty */
|
||||
#define USART_FLAG_RTOF USART_ISR_RTOF /*!< USART receiver timeout flag */
|
||||
#define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */
|
||||
#define USART_FLAG_RXNE USART_ISR_RXNE /*!< USART read data register not empty */
|
||||
#define USART_FLAG_IDLE USART_ISR_IDLE /*!< USART idle flag */
|
||||
#define USART_FLAG_ORE USART_ISR_ORE /*!< USART overrun error */
|
||||
#define USART_FLAG_NE USART_ISR_NE /*!< USART noise error */
|
||||
#define USART_FLAG_FE USART_ISR_FE /*!< USART frame error */
|
||||
#define USART_FLAG_PE USART_ISR_PE /*!< USART parity error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Interrupt_definition USART Interrupts Definition
|
||||
* Elements values convention: 0000ZZZZ0XXYYYYYb
|
||||
* - YYYYY : Interrupt source position in the XX register (5bits)
|
||||
* - XX : Interrupt source register (2bits)
|
||||
* - 01: CR1 register
|
||||
* - 10: CR2 register
|
||||
* - 11: CR3 register
|
||||
* - ZZZZ : Flag position in the ISR register(4bits)
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_IT_PE 0x0028U /*!< USART parity error interruption */
|
||||
#define USART_IT_TXE 0x0727U /*!< USART transmit data register empty interruption */
|
||||
#define USART_IT_TC 0x0626U /*!< USART transmission complete interruption */
|
||||
#define USART_IT_RXNE 0x0525U /*!< USART read data register not empty interruption */
|
||||
#define USART_IT_IDLE 0x0424U /*!< USART idle interruption */
|
||||
#define USART_IT_ERR 0x0060U /*!< USART error interruption */
|
||||
#define USART_IT_ORE 0x0300U /*!< USART overrun error interruption */
|
||||
#define USART_IT_NE 0x0200U /*!< USART noise error interruption */
|
||||
#define USART_IT_FE 0x0100U /*!< USART frame error interruption */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_IT_CLEAR_Flags USART Interruption Clear Flags
|
||||
* @{
|
||||
*/
|
||||
#define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
|
||||
#define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
|
||||
#define USART_CLEAR_NEF USART_ICR_NCF /*!< Noise Error detected Clear Flag */
|
||||
#define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
|
||||
#define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
|
||||
#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
|
||||
#define USART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
|
||||
#define USART_CLEAR_RTOF USART_ICR_RTOCF /*!< USART receiver timeout clear flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Interruption_Mask USART Interruption Flags Mask
|
||||
* @{
|
||||
*/
|
||||
#define USART_IT_MASK 0x001FU /*!< USART interruptions flags mask */
|
||||
#define USART_CR_MASK 0x00E0U /*!< USART control register mask */
|
||||
#define USART_CR_POS 5U /*!< USART control register position */
|
||||
#define USART_ISR_MASK 0x1F00U /*!< USART ISR register mask */
|
||||
#define USART_ISR_POS 8U /*!< USART ISR register position */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup USART_Exported_Macros USART Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset USART handle state.
|
||||
* @param __HANDLE__ USART handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_USART_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0U)
|
||||
#else
|
||||
#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
|
||||
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Check whether the specified USART flag is set or not.
|
||||
* @param __HANDLE__ specifies the USART Handle
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref USART_FLAG_REACK Receive enable acknowledge flag
|
||||
* @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag
|
||||
* @arg @ref USART_FLAG_BUSY Busy flag
|
||||
* @arg @ref USART_FLAG_CTS CTS Change flag
|
||||
* @arg @ref USART_FLAG_TXE Transmit data register empty flag
|
||||
* @arg @ref USART_FLAG_TC Transmission Complete flag
|
||||
* @arg @ref USART_FLAG_RXNE Receive data register not empty flag
|
||||
* @arg @ref USART_FLAG_RTOF Receiver Timeout flag
|
||||
* @arg @ref USART_FLAG_IDLE Idle Line detection flag
|
||||
* @arg @ref USART_FLAG_ORE OverRun Error flag
|
||||
* @arg @ref USART_FLAG_NE Noise Error flag
|
||||
* @arg @ref USART_FLAG_FE Framing Error flag
|
||||
* @arg @ref USART_FLAG_PE Parity Error flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the specified USART pending flag.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref USART_CLEAR_PEF Parity Error Clear Flag
|
||||
* @arg @ref USART_CLEAR_FEF Framing Error Clear Flag
|
||||
* @arg @ref USART_CLEAR_NEF Noise detected Clear Flag
|
||||
* @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag
|
||||
* @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
|
||||
* @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
|
||||
* @arg @ref USART_CLEAR_RTOF Receiver Timeout clear flag
|
||||
* @arg @ref USART_CLEAR_CTSF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
|
||||
|
||||
/** @brief Clear the USART PE pending flag.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)
|
||||
|
||||
/** @brief Clear the USART FE pending flag.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)
|
||||
|
||||
/** @brief Clear the USART NE pending flag.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)
|
||||
|
||||
/** @brief Clear the USART ORE pending flag.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)
|
||||
|
||||
/** @brief Clear the USART IDLE pending flag.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
|
||||
|
||||
|
||||
/** @brief Enable the specified USART interrupt.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* @param __INTERRUPT__ specifies the USART interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
|
||||
* @arg @ref USART_IT_TC Transmission complete interrupt
|
||||
* @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
|
||||
* @arg @ref USART_IT_IDLE Idle line detection interrupt
|
||||
* @arg @ref USART_IT_PE Parity Error interrupt
|
||||
* @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\
|
||||
(((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
|
||||
((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
|
||||
((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
|
||||
((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
|
||||
|
||||
/** @brief Disable the specified USART interrupt.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* @param __INTERRUPT__ specifies the USART interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
|
||||
* @arg @ref USART_IT_TC Transmission complete interrupt
|
||||
* @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
|
||||
* @arg @ref USART_IT_IDLE Idle line detection interrupt
|
||||
* @arg @ref USART_IT_PE Parity Error interrupt
|
||||
* @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\
|
||||
(((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
|
||||
((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
|
||||
((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
|
||||
((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
|
||||
|
||||
/** @brief Check whether the specified USART interrupt has occurred or not.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* @param __INTERRUPT__ specifies the USART interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
|
||||
* @arg @ref USART_IT_TC Transmission complete interrupt
|
||||
* @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
|
||||
* @arg @ref USART_IT_IDLE Idle line detection interrupt
|
||||
* @arg @ref USART_IT_ORE OverRun Error interrupt
|
||||
* @arg @ref USART_IT_NE Noise Error interrupt
|
||||
* @arg @ref USART_IT_FE Framing Error interrupt
|
||||
* @arg @ref USART_IT_PE Parity Error interrupt
|
||||
* @retval The new state of __INTERRUPT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
|
||||
& (0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>>\
|
||||
USART_ISR_POS))) != 0U) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified USART interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* @param __INTERRUPT__ specifies the USART interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
|
||||
* @arg @ref USART_IT_TC Transmission complete interrupt
|
||||
* @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
|
||||
* @arg @ref USART_IT_IDLE Idle line detection interrupt
|
||||
* @arg @ref USART_IT_ORE OverRun Error interrupt
|
||||
* @arg @ref USART_IT_NE Noise Error interrupt
|
||||
* @arg @ref USART_IT_FE Framing Error interrupt
|
||||
* @arg @ref USART_IT_PE Parity Error interrupt
|
||||
* @retval The new state of __INTERRUPT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ?\
|
||||
(__HANDLE__)->Instance->CR1 : \
|
||||
(((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ?\
|
||||
(__HANDLE__)->Instance->CR2 : \
|
||||
(__HANDLE__)->Instance->CR3)) & (0x01U <<\
|
||||
(((uint16_t)(__INTERRUPT__)) &\
|
||||
USART_IT_MASK))) != 0U) ? SET : RESET)
|
||||
|
||||
/** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
|
||||
* to clear the corresponding interrupt.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref USART_CLEAR_PEF Parity Error Clear Flag
|
||||
* @arg @ref USART_CLEAR_FEF Framing Error Clear Flag
|
||||
* @arg @ref USART_CLEAR_NEF Noise detected Clear Flag
|
||||
* @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag
|
||||
* @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
|
||||
* @arg @ref USART_CLEAR_RTOF Receiver timeout clear flag
|
||||
* @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
|
||||
|
||||
/** @brief Set a specific USART request flag.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* @param __REQ__ specifies the request flag to set.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request
|
||||
#if defined(USART_RQR_TXFRQ)
|
||||
* @arg @ref USART_TXDATA_FLUSH_REQUEST Transmit data flush Request
|
||||
#endif
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
|
||||
|
||||
/** @brief Enable the USART one bit sample method.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
|
||||
|
||||
/** @brief Disable the USART one bit sample method.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
|
||||
|
||||
/** @brief Enable USART.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
|
||||
|
||||
/** @brief Disable USART.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @defgroup USART_Private_Macros USART Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
|
||||
* @param __PCLK__ USART clock.
|
||||
* @param __BAUD__ Baud rate set by the user.
|
||||
* @retval Division result
|
||||
*/
|
||||
#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__))
|
||||
|
||||
/** @brief Check USART Baud rate.
|
||||
* @param __BAUDRATE__ Baudrate specified by the user.
|
||||
* The maximum Baud Rate is derived from the maximum clock on F0 (i.e. 48 MHz)
|
||||
* divided by the smallest oversampling used on the USART (i.e. 8)
|
||||
* @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) */
|
||||
#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 6000000U)
|
||||
|
||||
/**
|
||||
* @brief Ensure that USART frame number of stop bits is valid.
|
||||
* @param __STOPBITS__ USART frame number of stop bits.
|
||||
* @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
|
||||
*/
|
||||
#if defined(USART_SMARTCARD_SUPPORT)
|
||||
#define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \
|
||||
((__STOPBITS__) == USART_STOPBITS_1) || \
|
||||
((__STOPBITS__) == USART_STOPBITS_1_5) || \
|
||||
((__STOPBITS__) == USART_STOPBITS_2))
|
||||
#else
|
||||
#define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_1) || \
|
||||
((__STOPBITS__) == USART_STOPBITS_2))
|
||||
#endif /* USART_SMARTCARD_SUPPORT */
|
||||
|
||||
/**
|
||||
* @brief Ensure that USART frame parity is valid.
|
||||
* @param __PARITY__ USART frame parity.
|
||||
* @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
|
||||
*/
|
||||
#define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \
|
||||
((__PARITY__) == USART_PARITY_EVEN) || \
|
||||
((__PARITY__) == USART_PARITY_ODD))
|
||||
|
||||
/**
|
||||
* @brief Ensure that USART communication mode is valid.
|
||||
* @param __MODE__ USART communication mode.
|
||||
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
|
||||
*/
|
||||
#define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
|
||||
|
||||
/**
|
||||
* @brief Ensure that USART clock state is valid.
|
||||
* @param __CLOCK__ USART clock state.
|
||||
* @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)
|
||||
*/
|
||||
#define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \
|
||||
((__CLOCK__) == USART_CLOCK_ENABLE))
|
||||
|
||||
/**
|
||||
* @brief Ensure that USART frame polarity is valid.
|
||||
* @param __CPOL__ USART frame polarity.
|
||||
* @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
|
||||
*/
|
||||
#define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
|
||||
|
||||
/**
|
||||
* @brief Ensure that USART frame phase is valid.
|
||||
* @param __CPHA__ USART frame phase.
|
||||
* @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
|
||||
*/
|
||||
#define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
|
||||
|
||||
/**
|
||||
* @brief Ensure that USART frame last bit clock pulse setting is valid.
|
||||
* @param __LASTBIT__ USART frame last bit clock pulse setting.
|
||||
* @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
|
||||
*/
|
||||
#define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \
|
||||
((__LASTBIT__) == USART_LASTBIT_ENABLE))
|
||||
|
||||
/**
|
||||
* @brief Ensure that USART request parameter is valid.
|
||||
* @param __PARAM__ USART request parameter.
|
||||
* @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
|
||||
*/
|
||||
#if defined(USART_RQR_TXFRQ)
|
||||
#define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
|
||||
((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))
|
||||
#else
|
||||
#define IS_USART_REQUEST_PARAMETER(__PARAM__) ((__PARAM__) == USART_RXDATA_FLUSH_REQUEST)
|
||||
#endif /* USART_RQR_TXFRQ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include USART HAL Extended module */
|
||||
#include "stm32f0xx_hal_usart_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup USART_Exported_Functions USART Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
|
||||
HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
|
||||
void HAL_USART_MspInit(USART_HandleTypeDef *husart);
|
||||
void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID,
|
||||
pUSART_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup USART_Exported_Functions_Group2 IO operation functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
|
||||
uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
|
||||
HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
|
||||
HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
|
||||
/* Transfer Abort functions */
|
||||
HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);
|
||||
HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);
|
||||
|
||||
void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
|
||||
void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
|
||||
void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
|
||||
void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
|
||||
void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
|
||||
void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
|
||||
void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
|
||||
void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup USART_Exported_Functions_Group4 Peripheral State and Error functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart);
|
||||
uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F0xx_HAL_USART_H */
|
||||
|
||||
519
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_usart_ex.h
Normal file
519
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_usart_ex.h
Normal file
@@ -0,0 +1,519 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_usart_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of USART HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F0xx_HAL_USART_EX_H
|
||||
#define STM32F0xx_HAL_USART_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USARTEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USARTEx_Word_Length USARTEx Word Length
|
||||
* @{
|
||||
*/
|
||||
#if defined(USART_CR1_M0)&& defined(USART_CR1_M1)
|
||||
#define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */
|
||||
#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
|
||||
#define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */
|
||||
#elif defined(USART_CR1_M)
|
||||
#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
|
||||
#define USART_WORDLENGTH_9B (USART_CR1_M) /*!< 9-bit long USART frame */
|
||||
#endif /* USART_CR1_M0 && USART_CR1_M */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup USARTEx_Private_Macros USARTEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Report the USART clock source.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* @param __CLOCKSOURCE__ output variable.
|
||||
* @retval the USART clocking source, written in __CLOCKSOURCE__.
|
||||
*/
|
||||
/** @brief Report the UART clock source.
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* @param __CLOCKSOURCE__ output variable.
|
||||
* @retval UART clocking source, written in __CLOCKSOURCE__.
|
||||
*/
|
||||
|
||||
#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx)
|
||||
#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} while(0)
|
||||
#elif defined (STM32F030x8) || defined (STM32F070x6) || defined (STM32F042x6) || defined (STM32F048xx) \
|
||||
|| defined (STM32F051x8) || defined (STM32F058xx)
|
||||
#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0)
|
||||
#elif defined (STM32F070xB)
|
||||
#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART4) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0)
|
||||
#elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
|
||||
#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART4) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0)
|
||||
#elif defined(STM32F091xC) || defined (STM32F098xx)
|
||||
#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART3_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART3CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART4) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART5) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART6) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART7) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART8) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0)
|
||||
#elif defined(STM32F030xC)
|
||||
#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART4) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART5) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART6) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0)
|
||||
#endif /* defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) */
|
||||
/** @brief Compute the USART mask to apply to retrieve the received data
|
||||
* according to the word length and to the parity bits activation.
|
||||
* @note If PCE = 1, the parity bit is not included in the data extracted
|
||||
* by the reception API().
|
||||
* This masking operation is not carried out in the case of
|
||||
* DMA transfers.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.
|
||||
*/
|
||||
#if defined(USART_CR1_M0)&& defined(USART_CR1_M1)
|
||||
#define USART_MASK_COMPUTATION(__HANDLE__) \
|
||||
do { \
|
||||
if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x01FFU; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FFU; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FFU; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007FU; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007FU; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x003FU; \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x0000U; \
|
||||
} \
|
||||
} while(0U)
|
||||
#elif defined(USART_CR1_M)
|
||||
#define USART_MASK_COMPUTATION(__HANDLE__) \
|
||||
do { \
|
||||
if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x01FFU; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FFU; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FFU; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007FU; \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x0000U; \
|
||||
} \
|
||||
} while(0U)
|
||||
#endif /* USART_CR1_M0 && USART_CR1_M */
|
||||
|
||||
/**
|
||||
* @brief Ensure that USART frame length is valid.
|
||||
* @param __LENGTH__ USART frame length.
|
||||
* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
|
||||
*/
|
||||
#if defined(USART_CR1_M0)&& defined(USART_CR1_M1)
|
||||
#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \
|
||||
((__LENGTH__) == USART_WORDLENGTH_8B) || \
|
||||
((__LENGTH__) == USART_WORDLENGTH_9B))
|
||||
#elif defined(USART_CR1_M)
|
||||
#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_8B) || \
|
||||
((__LENGTH__) == USART_WORDLENGTH_9B))
|
||||
#endif /* USART_CR1_M0 && USART_CR1_M */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup USARTEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USARTEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup USARTEx_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F0xx_HAL_USART_EX_H */
|
||||
|
||||
299
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_wwdg.h
Normal file
299
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_wwdg.h
Normal file
@@ -0,0 +1,299 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_wwdg.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of WWDG HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F0xx_HAL_WWDG_H
|
||||
#define STM32F0xx_HAL_WWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup WWDG_Exported_Types WWDG Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief WWDG Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG.
|
||||
This parameter can be a value of @ref WWDG_Prescaler */
|
||||
|
||||
uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter.
|
||||
This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */
|
||||
|
||||
uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
|
||||
This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
|
||||
|
||||
uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interrupt is enable or not.
|
||||
This parameter can be a value of @ref WWDG_EWI_Mode */
|
||||
|
||||
} WWDG_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief WWDG handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __WWDG_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
|
||||
{
|
||||
WWDG_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
WWDG_InitTypeDef Init; /*!< WWDG required parameters */
|
||||
|
||||
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
|
||||
void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */
|
||||
|
||||
void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */
|
||||
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
|
||||
} WWDG_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL WWDG common Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_WWDG_EWI_CB_ID = 0x00U, /*!< WWDG EWI callback ID */
|
||||
HAL_WWDG_MSPINIT_CB_ID = 0x01U, /*!< WWDG MspInit callback ID */
|
||||
} HAL_WWDG_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL WWDG Callback pointer definition
|
||||
*/
|
||||
typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer to a WWDG common callback functions */
|
||||
|
||||
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup WWDG_Exported_Constants WWDG Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
|
||||
* @{
|
||||
*/
|
||||
#define WWDG_IT_EWI WWDG_CFR_EWI /*!< Early wakeup interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Flag_definition WWDG Flag definition
|
||||
* @brief WWDG Flag definition
|
||||
* @{
|
||||
*/
|
||||
#define WWDG_FLAG_EWIF WWDG_SR_EWIF /*!< Early wakeup interrupt flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Prescaler WWDG Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
|
||||
#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
|
||||
#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
|
||||
#define WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/8 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
|
||||
* @{
|
||||
*/
|
||||
#define WWDG_EWI_DISABLE 0x00000000u /*!< EWI Disable */
|
||||
#define WWDG_EWI_ENABLE WWDG_CFR_EWI /*!< EWI Enable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup WWDG_Private_Macros WWDG Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
|
||||
((__PRESCALER__) == WWDG_PRESCALER_2) || \
|
||||
((__PRESCALER__) == WWDG_PRESCALER_4) || \
|
||||
((__PRESCALER__) == WWDG_PRESCALER_8))
|
||||
|
||||
#define IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
|
||||
|
||||
#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
|
||||
|
||||
#define IS_WWDG_EWI_MODE(__MODE__) (((__MODE__) == WWDG_EWI_ENABLE) || \
|
||||
((__MODE__) == WWDG_EWI_DISABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macros ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup WWDG_Exported_Macros WWDG Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the WWDG peripheral.
|
||||
* @param __HANDLE__ WWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
|
||||
|
||||
/**
|
||||
* @brief Enable the WWDG early wakeup interrupt.
|
||||
* @param __HANDLE__: WWDG handle
|
||||
* @param __INTERRUPT__ specifies the interrupt to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg WWDG_IT_EWI: Early wakeup interrupt
|
||||
* @note Once enabled this interrupt cannot be disabled except by a system reset.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the selected WWDG interrupt has occurred or not.
|
||||
* @param __HANDLE__ WWDG handle
|
||||
* @param __INTERRUPT__ specifies the it to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
|
||||
* @retval The new state of WWDG_FLAG (SET or RESET).
|
||||
*/
|
||||
#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
|
||||
|
||||
/** @brief Clear the WWDG interrupt pending bits.
|
||||
* bits to clear the selected interrupt pending bits.
|
||||
* @param __HANDLE__ WWDG handle
|
||||
* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
|
||||
*/
|
||||
#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified WWDG flag is set or not.
|
||||
* @param __HANDLE__ WWDG handle
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
|
||||
* @retval The new state of WWDG_FLAG (SET or RESET).
|
||||
*/
|
||||
#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clear the WWDG's pending flags.
|
||||
* @param __HANDLE__ WWDG handle
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
|
||||
|
||||
/** @brief Check whether the specified WWDG interrupt source is enabled or not.
|
||||
* @param __HANDLE__ WWDG Handle.
|
||||
* @param __INTERRUPT__ specifies the WWDG interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg WWDG_IT_EWI: Early Wakeup Interrupt
|
||||
* @retval state of __INTERRUPT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup WWDG_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDG_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions **********************************/
|
||||
HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
|
||||
void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
|
||||
pWWDG_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDG_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ******************************************************/
|
||||
HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
|
||||
void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
|
||||
void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F0xx_HAL_WWDG_H */
|
||||
|
||||
3408
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_adc.h
Normal file
3408
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_adc.h
Normal file
File diff suppressed because it is too large
Load Diff
842
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h
Normal file
842
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h
Normal file
@@ -0,0 +1,842 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_ll_bus.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of BUS LL module.
|
||||
|
||||
@verbatim
|
||||
##### RCC Limitations #####
|
||||
==============================================================================
|
||||
[..]
|
||||
A delay between an RCC peripheral clock enable and the effective peripheral
|
||||
enabling should be taken into account in order to manage the peripheral read/write
|
||||
from/to registers.
|
||||
(+) This delay depends on the peripheral mapping.
|
||||
(++) AHB & APB peripherals, 1 dummy read is necessary
|
||||
|
||||
[..]
|
||||
Workarounds:
|
||||
(#) For AHB & APB peripherals, a dummy read to the peripheral register has been
|
||||
inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0xx_LL_BUS_H
|
||||
#define __STM32F0xx_LL_BUS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(RCC)
|
||||
|
||||
/** @defgroup BUS_LL BUS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
|
||||
* @{
|
||||
*/
|
||||
#define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
|
||||
#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
|
||||
#if defined(DMA2)
|
||||
#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
|
||||
#endif /*DMA2*/
|
||||
#define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN
|
||||
#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN
|
||||
#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
|
||||
#define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN
|
||||
#define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN
|
||||
#define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN
|
||||
#if defined(GPIOD)
|
||||
#define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN
|
||||
#endif /*GPIOD*/
|
||||
#if defined(GPIOE)
|
||||
#define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN
|
||||
#endif /*GPIOE*/
|
||||
#define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN
|
||||
#if defined(TSC)
|
||||
#define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN
|
||||
#endif /*TSC*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
|
||||
* @{
|
||||
*/
|
||||
#define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
|
||||
#if defined(TIM2)
|
||||
#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
|
||||
#endif /*TIM2*/
|
||||
#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
|
||||
#if defined(TIM6)
|
||||
#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
|
||||
#endif /*TIM6*/
|
||||
#if defined(TIM7)
|
||||
#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
|
||||
#endif /*TIM7*/
|
||||
#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
|
||||
#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
|
||||
#if defined(SPI2)
|
||||
#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
|
||||
#endif /*SPI2*/
|
||||
#if defined(USART2)
|
||||
#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
|
||||
#endif /* USART2 */
|
||||
#if defined(USART3)
|
||||
#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
|
||||
#endif /* USART3 */
|
||||
#if defined(USART4)
|
||||
#define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN
|
||||
#endif /* USART4 */
|
||||
#if defined(USART5)
|
||||
#define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN
|
||||
#endif /* USART5 */
|
||||
#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
|
||||
#if defined(I2C2)
|
||||
#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
|
||||
#endif /*I2C2*/
|
||||
#if defined(USB)
|
||||
#define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN
|
||||
#endif /* USB */
|
||||
#if defined(CAN)
|
||||
#define LL_APB1_GRP1_PERIPH_CAN RCC_APB1ENR_CANEN
|
||||
#endif /*CAN*/
|
||||
#if defined(CRS)
|
||||
#define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN
|
||||
#endif /*CRS*/
|
||||
#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
|
||||
#if defined(DAC)
|
||||
#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
|
||||
#endif /*DAC*/
|
||||
#if defined(CEC)
|
||||
#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
|
||||
#endif /*CEC*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
|
||||
* @{
|
||||
*/
|
||||
#define LL_APB1_GRP2_PERIPH_ALL (uint32_t)0xFFFFFFFFU
|
||||
#define LL_APB1_GRP2_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
|
||||
#define LL_APB1_GRP2_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
|
||||
#if defined(USART8)
|
||||
#define LL_APB1_GRP2_PERIPH_USART8 RCC_APB2ENR_USART8EN
|
||||
#endif /*USART8*/
|
||||
#if defined(USART7)
|
||||
#define LL_APB1_GRP2_PERIPH_USART7 RCC_APB2ENR_USART7EN
|
||||
#endif /*USART7*/
|
||||
#if defined(USART6)
|
||||
#define LL_APB1_GRP2_PERIPH_USART6 RCC_APB2ENR_USART6EN
|
||||
#endif /*USART6*/
|
||||
#define LL_APB1_GRP2_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
|
||||
#define LL_APB1_GRP2_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
|
||||
#define LL_APB1_GRP2_PERIPH_USART1 RCC_APB2ENR_USART1EN
|
||||
#if defined(TIM15)
|
||||
#define LL_APB1_GRP2_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
|
||||
#endif /*TIM15*/
|
||||
#define LL_APB1_GRP2_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
|
||||
#define LL_APB1_GRP2_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
|
||||
#define LL_APB1_GRP2_PERIPH_DBGMCU RCC_APB2ENR_DBGMCUEN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup BUS_LL_EF_AHB1 AHB1
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable AHB1 peripherals clock.
|
||||
* @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n
|
||||
* AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n
|
||||
* AHBENR SRAMEN LL_AHB1_GRP1_EnableClock\n
|
||||
* AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n
|
||||
* AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n
|
||||
* AHBENR GPIOAEN LL_AHB1_GRP1_EnableClock\n
|
||||
* AHBENR GPIOBEN LL_AHB1_GRP1_EnableClock\n
|
||||
* AHBENR GPIOCEN LL_AHB1_GRP1_EnableClock\n
|
||||
* AHBENR GPIODEN LL_AHB1_GRP1_EnableClock\n
|
||||
* AHBENR GPIOEEN LL_AHB1_GRP1_EnableClock\n
|
||||
* AHBENR GPIOFEN LL_AHB1_GRP1_EnableClock\n
|
||||
* AHBENR TSCEN LL_AHB1_GRP1_EnableClock
|
||||
* @param Periphs This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
|
||||
*
|
||||
* (*) value not defined in all devices.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
|
||||
{
|
||||
__IO uint32_t tmpreg;
|
||||
SET_BIT(RCC->AHBENR, Periphs);
|
||||
/* Delay after an RCC peripheral clock enabling */
|
||||
tmpreg = READ_BIT(RCC->AHBENR, Periphs);
|
||||
(void)tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if AHB1 peripheral clock is enabled or not
|
||||
* @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
|
||||
* AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
|
||||
* AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock\n
|
||||
* AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n
|
||||
* AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
|
||||
* AHBENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n
|
||||
* AHBENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n
|
||||
* AHBENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n
|
||||
* AHBENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n
|
||||
* AHBENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n
|
||||
* AHBENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n
|
||||
* AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock
|
||||
* @param Periphs This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
|
||||
*
|
||||
* (*) value not defined in all devices.
|
||||
* @retval State of Periphs (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
|
||||
{
|
||||
return (READ_BIT(RCC->AHBENR, Periphs) == Periphs);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable AHB1 peripherals clock.
|
||||
* @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n
|
||||
* AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n
|
||||
* AHBENR SRAMEN LL_AHB1_GRP1_DisableClock\n
|
||||
* AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n
|
||||
* AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n
|
||||
* AHBENR GPIOAEN LL_AHB1_GRP1_DisableClock\n
|
||||
* AHBENR GPIOBEN LL_AHB1_GRP1_DisableClock\n
|
||||
* AHBENR GPIOCEN LL_AHB1_GRP1_DisableClock\n
|
||||
* AHBENR GPIODEN LL_AHB1_GRP1_DisableClock\n
|
||||
* AHBENR GPIOEEN LL_AHB1_GRP1_DisableClock\n
|
||||
* AHBENR GPIOFEN LL_AHB1_GRP1_DisableClock\n
|
||||
* AHBENR TSCEN LL_AHB1_GRP1_DisableClock
|
||||
* @param Periphs This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
|
||||
*
|
||||
* (*) value not defined in all devices.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
|
||||
{
|
||||
CLEAR_BIT(RCC->AHBENR, Periphs);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Force AHB1 peripherals reset.
|
||||
* @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ForceReset\n
|
||||
* AHBRSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n
|
||||
* AHBRSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n
|
||||
* AHBRSTR GPIODRST LL_AHB1_GRP1_ForceReset\n
|
||||
* AHBRSTR GPIOERST LL_AHB1_GRP1_ForceReset\n
|
||||
* AHBRSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n
|
||||
* AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset
|
||||
* @param Periphs This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
|
||||
*
|
||||
* (*) value not defined in all devices.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
|
||||
{
|
||||
SET_BIT(RCC->AHBRSTR, Periphs);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Release AHB1 peripherals reset.
|
||||
* @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n
|
||||
* AHBRSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n
|
||||
* AHBRSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n
|
||||
* AHBRSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n
|
||||
* AHBRSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n
|
||||
* AHBRSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n
|
||||
* AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset
|
||||
* @param Periphs This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
|
||||
* @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
|
||||
*
|
||||
* (*) value not defined in all devices.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
|
||||
{
|
||||
CLEAR_BIT(RCC->AHBRSTR, Periphs);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup BUS_LL_EF_APB1_GRP1 APB1 GRP1
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable APB1 peripherals clock (available in register 1).
|
||||
* @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
|
||||
* APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
|
||||
* APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
|
||||
* APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
|
||||
* APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n
|
||||
* APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n
|
||||
* APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
|
||||
* APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
|
||||
* APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
|
||||
* APB1ENR USART4EN LL_APB1_GRP1_EnableClock\n
|
||||
* APB1ENR USART5EN LL_APB1_GRP1_EnableClock\n
|
||||
* APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
|
||||
* APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
|
||||
* APB1ENR USBEN LL_APB1_GRP1_EnableClock\n
|
||||
* APB1ENR CANEN LL_APB1_GRP1_EnableClock\n
|
||||
* APB1ENR CRSEN LL_APB1_GRP1_EnableClock\n
|
||||
* APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
|
||||
* APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
|
||||
* APB1ENR CECEN LL_APB1_GRP1_EnableClock
|
||||
* @param Periphs This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_PWR
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
|
||||
*
|
||||
* (*) value not defined in all devices.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
|
||||
{
|
||||
__IO uint32_t tmpreg;
|
||||
SET_BIT(RCC->APB1ENR, Periphs);
|
||||
/* Delay after an RCC peripheral clock enabling */
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
|
||||
(void)tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if APB1 peripheral clock is enabled or not (available in register 1).
|
||||
* @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
|
||||
* APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
|
||||
* APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
|
||||
* APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
|
||||
* APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
|
||||
* APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n
|
||||
* APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
|
||||
* APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
|
||||
* APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
|
||||
* APB1ENR USART4EN LL_APB1_GRP1_IsEnabledClock\n
|
||||
* APB1ENR USART5EN LL_APB1_GRP1_IsEnabledClock\n
|
||||
* APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
|
||||
* APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
|
||||
* APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n
|
||||
* APB1ENR CANEN LL_APB1_GRP1_IsEnabledClock\n
|
||||
* APB1ENR CRSEN LL_APB1_GRP1_IsEnabledClock\n
|
||||
* APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
|
||||
* APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
|
||||
* APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock
|
||||
* @param Periphs This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_PWR
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
|
||||
*
|
||||
* (*) value not defined in all devices.
|
||||
* @retval State of Periphs (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
|
||||
{
|
||||
return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable APB1 peripherals clock (available in register 1).
|
||||
* @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
|
||||
* APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
|
||||
* APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
|
||||
* APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
|
||||
* APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n
|
||||
* APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n
|
||||
* APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
|
||||
* APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
|
||||
* APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
|
||||
* APB1ENR USART4EN LL_APB1_GRP1_DisableClock\n
|
||||
* APB1ENR USART5EN LL_APB1_GRP1_DisableClock\n
|
||||
* APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
|
||||
* APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
|
||||
* APB1ENR USBEN LL_APB1_GRP1_DisableClock\n
|
||||
* APB1ENR CANEN LL_APB1_GRP1_DisableClock\n
|
||||
* APB1ENR CRSEN LL_APB1_GRP1_DisableClock\n
|
||||
* APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
|
||||
* APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
|
||||
* APB1ENR CECEN LL_APB1_GRP1_DisableClock
|
||||
* @param Periphs This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_PWR
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
|
||||
*
|
||||
* (*) value not defined in all devices.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
|
||||
{
|
||||
CLEAR_BIT(RCC->APB1ENR, Periphs);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Force APB1 peripherals reset (available in register 1).
|
||||
* @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
|
||||
* APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
|
||||
* APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
|
||||
* APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
|
||||
* APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n
|
||||
* APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n
|
||||
* APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
|
||||
* APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
|
||||
* APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
|
||||
* APB1RSTR USART4RST LL_APB1_GRP1_ForceReset\n
|
||||
* APB1RSTR USART5RST LL_APB1_GRP1_ForceReset\n
|
||||
* APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
|
||||
* APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
|
||||
* APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n
|
||||
* APB1RSTR CANRST LL_APB1_GRP1_ForceReset\n
|
||||
* APB1RSTR CRSRST LL_APB1_GRP1_ForceReset\n
|
||||
* APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
|
||||
* APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
|
||||
* APB1RSTR CECRST LL_APB1_GRP1_ForceReset
|
||||
* @param Periphs This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_ALL
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_PWR
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
|
||||
*
|
||||
* (*) value not defined in all devices.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
|
||||
{
|
||||
SET_BIT(RCC->APB1RSTR, Periphs);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Release APB1 peripherals reset (available in register 1).
|
||||
* @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
|
||||
* APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
|
||||
* APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
|
||||
* APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
|
||||
* APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
|
||||
* APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n
|
||||
* APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
|
||||
* APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
|
||||
* APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
|
||||
* APB1RSTR USART4RST LL_APB1_GRP1_ReleaseReset\n
|
||||
* APB1RSTR USART5RST LL_APB1_GRP1_ReleaseReset\n
|
||||
* APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
|
||||
* APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
|
||||
* APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n
|
||||
* APB1RSTR CANRST LL_APB1_GRP1_ReleaseReset\n
|
||||
* APB1RSTR CRSRST LL_APB1_GRP1_ReleaseReset\n
|
||||
* APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
|
||||
* APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
|
||||
* APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset
|
||||
* @param Periphs This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_ALL
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_PWR
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
|
||||
* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
|
||||
*
|
||||
* (*) value not defined in all devices.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
|
||||
{
|
||||
CLEAR_BIT(RCC->APB1RSTR, Periphs);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup BUS_LL_EF_APB1_GRP2 APB1 GRP2
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable APB1 peripherals clock (available in register 2).
|
||||
* @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_EnableClock\n
|
||||
* APB2ENR ADC1EN LL_APB1_GRP2_EnableClock\n
|
||||
* APB2ENR USART8EN LL_APB1_GRP2_EnableClock\n
|
||||
* APB2ENR USART7EN LL_APB1_GRP2_EnableClock\n
|
||||
* APB2ENR USART6EN LL_APB1_GRP2_EnableClock\n
|
||||
* APB2ENR TIM1EN LL_APB1_GRP2_EnableClock\n
|
||||
* APB2ENR SPI1EN LL_APB1_GRP2_EnableClock\n
|
||||
* APB2ENR USART1EN LL_APB1_GRP2_EnableClock\n
|
||||
* APB2ENR TIM15EN LL_APB1_GRP2_EnableClock\n
|
||||
* APB2ENR TIM16EN LL_APB1_GRP2_EnableClock\n
|
||||
* APB2ENR TIM17EN LL_APB1_GRP2_EnableClock\n
|
||||
* APB2ENR DBGMCUEN LL_APB1_GRP2_EnableClock
|
||||
* @param Periphs This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_ADC1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_SPI1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM16
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM17
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
|
||||
*
|
||||
* (*) value not defined in all devices.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
|
||||
{
|
||||
__IO uint32_t tmpreg;
|
||||
SET_BIT(RCC->APB2ENR, Periphs);
|
||||
/* Delay after an RCC peripheral clock enabling */
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
|
||||
(void)tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if APB1 peripheral clock is enabled or not (available in register 2).
|
||||
* @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_IsEnabledClock\n
|
||||
* APB2ENR ADC1EN LL_APB1_GRP2_IsEnabledClock\n
|
||||
* APB2ENR USART8EN LL_APB1_GRP2_IsEnabledClock\n
|
||||
* APB2ENR USART7EN LL_APB1_GRP2_IsEnabledClock\n
|
||||
* APB2ENR USART6EN LL_APB1_GRP2_IsEnabledClock\n
|
||||
* APB2ENR TIM1EN LL_APB1_GRP2_IsEnabledClock\n
|
||||
* APB2ENR SPI1EN LL_APB1_GRP2_IsEnabledClock\n
|
||||
* APB2ENR USART1EN LL_APB1_GRP2_IsEnabledClock\n
|
||||
* APB2ENR TIM15EN LL_APB1_GRP2_IsEnabledClock\n
|
||||
* APB2ENR TIM16EN LL_APB1_GRP2_IsEnabledClock\n
|
||||
* APB2ENR TIM17EN LL_APB1_GRP2_IsEnabledClock\n
|
||||
* APB2ENR DBGMCUEN LL_APB1_GRP2_IsEnabledClock
|
||||
* @param Periphs This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_ADC1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_SPI1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM16
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM17
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
|
||||
*
|
||||
* (*) value not defined in all devices.
|
||||
* @retval State of Periphs (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
|
||||
{
|
||||
return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable APB1 peripherals clock (available in register 2).
|
||||
* @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_DisableClock\n
|
||||
* APB2ENR ADC1EN LL_APB1_GRP2_DisableClock\n
|
||||
* APB2ENR USART8EN LL_APB1_GRP2_DisableClock\n
|
||||
* APB2ENR USART7EN LL_APB1_GRP2_DisableClock\n
|
||||
* APB2ENR USART6EN LL_APB1_GRP2_DisableClock\n
|
||||
* APB2ENR TIM1EN LL_APB1_GRP2_DisableClock\n
|
||||
* APB2ENR SPI1EN LL_APB1_GRP2_DisableClock\n
|
||||
* APB2ENR USART1EN LL_APB1_GRP2_DisableClock\n
|
||||
* APB2ENR TIM15EN LL_APB1_GRP2_DisableClock\n
|
||||
* APB2ENR TIM16EN LL_APB1_GRP2_DisableClock\n
|
||||
* APB2ENR TIM17EN LL_APB1_GRP2_DisableClock\n
|
||||
* APB2ENR DBGMCUEN LL_APB1_GRP2_DisableClock
|
||||
* @param Periphs This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_ADC1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_SPI1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM16
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM17
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
|
||||
*
|
||||
* (*) value not defined in all devices.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
|
||||
{
|
||||
CLEAR_BIT(RCC->APB2ENR, Periphs);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Force APB1 peripherals reset (available in register 2).
|
||||
* @rmtoll APB2RSTR SYSCFGRST LL_APB1_GRP2_ForceReset\n
|
||||
* APB2RSTR ADC1RST LL_APB1_GRP2_ForceReset\n
|
||||
* APB2RSTR USART8RST LL_APB1_GRP2_ForceReset\n
|
||||
* APB2RSTR USART7RST LL_APB1_GRP2_ForceReset\n
|
||||
* APB2RSTR USART6RST LL_APB1_GRP2_ForceReset\n
|
||||
* APB2RSTR TIM1RST LL_APB1_GRP2_ForceReset\n
|
||||
* APB2RSTR SPI1RST LL_APB1_GRP2_ForceReset\n
|
||||
* APB2RSTR USART1RST LL_APB1_GRP2_ForceReset\n
|
||||
* APB2RSTR TIM15RST LL_APB1_GRP2_ForceReset\n
|
||||
* APB2RSTR TIM16RST LL_APB1_GRP2_ForceReset\n
|
||||
* APB2RSTR TIM17RST LL_APB1_GRP2_ForceReset\n
|
||||
* APB2RSTR DBGMCURST LL_APB1_GRP2_ForceReset
|
||||
* @param Periphs This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_ALL
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_ADC1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_SPI1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM16
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM17
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
|
||||
*
|
||||
* (*) value not defined in all devices.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
|
||||
{
|
||||
SET_BIT(RCC->APB2RSTR, Periphs);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Release APB1 peripherals reset (available in register 2).
|
||||
* @rmtoll APB2RSTR SYSCFGRST LL_APB1_GRP2_ReleaseReset\n
|
||||
* APB2RSTR ADC1RST LL_APB1_GRP2_ReleaseReset\n
|
||||
* APB2RSTR USART8RST LL_APB1_GRP2_ReleaseReset\n
|
||||
* APB2RSTR USART7RST LL_APB1_GRP2_ReleaseReset\n
|
||||
* APB2RSTR USART6RST LL_APB1_GRP2_ReleaseReset\n
|
||||
* APB2RSTR TIM1RST LL_APB1_GRP2_ReleaseReset\n
|
||||
* APB2RSTR SPI1RST LL_APB1_GRP2_ReleaseReset\n
|
||||
* APB2RSTR USART1RST LL_APB1_GRP2_ReleaseReset\n
|
||||
* APB2RSTR TIM15RST LL_APB1_GRP2_ReleaseReset\n
|
||||
* APB2RSTR TIM16RST LL_APB1_GRP2_ReleaseReset\n
|
||||
* APB2RSTR TIM17RST LL_APB1_GRP2_ReleaseReset\n
|
||||
* APB2RSTR DBGMCURST LL_APB1_GRP2_ReleaseReset
|
||||
* @param Periphs This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_ALL
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_ADC1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_SPI1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_USART1
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM16
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_TIM17
|
||||
* @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
|
||||
*
|
||||
* (*) value not defined in all devices.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
|
||||
{
|
||||
CLEAR_BIT(RCC->APB2RSTR, Periphs);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined(RCC) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0xx_LL_BUS_H */
|
||||
|
||||
829
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_comp.h
Normal file
829
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_comp.h
Normal file
@@ -0,0 +1,829 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_ll_comp.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of COMP LL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0xx_LL_COMP_H
|
||||
#define __STM32F0xx_LL_COMP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (COMP1) || defined (COMP2)
|
||||
|
||||
/** @defgroup COMP_LL COMP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup COMP_LL_Private_Constants COMP Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Differentiation between COMP instances */
|
||||
/* Note: Value not corresponding to a register offset since both */
|
||||
/* COMP instances are sharing the same register) . */
|
||||
#define COMPX_BASE COMP_BASE
|
||||
#define COMPX (COMP1 - COMP2)
|
||||
|
||||
/* COMP registers bits positions */
|
||||
#define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS ((uint32_t)14U) /* Value equivalent to POSITION_VAL(COMP_CSR_COMP1OUT) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup COMP_LL_Private_Macros COMP Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Driver macro reserved for internal use: if COMP instance selected
|
||||
* is odd (COMP1, COMP3, ...), return value '1', else return '0'.
|
||||
* @param __COMP_INSTANCE__ COMP instance
|
||||
* @retval If COMP instance is odd, value '1'. Else, value '0'.
|
||||
*/
|
||||
#define __COMP_IS_INSTANCE_ODD(__COMP_INSTANCE__) \
|
||||
((~(((uint32_t)(__COMP_INSTANCE__) - COMP_BASE) >> 1U)) & 0x00000001)
|
||||
|
||||
/**
|
||||
* @brief Driver macro reserved for internal use: if COMP instance selected
|
||||
* is even (COMP2, COMP4, ...), return value '1', else return '0'.
|
||||
* @param __COMP_INSTANCE__ COMP instance
|
||||
* @retval If COMP instance is even, value '1'. Else, value '0'.
|
||||
*/
|
||||
#define __COMP_IS_INSTANCE_EVEN(__COMP_INSTANCE__) \
|
||||
(((uint32_t)(__COMP_INSTANCE__) - COMP_BASE) >> 1U)
|
||||
|
||||
/**
|
||||
* @brief Driver macro reserved for internal use: from COMP instance
|
||||
* selected, set offset of bits into COMP register.
|
||||
* @note Since both COMP instances are sharing the same register
|
||||
* with 2 area of bits with an offset of 16 bits, this function
|
||||
* returns value "0" if COMP1 is selected and "16" if COMP2 is
|
||||
* selected.
|
||||
* @param __COMP_INSTANCE__ COMP instance
|
||||
* @retval Bits offset in register 32 bits
|
||||
*/
|
||||
#define __COMP_BITOFFSET_INSTANCE(__COMP_INSTANCE__) \
|
||||
(((uint32_t)(__COMP_INSTANCE__) - COMP_BASE) << 3U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup COMP_LL_ES_INIT COMP Exported Init structure
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Structure definition of some features of COMP instance.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PowerMode; /*!< Set comparator operating mode to adjust power and speed.
|
||||
This parameter can be a value of @ref COMP_LL_EC_POWERMODE
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_COMP_SetPowerMode(). */
|
||||
|
||||
uint32_t InputPlus; /*!< Set comparator input plus (non-inverting input).
|
||||
This parameter can be a value of @ref COMP_LL_EC_INPUT_PLUS
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputPlus(). */
|
||||
|
||||
uint32_t InputMinus; /*!< Set comparator input minus (inverting input).
|
||||
This parameter can be a value of @ref COMP_LL_EC_INPUT_MINUS
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputMinus(). */
|
||||
|
||||
uint32_t InputHysteresis; /*!< Set comparator hysteresis mode of the input minus.
|
||||
This parameter can be a value of @ref COMP_LL_EC_INPUT_HYSTERESIS
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputHysteresis(). */
|
||||
|
||||
uint32_t OutputSelection; /*!< Set comparator output selection.
|
||||
This parameter can be a value of @ref COMP_LL_EC_OUTPUT_SELECTION
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputSelection(). */
|
||||
|
||||
uint32_t OutputPolarity; /*!< Set comparator output polarity.
|
||||
This parameter can be a value of @ref COMP_LL_EC_OUTPUT_POLARITY
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputPolarity(). */
|
||||
|
||||
} LL_COMP_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup COMP_LL_Exported_Constants COMP Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_LL_EC_COMMON_WINDOWMODE Comparator common modes - Window mode
|
||||
* @{
|
||||
*/
|
||||
#define LL_COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000U) /*!< Window mode disable: Comparators 1 and 2 are independent */
|
||||
#define LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WNDWEN) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_LL_EC_POWERMODE Comparator modes - Power mode
|
||||
* @{
|
||||
*/
|
||||
#define LL_COMP_POWERMODE_HIGHSPEED ((uint32_t)0x00000000U) /*!< COMP power mode to high speed */
|
||||
#define LL_COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_COMP1MODE_0) /*!< COMP power mode to medium speed */
|
||||
#define LL_COMP_POWERMODE_LOWPOWER (COMP_CSR_COMP1MODE_1) /*!< COMP power mode to low power */
|
||||
#define LL_COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_COMP1MODE_1 | COMP_CSR_COMP1MODE_0) /*!< COMP power mode to ultra-low power */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_LL_EC_INPUT_PLUS Comparator inputs - Input plus (input non-inverting) selection
|
||||
* @{
|
||||
*/
|
||||
#define LL_COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000U) /*!< Comparator input plus connected to IO1 (pin PA1 for COMP1, pin PA3 for COMP2) */
|
||||
#define LL_COMP_INPUT_PLUS_DAC1_CH1 (COMP_CSR_COMP1SW1) /*!< Comparator input plus connected to DAC1 channel 1 (DAC_OUT1), through dedicated switch (Note: this switch is solely intended to redirect signals onto high impedance input, such as COMP1 input plus (highly resistive switch)) (specific to COMP instance: COMP1) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_LL_EC_INPUT_MINUS Comparator inputs - Input minus (input inverting) selection
|
||||
* @{
|
||||
*/
|
||||
#define LL_COMP_INPUT_MINUS_1_4VREFINT ((uint32_t)0x00000000U) /*!< Comparator input minus connected to 1/4 VrefInt */
|
||||
#define LL_COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_COMP1INSEL_0) /*!< Comparator input minus connected to 1/2 VrefInt */
|
||||
#define LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_COMP1INSEL_1 ) /*!< Comparator input minus connected to 3/4 VrefInt */
|
||||
#define LL_COMP_INPUT_MINUS_VREFINT ( COMP_CSR_COMP1INSEL_1 | COMP_CSR_COMP1INSEL_0) /*!< Comparator input minus connected to VrefInt */
|
||||
#define LL_COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_COMP1INSEL_2 ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */
|
||||
#define LL_COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_COMP1INSEL_2 | COMP_CSR_COMP1INSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */
|
||||
#define LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_COMP1INSEL_2 | COMP_CSR_COMP1INSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PA0 for COMP1, pin PA2 for COMP2) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_LL_EC_INPUT_HYSTERESIS Comparator input - Hysteresis
|
||||
* @{
|
||||
*/
|
||||
#define LL_COMP_HYSTERESIS_NONE ((uint32_t)0x00000000U) /*!< No hysteresis */
|
||||
#define LL_COMP_HYSTERESIS_LOW ( COMP_CSR_COMP1HYST_0) /*!< Hysteresis level low */
|
||||
#define LL_COMP_HYSTERESIS_MEDIUM (COMP_CSR_COMP1HYST_1 ) /*!< Hysteresis level medium */
|
||||
#define LL_COMP_HYSTERESIS_HIGH (COMP_CSR_COMP1HYST_1 | COMP_CSR_COMP1HYST_0) /*!< Hysteresis level high */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_LL_EC_OUTPUT_SELECTION Comparator output - Output selection
|
||||
* @{
|
||||
*/
|
||||
/* Note: Output redirection is common for COMP1 and COMP2 */
|
||||
#define LL_COMP_OUTPUT_NONE ((uint32_t)0x00000000U) /*!< COMP output is not connected to other peripherals (except GPIO and EXTI that are always connected to COMP output) */
|
||||
#define LL_COMP_OUTPUT_TIM1_BKIN (COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM1 break input (BKIN) */
|
||||
#define LL_COMP_OUTPUT_TIM1_IC1 (COMP_CSR_COMP1OUTSEL_1) /*!< COMP output connected to TIM1 input capture 1 */
|
||||
#define LL_COMP_OUTPUT_TIM1_OCCLR (COMP_CSR_COMP1OUTSEL_1 | COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM1 OCREF clear */
|
||||
#define LL_COMP_OUTPUT_TIM2_IC4 (COMP_CSR_COMP1OUTSEL_2) /*!< COMP output connected to TIM2 input capture 4 */
|
||||
#define LL_COMP_OUTPUT_TIM2_OCCLR (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM2 OCREF clear */
|
||||
#define LL_COMP_OUTPUT_TIM3_IC1 (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_1) /*!< COMP output connected to TIM3 input capture 1 */
|
||||
#define LL_COMP_OUTPUT_TIM3_OCCLR (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_1 | COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM3 OCREF clear */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_LL_EC_OUTPUT_POLARITY Comparator output - Output polarity
|
||||
* @{
|
||||
*/
|
||||
#define LL_COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000U) /*!< COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input */
|
||||
#define LL_COMP_OUTPUTPOL_INVERTED (COMP_CSR_COMP1POL) /*!< COMP output polarity is inverted: comparator output is low when the plus (non-inverting) input is at a lower voltage than the minus (inverting) input */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_LL_EC_OUTPUT_LEVEL Comparator output - Output level
|
||||
* @{
|
||||
*/
|
||||
#define LL_COMP_OUTPUT_LEVEL_LOW ((uint32_t)0x00000000U) /*!< Comparator output level low (if the polarity is not inverted, otherwise to be complemented) */
|
||||
#define LL_COMP_OUTPUT_LEVEL_HIGH ((uint32_t)0x00000001U) /*!< Comparator output level high (if the polarity is not inverted, otherwise to be complemented) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_LL_EC_HW_DELAYS Definitions of COMP hardware constraints delays
|
||||
* @note Only COMP IP HW delays are defined in COMP LL driver driver,
|
||||
* not timeout values.
|
||||
* For details on delays values, refer to descriptions in source code
|
||||
* above each literal definition.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Delay for comparator startup time. */
|
||||
/* Note: Delay required to reach propagation delay specification. */
|
||||
/* Literal set to maximum value (refer to device datasheet, */
|
||||
/* parameter "tSTART"). */
|
||||
/* Unit: us */
|
||||
#define LL_COMP_DELAY_STARTUP_US ((uint32_t) 60U) /*!< Delay for COMP startup time */
|
||||
|
||||
/* Delay for comparator voltage scaler stabilization time */
|
||||
/* (voltage from VrefInt, delay based on VrefInt startup time). */
|
||||
/* Literal set to maximum value (refer to device datasheet, */
|
||||
/* parameter "tS_SC"). */
|
||||
/* Unit: us */
|
||||
#define LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ((uint32_t) 200U) /*!< Delay for COMP voltage scaler stabilization time */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup COMP_LL_Exported_Macros COMP Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup COMP_LL_EM_WRITE_READ Common write and read registers macro
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write a value in COMP register
|
||||
* @param __INSTANCE__ comparator instance
|
||||
* @param __REG__ Register to be written
|
||||
* @param __VALUE__ Value to be written in the register
|
||||
* @retval None
|
||||
*/
|
||||
#define LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Read a value in COMP register
|
||||
* @param __INSTANCE__ comparator instance
|
||||
* @param __REG__ Register to be read
|
||||
* @retval Register value
|
||||
*/
|
||||
#define LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_LL_EM_HELPER_MACRO COMP helper macro
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Helper macro to select the COMP common instance
|
||||
* to which is belonging the selected COMP instance.
|
||||
* @note COMP common register instance can be used to
|
||||
* set parameters common to several COMP instances.
|
||||
* Refer to functions having argument "COMPxy_COMMON" as parameter.
|
||||
* @param __COMPx__ COMP instance
|
||||
* @retval COMP common instance or value "0" if there is no COMP common instance.
|
||||
*/
|
||||
#define __LL_COMP_COMMON_INSTANCE(__COMPx__) \
|
||||
(COMP12_COMMON)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup COMP_LL_Exported_Functions COMP Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration of COMP hierarchical scope: common to several COMP instances
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set window mode of a pair of comparators instances
|
||||
* (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
|
||||
* @rmtoll CSR WNDWEN LL_COMP_SetCommonWindowMode
|
||||
* @param COMPxy_COMMON Comparator common instance
|
||||
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
|
||||
* @param WindowMode This parameter can be one of the following values:
|
||||
* @arg @ref LL_COMP_WINDOWMODE_DISABLE
|
||||
* @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode)
|
||||
{
|
||||
MODIFY_REG(COMPxy_COMMON->CSR, COMP_CSR_WNDWEN, WindowMode);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get window mode of a pair of comparators instances
|
||||
* (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
|
||||
* @rmtoll CSR WNDWEN LL_COMP_GetCommonWindowMode
|
||||
* @param COMPxy_COMMON Comparator common instance
|
||||
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_COMP_WINDOWMODE_DISABLE
|
||||
* @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(COMPxy_COMMON->CSR, COMP_CSR_WNDWEN));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_LL_EF_Configuration_comparator_modes Configuration of comparator modes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set comparator instance operating mode to adjust power and speed.
|
||||
* @rmtoll CSR COMP1MODE LL_COMP_SetPowerMode\n
|
||||
* COMP2MODE LL_COMP_SetPowerMode
|
||||
* @param COMPx Comparator instance
|
||||
* @param PowerMode This parameter can be one of the following values:
|
||||
* @arg @ref LL_COMP_POWERMODE_HIGHSPEED
|
||||
* @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED
|
||||
* @arg @ref LL_COMP_POWERMODE_LOWPOWER
|
||||
* @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *COMPx, uint32_t PowerMode)
|
||||
{
|
||||
MODIFY_REG(COMP->CSR,
|
||||
COMP_CSR_COMP1MODE << __COMP_BITOFFSET_INSTANCE(COMPx),
|
||||
PowerMode << __COMP_BITOFFSET_INSTANCE(COMPx) );
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get comparator instance operating mode to adjust power and speed.
|
||||
* @rmtoll CSR COMP1MODE LL_COMP_GetPowerMode\n
|
||||
* COMP2MODE LL_COMP_GetPowerMode
|
||||
* @param COMPx Comparator instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_COMP_POWERMODE_HIGHSPEED
|
||||
* @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED
|
||||
* @arg @ref LL_COMP_POWERMODE_LOWPOWER
|
||||
* @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(COMP->CSR,
|
||||
COMP_CSR_COMP1MODE << __COMP_BITOFFSET_INSTANCE(COMPx))
|
||||
>> __COMP_BITOFFSET_INSTANCE(COMPx)
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_LL_EF_Configuration_comparator_inputs Configuration of comparator inputs
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set comparator inputs minus (inverting) and plus (non-inverting).
|
||||
* @note In case of comparator input selected to be connected to IO:
|
||||
* GPIO pins are specific to each comparator instance.
|
||||
* Refer to description of parameters or to reference manual.
|
||||
* @rmtoll CSR COMP1INSEL LL_COMP_ConfigInputs\n
|
||||
* CSR COMP2INSEL LL_COMP_ConfigInputs\n
|
||||
* CSR COMP1SW1 LL_COMP_ConfigInputs
|
||||
* @param COMPx Comparator instance
|
||||
* @param InputMinus This parameter can be one of the following values:
|
||||
* @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
|
||||
* @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
|
||||
* @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
|
||||
* @arg @ref LL_COMP_INPUT_MINUS_VREFINT
|
||||
* @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
|
||||
* @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2
|
||||
* @arg @ref LL_COMP_INPUT_MINUS_IO1
|
||||
* @param InputPlus This parameter can be one of the following values:
|
||||
* @arg @ref LL_COMP_INPUT_PLUS_IO1
|
||||
* @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1 (1)
|
||||
*
|
||||
* (1) Parameter available only on COMP instance: COMP1.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_COMP_ConfigInputs(COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus)
|
||||
{
|
||||
/* Note: Connection switch is applicable only to COMP instance COMP1, */
|
||||
/* therefore if COMP2 is selected the equivalent bit is */
|
||||
/* kept unmodified. */
|
||||
MODIFY_REG(COMP->CSR,
|
||||
(COMP_CSR_COMP1INSEL | (COMP_CSR_COMP1SW1 * __COMP_IS_INSTANCE_ODD(COMPx))) << __COMP_BITOFFSET_INSTANCE(COMPx),
|
||||
(InputMinus | InputPlus) << __COMP_BITOFFSET_INSTANCE(COMPx) );
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set comparator input plus (non-inverting).
|
||||
* @note In case of comparator input selected to be connected to IO:
|
||||
* GPIO pins are specific to each comparator instance.
|
||||
* Refer to description of parameters or to reference manual.
|
||||
* @rmtoll CSR COMP1INSEL LL_COMP_SetInputPlus\n
|
||||
* CSR COMP2INSEL LL_COMP_SetInputPlus
|
||||
* @param COMPx Comparator instance
|
||||
* @param InputPlus This parameter can be one of the following values:
|
||||
* @arg @ref LL_COMP_INPUT_PLUS_IO1
|
||||
* @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1 (1)
|
||||
*
|
||||
* (1) Parameter available only on COMP instance: COMP1.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlus)
|
||||
{
|
||||
/* Note: Connection switch is applicable only to COMP instance COMP1, */
|
||||
/* therefore if COMP2 is selected the equivalent bit is */
|
||||
/* kept unmodified. */
|
||||
MODIFY_REG(COMP->CSR,
|
||||
(COMP_CSR_COMP1SW1 * __COMP_IS_INSTANCE_ODD(COMPx)) << __COMP_BITOFFSET_INSTANCE(COMPx),
|
||||
InputPlus << __COMP_BITOFFSET_INSTANCE(COMPx) );
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get comparator input plus (non-inverting).
|
||||
* @note In case of comparator input selected to be connected to IO:
|
||||
* GPIO pins are specific to each comparator instance.
|
||||
* Refer to description of parameters or to reference manual.
|
||||
* @rmtoll CSR COMP1INSEL LL_COMP_GetInputPlus\n
|
||||
* CSR COMP2INSEL LL_COMP_GetInputPlus
|
||||
* @param COMPx Comparator instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_COMP_INPUT_PLUS_IO1
|
||||
* @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1 (1)
|
||||
*
|
||||
* (1) Parameter available only on COMP instance: COMP1.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx)
|
||||
{
|
||||
/* Note: Connection switch is applicable only to COMP instance COMP1, */
|
||||
/* therefore is COMP2 is selected the returned value will be null. */
|
||||
return (uint32_t)(READ_BIT(COMP->CSR,
|
||||
COMP_CSR_COMP1SW1 << __COMP_BITOFFSET_INSTANCE(COMPx))
|
||||
>> __COMP_BITOFFSET_INSTANCE(COMPx)
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set comparator input minus (inverting).
|
||||
* @note In case of comparator input selected to be connected to IO:
|
||||
* GPIO pins are specific to each comparator instance.
|
||||
* Refer to description of parameters or to reference manual.
|
||||
* @rmtoll CSR COMP1SW1 LL_COMP_SetInputMinus
|
||||
* @param COMPx Comparator instance
|
||||
* @param InputMinus This parameter can be one of the following values:
|
||||
* @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
|
||||
* @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
|
||||
* @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
|
||||
* @arg @ref LL_COMP_INPUT_MINUS_VREFINT
|
||||
* @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
|
||||
* @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2
|
||||
* @arg @ref LL_COMP_INPUT_MINUS_IO1
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMinus)
|
||||
{
|
||||
MODIFY_REG(COMP->CSR,
|
||||
COMP_CSR_COMP1INSEL << __COMP_BITOFFSET_INSTANCE(COMPx),
|
||||
InputMinus << __COMP_BITOFFSET_INSTANCE(COMPx) );
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get comparator input minus (inverting).
|
||||
* @note In case of comparator input selected to be connected to IO:
|
||||
* GPIO pins are specific to each comparator instance.
|
||||
* Refer to description of parameters or to reference manual.
|
||||
* @rmtoll CSR COMP1SW1 LL_COMP_GetInputMinus
|
||||
* @param COMPx Comparator instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
|
||||
* @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
|
||||
* @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
|
||||
* @arg @ref LL_COMP_INPUT_MINUS_VREFINT
|
||||
* @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
|
||||
* @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2
|
||||
* @arg @ref LL_COMP_INPUT_MINUS_IO1
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(COMP->CSR,
|
||||
COMP_CSR_COMP1INSEL << __COMP_BITOFFSET_INSTANCE(COMPx))
|
||||
>> __COMP_BITOFFSET_INSTANCE(COMPx)
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set comparator instance hysteresis mode of the input minus (inverting input).
|
||||
* @rmtoll CSR COMP1HYST LL_COMP_SetInputHysteresis\n
|
||||
* COMP2HYST LL_COMP_SetInputHysteresis
|
||||
* @param COMPx Comparator instance
|
||||
* @param InputHysteresis This parameter can be one of the following values:
|
||||
* @arg @ref LL_COMP_HYSTERESIS_NONE
|
||||
* @arg @ref LL_COMP_HYSTERESIS_LOW
|
||||
* @arg @ref LL_COMP_HYSTERESIS_MEDIUM
|
||||
* @arg @ref LL_COMP_HYSTERESIS_HIGH
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_COMP_SetInputHysteresis(COMP_TypeDef *COMPx, uint32_t InputHysteresis)
|
||||
{
|
||||
MODIFY_REG(COMP->CSR,
|
||||
COMP_CSR_COMP1HYST << __COMP_BITOFFSET_INSTANCE(COMPx),
|
||||
InputHysteresis << __COMP_BITOFFSET_INSTANCE(COMPx) );
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get comparator instance hysteresis mode of the minus (inverting) input.
|
||||
* @rmtoll CSR COMP1HYST LL_COMP_GetInputHysteresis\n
|
||||
* COMP2HYST LL_COMP_GetInputHysteresis
|
||||
* @param COMPx Comparator instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_COMP_HYSTERESIS_NONE
|
||||
* @arg @ref LL_COMP_HYSTERESIS_LOW
|
||||
* @arg @ref LL_COMP_HYSTERESIS_MEDIUM
|
||||
* @arg @ref LL_COMP_HYSTERESIS_HIGH
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(COMP_TypeDef *COMPx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(COMP->CSR,
|
||||
COMP_CSR_COMP1HYST << __COMP_BITOFFSET_INSTANCE(COMPx))
|
||||
>> __COMP_BITOFFSET_INSTANCE(COMPx)
|
||||
);
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_LL_EF_Configuration_comparator_output Configuration of comparator output
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set comparator output selection.
|
||||
* @note Availability of parameters of output selection to timer
|
||||
* depends on timers availability on the selected device.
|
||||
* @rmtoll CSR COMP1OUTSEL LL_COMP_SetOutputSelection\n
|
||||
* COMP2OUTSEL LL_COMP_SetOutputSelection
|
||||
* @param COMPx Comparator instance
|
||||
* @param OutputSelection This parameter can be one of the following values:
|
||||
* @arg @ref LL_COMP_OUTPUT_NONE
|
||||
* @arg @ref LL_COMP_OUTPUT_TIM1_BKIN (1)
|
||||
* @arg @ref LL_COMP_OUTPUT_TIM1_IC1 (1)
|
||||
* @arg @ref LL_COMP_OUTPUT_TIM1_OCCLR (1)
|
||||
* @arg @ref LL_COMP_OUTPUT_TIM2_IC4 (1)
|
||||
* @arg @ref LL_COMP_OUTPUT_TIM2_OCCLR (1)
|
||||
* @arg @ref LL_COMP_OUTPUT_TIM3_IC1 (1)
|
||||
* @arg @ref LL_COMP_OUTPUT_TIM3_OCCLR (1)
|
||||
*
|
||||
* (1) Parameter availability depending on timer availability
|
||||
* on the selected device.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_COMP_SetOutputSelection(COMP_TypeDef *COMPx, uint32_t OutputSelection)
|
||||
{
|
||||
MODIFY_REG(COMP->CSR,
|
||||
COMP_CSR_COMP1OUTSEL << __COMP_BITOFFSET_INSTANCE(COMPx),
|
||||
OutputSelection << __COMP_BITOFFSET_INSTANCE(COMPx) );
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get comparator output selection.
|
||||
* @note Availability of parameters of output selection to timer
|
||||
* depends on timers availability on the selected device.
|
||||
* @rmtoll CSR COMP1OUTSEL LL_COMP_GetOutputSelection\n
|
||||
* COMP2OUTSEL LL_COMP_GetOutputSelection
|
||||
* @param COMPx Comparator instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_COMP_OUTPUT_NONE
|
||||
* @arg @ref LL_COMP_OUTPUT_TIM1_BKIN (1)
|
||||
* @arg @ref LL_COMP_OUTPUT_TIM1_IC1 (1)
|
||||
* @arg @ref LL_COMP_OUTPUT_TIM1_OCCLR (1)
|
||||
* @arg @ref LL_COMP_OUTPUT_TIM2_IC4 (1)
|
||||
* @arg @ref LL_COMP_OUTPUT_TIM2_OCCLR (1)
|
||||
* @arg @ref LL_COMP_OUTPUT_TIM3_IC1 (1)
|
||||
* @arg @ref LL_COMP_OUTPUT_TIM3_OCCLR (1)
|
||||
*
|
||||
* (1) Parameter availability depending on timer availability
|
||||
* on the selected device.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_COMP_GetOutputSelection(COMP_TypeDef *COMPx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(COMP->CSR,
|
||||
COMP_CSR_COMP1OUTSEL << __COMP_BITOFFSET_INSTANCE(COMPx))
|
||||
>> __COMP_BITOFFSET_INSTANCE(COMPx)
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set comparator instance output polarity.
|
||||
* @rmtoll CSR COMP1POL LL_COMP_SetOutputPolarity\n
|
||||
* COMP2POL LL_COMP_SetOutputPolarity
|
||||
* @param COMPx Comparator instance
|
||||
* @param OutputPolarity This parameter can be one of the following values:
|
||||
* @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
|
||||
* @arg @ref LL_COMP_OUTPUTPOL_INVERTED
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_COMP_SetOutputPolarity(COMP_TypeDef *COMPx, uint32_t OutputPolarity)
|
||||
{
|
||||
MODIFY_REG(COMP->CSR,
|
||||
COMP_CSR_COMP1POL << __COMP_BITOFFSET_INSTANCE(COMPx),
|
||||
OutputPolarity << __COMP_BITOFFSET_INSTANCE(COMPx) );
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get comparator instance output polarity.
|
||||
* @rmtoll CSR COMP1POL LL_COMP_GetOutputPolarity\n
|
||||
* COMP2POL LL_COMP_GetOutputPolarity
|
||||
* @param COMPx Comparator instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
|
||||
* @arg @ref LL_COMP_OUTPUTPOL_INVERTED
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(COMP->CSR,
|
||||
COMP_CSR_COMP1POL << __COMP_BITOFFSET_INSTANCE(COMPx))
|
||||
>> __COMP_BITOFFSET_INSTANCE(COMPx)
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_LL_EF_Operation Operation on comparator instance
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable comparator instance.
|
||||
* @note After enable from off state, comparator requires a delay
|
||||
* to reach reach propagation delay specification.
|
||||
* Refer to device datasheet, parameter "tSTART".
|
||||
* @rmtoll CSR COMP1EN LL_COMP_Enable\n
|
||||
* CSR COMP2EN LL_COMP_Enable
|
||||
* @param COMPx Comparator instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_COMP_Enable(COMP_TypeDef *COMPx)
|
||||
{
|
||||
SET_BIT(COMP->CSR, COMP_CSR_COMP1EN << __COMP_BITOFFSET_INSTANCE(COMPx));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable comparator instance.
|
||||
* @rmtoll CSR COMP1EN LL_COMP_Disable\n
|
||||
* CSR COMP2EN LL_COMP_Disable
|
||||
* @param COMPx Comparator instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx)
|
||||
{
|
||||
CLEAR_BIT(COMP->CSR, COMP_CSR_COMP1EN << __COMP_BITOFFSET_INSTANCE(COMPx));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get comparator enable state
|
||||
* (0: COMP is disabled, 1: COMP is enabled)
|
||||
* @rmtoll CSR COMP1EN LL_COMP_IsEnabled\n
|
||||
* CSR COMP2EN LL_COMP_IsEnabled
|
||||
* @param COMPx Comparator instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_COMP_IsEnabled(COMP_TypeDef *COMPx)
|
||||
{
|
||||
return (READ_BIT(COMP->CSR, COMP_CSR_COMP1EN << __COMP_BITOFFSET_INSTANCE(COMPx)) == COMP_CSR_COMP1EN << __COMP_BITOFFSET_INSTANCE(COMPx));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Lock comparator instance.
|
||||
* @note Once locked, comparator configuration can be accessed in read-only.
|
||||
* @note The only way to unlock the comparator is a device hardware reset.
|
||||
* @rmtoll CSR COMP1LOCK LL_COMP_Lock\n
|
||||
* CSR COMP2LOCK LL_COMP_Lock
|
||||
* @param COMPx Comparator instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx)
|
||||
{
|
||||
SET_BIT(COMP->CSR, COMP_CSR_COMP1LOCK << __COMP_BITOFFSET_INSTANCE(COMPx));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get comparator lock state
|
||||
* (0: COMP is unlocked, 1: COMP is locked).
|
||||
* @note Once locked, comparator configuration can be accessed in read-only.
|
||||
* @note The only way to unlock the comparator is a device hardware reset.
|
||||
* @rmtoll CSR COMP1LOCK LL_COMP_IsLocked\n
|
||||
* CSR COMP2LOCK LL_COMP_IsLocked
|
||||
* @param COMPx Comparator instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx)
|
||||
{
|
||||
return (READ_BIT(COMP->CSR, COMP_CSR_COMP1LOCK << __COMP_BITOFFSET_INSTANCE(COMPx)) == COMP_CSR_COMP1LOCK << __COMP_BITOFFSET_INSTANCE(COMPx));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read comparator instance output level.
|
||||
* @note The comparator output level depends on the selected polarity
|
||||
* (Refer to function @ref LL_COMP_SetOutputPolarity()).
|
||||
* If the comparator polarity is not inverted:
|
||||
* - Comparator output is low when the input plus
|
||||
* is at a lower voltage than the input minus
|
||||
* - Comparator output is high when the input plus
|
||||
* is at a higher voltage than the input minus
|
||||
* If the comparator polarity is inverted:
|
||||
* - Comparator output is high when the input plus
|
||||
* is at a lower voltage than the input minus
|
||||
* - Comparator output is low when the input plus
|
||||
* is at a higher voltage than the input minus
|
||||
* @rmtoll CSR COMP1OUT LL_COMP_ReadOutputLevel\n
|
||||
* CSR COMP2OUT LL_COMP_ReadOutputLevel
|
||||
* @param COMPx Comparator instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_COMP_OUTPUT_LEVEL_LOW
|
||||
* @arg @ref LL_COMP_OUTPUT_LEVEL_HIGH
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(COMP->CSR,
|
||||
COMP_CSR_COMP1OUT << __COMP_BITOFFSET_INSTANCE(COMPx))
|
||||
>> (__COMP_BITOFFSET_INSTANCE(COMPx) + LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS)
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup COMP_LL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx);
|
||||
ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct);
|
||||
void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* COMP1 || COMP2 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0xx_LL_COMP_H */
|
||||
|
||||
318
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_cortex.h
Normal file
318
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_cortex.h
Normal file
@@ -0,0 +1,318 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_ll_cortex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CORTEX LL module.
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The LL CORTEX driver contains a set of generic APIs that can be
|
||||
used by user:
|
||||
(+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick
|
||||
functions
|
||||
(+) Low power mode configuration (SCB register of Cortex-MCU)
|
||||
(+) API to access to MCU info (CPUID register)
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0xx_LL_CORTEX_H
|
||||
#define __STM32F0xx_LL_CORTEX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL CORTEX
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
|
||||
#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function checks if the Systick counter flag is active or not.
|
||||
* @note It can be used in timeout function on application side.
|
||||
* @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
|
||||
{
|
||||
return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the SysTick clock source
|
||||
* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
|
||||
* @param Source This parameter can be one of the following values:
|
||||
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
|
||||
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
|
||||
{
|
||||
if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
|
||||
{
|
||||
SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
|
||||
}
|
||||
else
|
||||
{
|
||||
CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the SysTick clock source
|
||||
* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
|
||||
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
|
||||
{
|
||||
return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable SysTick exception request
|
||||
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
|
||||
{
|
||||
SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable SysTick exception request
|
||||
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
|
||||
{
|
||||
CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks if the SYSTICK interrupt is enabled or disabled.
|
||||
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
|
||||
{
|
||||
return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Processor uses sleep as its low power mode
|
||||
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_LPM_EnableSleep(void)
|
||||
{
|
||||
/* Clear SLEEPDEEP bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Processor uses deep sleep as its low power mode
|
||||
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
|
||||
{
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
|
||||
* @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
|
||||
* empty main application.
|
||||
* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
|
||||
{
|
||||
/* Set SLEEPONEXIT bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Do not sleep when returning to Thread mode.
|
||||
* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
|
||||
{
|
||||
/* Clear SLEEPONEXIT bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
|
||||
* processor.
|
||||
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
|
||||
{
|
||||
/* Set SEVEONPEND bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
|
||||
* excluded
|
||||
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
|
||||
{
|
||||
/* Clear SEVEONPEND bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get Implementer code
|
||||
* @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
|
||||
* @retval Value should be equal to 0x41 for ARM
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Variant number (The r value in the rnpn product revision identifier)
|
||||
* @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
|
||||
* @retval Value between 0 and 255 (0x0: revision 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Architecture number
|
||||
* @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture
|
||||
* @retval Value should be equal to 0xC for Cortex-M0 devices
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Part number
|
||||
* @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
|
||||
* @retval Value should be equal to 0xC20 for Cortex-M0
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
|
||||
* @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
|
||||
* @retval Value between 0 and 255 (0x1: patch 1)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0xx_LL_CORTEX_H */
|
||||
|
||||
471
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_crc.h
Normal file
471
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_crc.h
Normal file
@@ -0,0 +1,471 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_ll_crc.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CRC LL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F0xx_LL_CRC_H
|
||||
#define STM32F0xx_LL_CRC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(CRC)
|
||||
|
||||
/** @defgroup CRC_LL CRC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(CRC_POL_POL)
|
||||
/** @defgroup CRC_LL_EC_POLYLENGTH Polynomial length
|
||||
* @{
|
||||
*/
|
||||
#define LL_CRC_POLYLENGTH_32B 0x00000000U /*!< 32 bits Polynomial size */
|
||||
#define LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< 16 bits Polynomial size */
|
||||
#define LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< 8 bits Polynomial size */
|
||||
#define LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0) /*!< 7 bits Polynomial size */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* CRC_POL_POL */
|
||||
|
||||
/** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse
|
||||
* @{
|
||||
*/
|
||||
#define LL_CRC_INDATA_REVERSE_NONE 0x00000000U /*!< Input Data bit order not affected */
|
||||
#define LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0 /*!< Input Data bit reversal done by byte */
|
||||
#define LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1 /*!< Input Data bit reversal done by half-word */
|
||||
#define LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0) /*!< Input Data bit reversal done by word */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_LL_EC_OUTDATA_REVERSE Output Data Reverse
|
||||
* @{
|
||||
*/
|
||||
#define LL_CRC_OUTDATA_REVERSE_NONE 0x00000000U /*!< Output Data bit order not affected */
|
||||
#define LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT /*!< Output Data bit reversal done by bit */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(CRC_POL_POL)
|
||||
/** @defgroup CRC_LL_EC_Default_Polynomial_Value Default CRC generating polynomial value
|
||||
* @brief Normal representation of this polynomial value is
|
||||
* X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .
|
||||
* @{
|
||||
*/
|
||||
#define LL_CRC_DEFAULT_CRC32_POLY 0x04C11DB7U /*!< Default CRC generating polynomial value */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* CRC_POL_POL */
|
||||
|
||||
/** @defgroup CRC_LL_EC_Default_InitValue Default CRC computation initialization value
|
||||
* @{
|
||||
*/
|
||||
#define LL_CRC_DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Default CRC computation initialization value */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write a value in CRC register
|
||||
* @param __INSTANCE__ CRC Instance
|
||||
* @param __REG__ Register to be written
|
||||
* @param __VALUE__ Value to be written in the register
|
||||
* @retval None
|
||||
*/
|
||||
#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__)
|
||||
|
||||
/**
|
||||
* @brief Read a value in CRC register
|
||||
* @param __INSTANCE__ CRC Instance
|
||||
* @param __REG__ Register to be read
|
||||
* @retval Register value
|
||||
*/
|
||||
#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Reset the CRC calculation unit.
|
||||
* @note If Programmable Initial CRC value feature
|
||||
* is available, also set the Data Register to the value stored in the
|
||||
* CRC_INIT register, otherwise, reset Data Register to its default value.
|
||||
* @rmtoll CR RESET LL_CRC_ResetCRCCalculationUnit
|
||||
* @param CRCx CRC Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
|
||||
{
|
||||
SET_BIT(CRCx->CR, CRC_CR_RESET);
|
||||
}
|
||||
|
||||
#if defined(CRC_POL_POL)
|
||||
/**
|
||||
* @brief Configure size of the polynomial.
|
||||
* @rmtoll CR POLYSIZE LL_CRC_SetPolynomialSize
|
||||
* @param CRCx CRC Instance
|
||||
* @param PolySize This parameter can be one of the following values:
|
||||
* @arg @ref LL_CRC_POLYLENGTH_32B
|
||||
* @arg @ref LL_CRC_POLYLENGTH_16B
|
||||
* @arg @ref LL_CRC_POLYLENGTH_8B
|
||||
* @arg @ref LL_CRC_POLYLENGTH_7B
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySize)
|
||||
{
|
||||
MODIFY_REG(CRCx->CR, CRC_CR_POLYSIZE, PolySize);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return size of the polynomial.
|
||||
* @rmtoll CR POLYSIZE LL_CRC_GetPolynomialSize
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_CRC_POLYLENGTH_32B
|
||||
* @arg @ref LL_CRC_POLYLENGTH_16B
|
||||
* @arg @ref LL_CRC_POLYLENGTH_8B
|
||||
* @arg @ref LL_CRC_POLYLENGTH_7B
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE));
|
||||
}
|
||||
#endif /* CRC_POL_POL */
|
||||
|
||||
/**
|
||||
* @brief Configure the reversal of the bit order of the input data
|
||||
* @rmtoll CR REV_IN LL_CRC_SetInputDataReverseMode
|
||||
* @param CRCx CRC Instance
|
||||
* @param ReverseMode This parameter can be one of the following values:
|
||||
* @arg @ref LL_CRC_INDATA_REVERSE_NONE
|
||||
* @arg @ref LL_CRC_INDATA_REVERSE_BYTE
|
||||
* @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
|
||||
* @arg @ref LL_CRC_INDATA_REVERSE_WORD
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
|
||||
{
|
||||
MODIFY_REG(CRCx->CR, CRC_CR_REV_IN, ReverseMode);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return type of reversal for input data bit order
|
||||
* @rmtoll CR REV_IN LL_CRC_GetInputDataReverseMode
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_CRC_INDATA_REVERSE_NONE
|
||||
* @arg @ref LL_CRC_INDATA_REVERSE_BYTE
|
||||
* @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
|
||||
* @arg @ref LL_CRC_INDATA_REVERSE_WORD
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the reversal of the bit order of the Output data
|
||||
* @rmtoll CR REV_OUT LL_CRC_SetOutputDataReverseMode
|
||||
* @param CRCx CRC Instance
|
||||
* @param ReverseMode This parameter can be one of the following values:
|
||||
* @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
|
||||
* @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
|
||||
{
|
||||
MODIFY_REG(CRCx->CR, CRC_CR_REV_OUT, ReverseMode);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return type of reversal of the bit order of the Output data
|
||||
* @rmtoll CR REV_OUT LL_CRC_GetOutputDataReverseMode
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
|
||||
* @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the Programmable initial CRC value.
|
||||
* @note If the CRC size is less than 32 bits, the least significant bits
|
||||
* are used to write the correct value
|
||||
* @note LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter.
|
||||
* @rmtoll INIT INIT LL_CRC_SetInitialData
|
||||
* @param CRCx CRC Instance
|
||||
* @param InitCrc Value to be programmed in Programmable initial CRC value register
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc)
|
||||
{
|
||||
WRITE_REG(CRCx->INIT, InitCrc);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return current Initial CRC value.
|
||||
* @note If the CRC size is less than 32 bits, the least significant bits
|
||||
* are used to read the correct value
|
||||
* @rmtoll INIT INIT LL_CRC_GetInitialData
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Value programmed in Programmable initial CRC value register
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetInitialData(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(CRCx->INIT));
|
||||
}
|
||||
|
||||
#if defined(CRC_POL_POL)
|
||||
/**
|
||||
* @brief Initialize the Programmable polynomial value
|
||||
* (coefficients of the polynomial to be used for CRC calculation).
|
||||
* @note LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter.
|
||||
* @note Please check Reference Manual and existing Errata Sheets,
|
||||
* regarding possible limitations for Polynomial values usage.
|
||||
* For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
|
||||
* @rmtoll POL POL LL_CRC_SetPolynomialCoef
|
||||
* @param CRCx CRC Instance
|
||||
* @param PolynomCoef Value to be programmed in Programmable Polynomial value register
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t PolynomCoef)
|
||||
{
|
||||
WRITE_REG(CRCx->POL, PolynomCoef);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return current Programmable polynomial value
|
||||
* @note Please check Reference Manual and existing Errata Sheets,
|
||||
* regarding possible limitations for Polynomial values usage.
|
||||
* For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
|
||||
* @rmtoll POL POL LL_CRC_GetPolynomialCoef
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Value programmed in Programmable Polynomial value register
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(CRCx->POL));
|
||||
}
|
||||
#endif /* CRC_POL_POL */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_LL_EF_Data_Management Data_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write given 32-bit data to the CRC calculator
|
||||
* @rmtoll DR DR LL_CRC_FeedData32
|
||||
* @param CRCx CRC Instance
|
||||
* @param InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
|
||||
{
|
||||
WRITE_REG(CRCx->DR, InData);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write given 16-bit data to the CRC calculator
|
||||
* @rmtoll DR DR LL_CRC_FeedData16
|
||||
* @param CRCx CRC Instance
|
||||
* @param InData 16 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData)
|
||||
{
|
||||
__IO uint16_t *pReg;
|
||||
|
||||
pReg = (__IO uint16_t *)(__IO void *)(&CRCx->DR); /* Derogation MisraC2012 R.11.5 */
|
||||
*pReg = InData;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write given 8-bit data to the CRC calculator
|
||||
* @rmtoll DR DR LL_CRC_FeedData8
|
||||
* @param CRCx CRC Instance
|
||||
* @param InData 8 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData)
|
||||
{
|
||||
*(uint8_t __IO *)(&CRCx->DR) = (uint8_t) InData;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return current CRC calculation result. 32 bits value is returned.
|
||||
* @rmtoll DR DR LL_CRC_ReadData32
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_ReadData32(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(CRCx->DR));
|
||||
}
|
||||
|
||||
#if defined(CRC_POL_POL)
|
||||
/**
|
||||
* @brief Return current CRC calculation result. 16 bits value is returned.
|
||||
* @note This function is expected to be used in a 16 bits CRC polynomial size context.
|
||||
* @rmtoll DR DR LL_CRC_ReadData16
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Current CRC calculation result as stored in CRC_DR register (16 bits).
|
||||
*/
|
||||
__STATIC_INLINE uint16_t LL_CRC_ReadData16(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint16_t)READ_REG(CRCx->DR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return current CRC calculation result. 8 bits value is returned.
|
||||
* @note This function is expected to be used in a 8 bits CRC polynomial size context.
|
||||
* @rmtoll DR DR LL_CRC_ReadData8
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Current CRC calculation result as stored in CRC_DR register (8 bits).
|
||||
*/
|
||||
__STATIC_INLINE uint8_t LL_CRC_ReadData8(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint8_t)READ_REG(CRCx->DR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return current CRC calculation result. 7 bits value is returned.
|
||||
* @note This function is expected to be used in a 7 bits CRC polynomial size context.
|
||||
* @rmtoll DR DR LL_CRC_ReadData7
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Current CRC calculation result as stored in CRC_DR register (7 bits).
|
||||
*/
|
||||
__STATIC_INLINE uint8_t LL_CRC_ReadData7(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU);
|
||||
}
|
||||
#endif /* CRC_POL_POL */
|
||||
|
||||
/**
|
||||
* @brief Return data stored in the Independent Data(IDR) register.
|
||||
* @note This register can be used as a temporary storage location for one byte.
|
||||
* @rmtoll IDR IDR LL_CRC_Read_IDR
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Value stored in CRC_IDR register (General-purpose 8-bit data register).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(CRCx->IDR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Store data in the Independent Data(IDR) register.
|
||||
* @note This register can be used as a temporary storage location for one byte.
|
||||
* @rmtoll IDR IDR LL_CRC_Write_IDR
|
||||
* @param CRCx CRC Instance
|
||||
* @param InData value to be stored in CRC_IDR register (8-bit) between Min_Data=0 and Max_Data=0xFF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
|
||||
{
|
||||
*((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData;
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined(CRC) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F0xx_LL_CRC_H */
|
||||
780
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_crs.h
Normal file
780
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_crs.h
Normal file
@@ -0,0 +1,780 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_ll_crs.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CRS LL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0xx_LL_CRS_H
|
||||
#define __STM32F0xx_LL_CRS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(CRS)
|
||||
|
||||
/** @defgroup CRS_LL CRS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
|
||||
* @brief Flags defines which can be used with LL_CRS_ReadReg function
|
||||
* @{
|
||||
*/
|
||||
#define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
|
||||
#define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
|
||||
#define LL_CRS_ISR_ERRF CRS_ISR_ERRF
|
||||
#define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
|
||||
#define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
|
||||
#define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
|
||||
#define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EC_IT IT Defines
|
||||
* @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions
|
||||
* @{
|
||||
*/
|
||||
#define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
|
||||
#define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
|
||||
#define LL_CRS_CR_ERRIE CRS_CR_ERRIE
|
||||
#define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
|
||||
* @{
|
||||
*/
|
||||
#define LL_CRS_SYNC_DIV_1 ((uint32_t)0x00U) /*!< Synchro Signal not divided (default) */
|
||||
#define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
|
||||
#define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
|
||||
#define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
|
||||
#define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
|
||||
#define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
|
||||
#define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
|
||||
#define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
|
||||
* @{
|
||||
*/
|
||||
#define LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal source GPIO */
|
||||
#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
|
||||
#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
|
||||
* @{
|
||||
*/
|
||||
#define LL_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00U) /*!< Synchro Active on rising edge (default) */
|
||||
#define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
|
||||
* @{
|
||||
*/
|
||||
#define LL_CRS_FREQ_ERROR_DIR_UP ((uint32_t)0x00U) /*!< Upcounting direction, the actual frequency is above the target */
|
||||
#define LL_CRS_FREQ_ERROR_DIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Reset value of the RELOAD field
|
||||
* @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
|
||||
* and a synchronization signal frequency of 1 kHz (SOF signal from USB)
|
||||
*/
|
||||
#define LL_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU)
|
||||
|
||||
/**
|
||||
* @brief Reset value of Frequency error limit.
|
||||
*/
|
||||
#define LL_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U)
|
||||
|
||||
/**
|
||||
* @brief Reset value of the HSI48 Calibration field
|
||||
* @note The default value is 32, which corresponds to the middle of the trimming interval.
|
||||
* The trimming step is around 67 kHz between two consecutive TRIM steps.
|
||||
* A higher TRIM value corresponds to a higher output frequency
|
||||
*/
|
||||
#define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write a value in CRS register
|
||||
* @param __INSTANCE__ CRS Instance
|
||||
* @param __REG__ Register to be written
|
||||
* @param __VALUE__ Value to be written in the register
|
||||
* @retval None
|
||||
*/
|
||||
#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Read a value in CRS register
|
||||
* @param __INSTANCE__ CRS Instance
|
||||
* @param __REG__ Register to be read
|
||||
* @retval Register value
|
||||
*/
|
||||
#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
|
||||
* @note The RELOAD value should be selected according to the ratio between
|
||||
* the target frequency and the frequency of the synchronization source after
|
||||
* prescaling. It is then decreased by one in order to reach the expected
|
||||
* synchronization on the zero value. The formula is the following:
|
||||
* RELOAD = (fTARGET / fSYNC) -1
|
||||
* @param __FTARGET__ Target frequency (value in Hz)
|
||||
* @param __FSYNC__ Synchronization signal frequency (value in Hz)
|
||||
* @retval Reload value (in Hz)
|
||||
*/
|
||||
#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EF_Configuration Configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable Frequency error counter
|
||||
* @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
|
||||
* @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
|
||||
{
|
||||
SET_BIT(CRS->CR, CRS_CR_CEN);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Frequency error counter
|
||||
* @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
|
||||
{
|
||||
CLEAR_BIT(CRS->CR, CRS_CR_CEN);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Frequency error counter is enabled or not
|
||||
* @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
|
||||
{
|
||||
return (READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Automatic trimming counter
|
||||
* @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
|
||||
{
|
||||
SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Automatic trimming counter
|
||||
* @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
|
||||
{
|
||||
CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Automatic trimming is enabled or not
|
||||
* @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
|
||||
{
|
||||
return (READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set HSI48 oscillator smooth trimming
|
||||
* @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
|
||||
* @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming
|
||||
* @param Value a number between Min_Data = 0 and Max_Data = 63
|
||||
* @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
|
||||
{
|
||||
MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get HSI48 oscillator smooth trimming
|
||||
* @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming
|
||||
* @retval a number between Min_Data = 0 and Max_Data = 63
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set counter reload value
|
||||
* @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter
|
||||
* @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF
|
||||
* @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
|
||||
* Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
|
||||
{
|
||||
MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get counter reload value
|
||||
* @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter
|
||||
* @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set frequency error limit
|
||||
* @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit
|
||||
* @param Value a number between Min_Data = 0 and Max_Data = 255
|
||||
* @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
|
||||
{
|
||||
MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get frequency error limit
|
||||
* @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit
|
||||
* @retval A number between Min_Data = 0 and Max_Data = 255
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set division factor for SYNC signal
|
||||
* @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider
|
||||
* @param Divider This parameter can be one of the following values:
|
||||
* @arg @ref LL_CRS_SYNC_DIV_1
|
||||
* @arg @ref LL_CRS_SYNC_DIV_2
|
||||
* @arg @ref LL_CRS_SYNC_DIV_4
|
||||
* @arg @ref LL_CRS_SYNC_DIV_8
|
||||
* @arg @ref LL_CRS_SYNC_DIV_16
|
||||
* @arg @ref LL_CRS_SYNC_DIV_32
|
||||
* @arg @ref LL_CRS_SYNC_DIV_64
|
||||
* @arg @ref LL_CRS_SYNC_DIV_128
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
|
||||
{
|
||||
MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get division factor for SYNC signal
|
||||
* @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_CRS_SYNC_DIV_1
|
||||
* @arg @ref LL_CRS_SYNC_DIV_2
|
||||
* @arg @ref LL_CRS_SYNC_DIV_4
|
||||
* @arg @ref LL_CRS_SYNC_DIV_8
|
||||
* @arg @ref LL_CRS_SYNC_DIV_16
|
||||
* @arg @ref LL_CRS_SYNC_DIV_32
|
||||
* @arg @ref LL_CRS_SYNC_DIV_64
|
||||
* @arg @ref LL_CRS_SYNC_DIV_128
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set SYNC signal source
|
||||
* @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource
|
||||
* @param Source This parameter can be one of the following values:
|
||||
* @arg @ref LL_CRS_SYNC_SOURCE_GPIO
|
||||
* @arg @ref LL_CRS_SYNC_SOURCE_LSE
|
||||
* @arg @ref LL_CRS_SYNC_SOURCE_USB
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
|
||||
{
|
||||
MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get SYNC signal source
|
||||
* @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_CRS_SYNC_SOURCE_GPIO
|
||||
* @arg @ref LL_CRS_SYNC_SOURCE_LSE
|
||||
* @arg @ref LL_CRS_SYNC_SOURCE_USB
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set input polarity for the SYNC signal source
|
||||
* @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity
|
||||
* @param Polarity This parameter can be one of the following values:
|
||||
* @arg @ref LL_CRS_SYNC_POLARITY_RISING
|
||||
* @arg @ref LL_CRS_SYNC_POLARITY_FALLING
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
|
||||
{
|
||||
MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get input polarity for the SYNC signal source
|
||||
* @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_CRS_SYNC_POLARITY_RISING
|
||||
* @arg @ref LL_CRS_SYNC_POLARITY_FALLING
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure CRS for the synchronization
|
||||
* @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n
|
||||
* CFGR RELOAD LL_CRS_ConfigSynchronization\n
|
||||
* CFGR FELIM LL_CRS_ConfigSynchronization\n
|
||||
* CFGR SYNCDIV LL_CRS_ConfigSynchronization\n
|
||||
* CFGR SYNCSRC LL_CRS_ConfigSynchronization\n
|
||||
* CFGR SYNCPOL LL_CRS_ConfigSynchronization
|
||||
* @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
|
||||
* @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
|
||||
* @param ReloadValue a number between Min_Data = 0 and Max_Data = 255
|
||||
* @param Settings This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
|
||||
* or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
|
||||
* @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
|
||||
* @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
|
||||
{
|
||||
MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue << CRS_CR_TRIM_Pos);
|
||||
MODIFY_REG(CRS->CFGR,
|
||||
CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
|
||||
ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EF_CRS_Management CRS_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Generate software SYNC event
|
||||
* @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
|
||||
{
|
||||
SET_BIT(CRS->CR, CRS_CR_SWSYNC);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the frequency error direction latched in the time of the last
|
||||
* SYNC event
|
||||
* @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
|
||||
* @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the frequency error counter value latched in the time of the last SYNC event
|
||||
* @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture
|
||||
* @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Check if SYNC event OK signal occurred or not
|
||||
* @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
|
||||
{
|
||||
return (READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if SYNC warning signal occurred or not
|
||||
* @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
|
||||
{
|
||||
return (READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Synchronization or trimming error signal occurred or not
|
||||
* @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
|
||||
{
|
||||
return (READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Expected SYNC signal occurred or not
|
||||
* @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
|
||||
{
|
||||
return (READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if SYNC error signal occurred or not
|
||||
* @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
|
||||
{
|
||||
return (READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if SYNC missed error signal occurred or not
|
||||
* @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
|
||||
{
|
||||
return (READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Trimming overflow or underflow occurred or not
|
||||
* @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
|
||||
{
|
||||
return (READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear the SYNC event OK flag
|
||||
* @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
|
||||
{
|
||||
WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear the SYNC warning flag
|
||||
* @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
|
||||
{
|
||||
WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
|
||||
* the ERR flag
|
||||
* @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
|
||||
{
|
||||
WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Expected SYNC flag
|
||||
* @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
|
||||
{
|
||||
WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EF_IT_Management IT_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable SYNC event OK interrupt
|
||||
* @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
|
||||
{
|
||||
SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable SYNC event OK interrupt
|
||||
* @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
|
||||
{
|
||||
CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if SYNC event OK interrupt is enabled or not
|
||||
* @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
|
||||
{
|
||||
return (READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable SYNC warning interrupt
|
||||
* @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
|
||||
{
|
||||
SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable SYNC warning interrupt
|
||||
* @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
|
||||
{
|
||||
CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if SYNC warning interrupt is enabled or not
|
||||
* @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
|
||||
{
|
||||
return (READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Synchronization or trimming error interrupt
|
||||
* @rmtoll CR ERRIE LL_CRS_EnableIT_ERR
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
|
||||
{
|
||||
SET_BIT(CRS->CR, CRS_CR_ERRIE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Synchronization or trimming error interrupt
|
||||
* @rmtoll CR ERRIE LL_CRS_DisableIT_ERR
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
|
||||
{
|
||||
CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Synchronization or trimming error interrupt is enabled or not
|
||||
* @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
|
||||
{
|
||||
return (READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Expected SYNC interrupt
|
||||
* @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
|
||||
{
|
||||
SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Expected SYNC interrupt
|
||||
* @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
|
||||
{
|
||||
CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Expected SYNC interrupt is enabled or not
|
||||
* @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
|
||||
{
|
||||
return (READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
ErrorStatus LL_CRS_DeInit(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined(CRS) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0xx_LL_CRS_H */
|
||||
1420
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_dac.h
Normal file
1420
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_dac.h
Normal file
File diff suppressed because it is too large
Load Diff
2234
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_dma.h
Normal file
2234
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_dma.h
Normal file
File diff suppressed because it is too large
Load Diff
1014
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h
Normal file
1014
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h
Normal file
File diff suppressed because it is too large
Load Diff
938
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h
Normal file
938
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h
Normal file
@@ -0,0 +1,938 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_ll_gpio.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of GPIO LL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0xx_LL_GPIO_H
|
||||
#define __STM32F0xx_LL_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF)
|
||||
|
||||
/** @defgroup GPIO_LL GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /*USE_FULL_LL_DRIVER*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief LL GPIO Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_LL_EC_PIN */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_LL_EC_MODE.
|
||||
|
||||
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
|
||||
|
||||
uint32_t Speed; /*!< Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_LL_EC_SPEED.
|
||||
|
||||
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
|
||||
|
||||
uint32_t OutputType; /*!< Specifies the operating output type for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
|
||||
|
||||
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
|
||||
|
||||
uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_LL_EC_PULL.
|
||||
|
||||
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
|
||||
|
||||
uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins.
|
||||
This parameter can be a value of @ref GPIO_LL_EC_AF.
|
||||
|
||||
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
|
||||
} LL_GPIO_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_LL_EC_PIN PIN
|
||||
* @{
|
||||
*/
|
||||
#define LL_GPIO_PIN_0 GPIO_BSRR_BS_0 /*!< Select pin 0 */
|
||||
#define LL_GPIO_PIN_1 GPIO_BSRR_BS_1 /*!< Select pin 1 */
|
||||
#define LL_GPIO_PIN_2 GPIO_BSRR_BS_2 /*!< Select pin 2 */
|
||||
#define LL_GPIO_PIN_3 GPIO_BSRR_BS_3 /*!< Select pin 3 */
|
||||
#define LL_GPIO_PIN_4 GPIO_BSRR_BS_4 /*!< Select pin 4 */
|
||||
#define LL_GPIO_PIN_5 GPIO_BSRR_BS_5 /*!< Select pin 5 */
|
||||
#define LL_GPIO_PIN_6 GPIO_BSRR_BS_6 /*!< Select pin 6 */
|
||||
#define LL_GPIO_PIN_7 GPIO_BSRR_BS_7 /*!< Select pin 7 */
|
||||
#define LL_GPIO_PIN_8 GPIO_BSRR_BS_8 /*!< Select pin 8 */
|
||||
#define LL_GPIO_PIN_9 GPIO_BSRR_BS_9 /*!< Select pin 9 */
|
||||
#define LL_GPIO_PIN_10 GPIO_BSRR_BS_10 /*!< Select pin 10 */
|
||||
#define LL_GPIO_PIN_11 GPIO_BSRR_BS_11 /*!< Select pin 11 */
|
||||
#define LL_GPIO_PIN_12 GPIO_BSRR_BS_12 /*!< Select pin 12 */
|
||||
#define LL_GPIO_PIN_13 GPIO_BSRR_BS_13 /*!< Select pin 13 */
|
||||
#define LL_GPIO_PIN_14 GPIO_BSRR_BS_14 /*!< Select pin 14 */
|
||||
#define LL_GPIO_PIN_15 GPIO_BSRR_BS_15 /*!< Select pin 15 */
|
||||
#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1 | GPIO_BSRR_BS_2 | \
|
||||
GPIO_BSRR_BS_3 | GPIO_BSRR_BS_4 | GPIO_BSRR_BS_5 | \
|
||||
GPIO_BSRR_BS_6 | GPIO_BSRR_BS_7 | GPIO_BSRR_BS_8 | \
|
||||
GPIO_BSRR_BS_9 | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \
|
||||
GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \
|
||||
GPIO_BSRR_BS_15) /*!< Select all pins */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_LL_EC_MODE Mode
|
||||
* @{
|
||||
*/
|
||||
#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */
|
||||
#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODER0_0 /*!< Select output mode */
|
||||
#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODER0_1 /*!< Select alternate function mode */
|
||||
#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODER0 /*!< Select analog mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_LL_EC_OUTPUT Output Type
|
||||
* @{
|
||||
*/
|
||||
#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */
|
||||
#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_LL_EC_SPEED Output Speed
|
||||
* @{
|
||||
*/
|
||||
#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */
|
||||
#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEEDR0_0 /*!< Select I/O medium output speed */
|
||||
#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEEDR0 /*!< Select I/O high output speed */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#define LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW
|
||||
#define LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM
|
||||
#define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_HIGH
|
||||
|
||||
/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
|
||||
* @{
|
||||
*/
|
||||
#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */
|
||||
#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */
|
||||
#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_LL_EC_AF Alternate Function
|
||||
* @{
|
||||
*/
|
||||
#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */
|
||||
#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */
|
||||
#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */
|
||||
#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */
|
||||
#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */
|
||||
#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */
|
||||
#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */
|
||||
#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write a value in GPIO register
|
||||
* @param __INSTANCE__ GPIO Instance
|
||||
* @param __REG__ Register to be written
|
||||
* @param __VALUE__ Value to be written in the register
|
||||
* @retval None
|
||||
*/
|
||||
#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Read a value in GPIO register
|
||||
* @param __INSTANCE__ GPIO Instance
|
||||
* @param __REG__ Register to be read
|
||||
* @retval Register value
|
||||
*/
|
||||
#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configure gpio mode for a dedicated pin on dedicated port.
|
||||
* @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
|
||||
* @note Warning: only one pin can be passed as parameter.
|
||||
* @rmtoll MODER MODEy LL_GPIO_SetPinMode
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @param Mode This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_MODE_INPUT
|
||||
* @arg @ref LL_GPIO_MODE_OUTPUT
|
||||
* @arg @ref LL_GPIO_MODE_ALTERNATE
|
||||
* @arg @ref LL_GPIO_MODE_ANALOG
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
|
||||
{
|
||||
MODIFY_REG(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODER0), ((Pin * Pin) * Mode));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return gpio mode for a dedicated pin on dedicated port.
|
||||
* @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
|
||||
* @note Warning: only one pin can be passed as parameter.
|
||||
* @rmtoll MODER MODEy LL_GPIO_GetPinMode
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_GPIO_MODE_INPUT
|
||||
* @arg @ref LL_GPIO_MODE_OUTPUT
|
||||
* @arg @ref LL_GPIO_MODE_ALTERNATE
|
||||
* @arg @ref LL_GPIO_MODE_ANALOG
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODER0)) / (Pin * Pin));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure gpio output type for several pins on dedicated port.
|
||||
* @note Output type as to be set when gpio pin is in output or
|
||||
* alternate modes. Possible type are Push-pull or Open-drain.
|
||||
* @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType
|
||||
* @param GPIOx GPIO Port
|
||||
* @param PinMask This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @arg @ref LL_GPIO_PIN_ALL
|
||||
* @param OutputType This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_OUTPUT_PUSHPULL
|
||||
* @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
|
||||
{
|
||||
MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return gpio output type for several pins on dedicated port.
|
||||
* @note Output type as to be set when gpio pin is in output or
|
||||
* alternate modes. Possible type are Push-pull or Open-drain.
|
||||
* @note Warning: only one pin can be passed as parameter.
|
||||
* @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @arg @ref LL_GPIO_PIN_ALL
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_GPIO_OUTPUT_PUSHPULL
|
||||
* @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure gpio speed for a dedicated pin on dedicated port.
|
||||
* @note I/O speed can be Low, Medium, Fast or High speed.
|
||||
* @note Warning: only one pin can be passed as parameter.
|
||||
* @note Refer to datasheet for frequency specifications and the power
|
||||
* supply and load conditions for each speed.
|
||||
* @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @param Speed This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_SPEED_FREQ_LOW
|
||||
* @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
|
||||
* @arg @ref LL_GPIO_SPEED_FREQ_HIGH
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
|
||||
{
|
||||
MODIFY_REG(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEEDR0), ((Pin * Pin) * Speed));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return gpio speed for a dedicated pin on dedicated port.
|
||||
* @note I/O speed can be Low, Medium, Fast or High speed.
|
||||
* @note Warning: only one pin can be passed as parameter.
|
||||
* @note Refer to datasheet for frequency specifications and the power
|
||||
* supply and load conditions for each speed.
|
||||
* @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_GPIO_SPEED_FREQ_LOW
|
||||
* @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
|
||||
* @arg @ref LL_GPIO_SPEED_FREQ_HIGH
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEEDR0)) / (Pin * Pin));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
|
||||
* @note Warning: only one pin can be passed as parameter.
|
||||
* @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @param Pull This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PULL_NO
|
||||
* @arg @ref LL_GPIO_PULL_UP
|
||||
* @arg @ref LL_GPIO_PULL_DOWN
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
|
||||
{
|
||||
MODIFY_REG(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPDR0), ((Pin * Pin) * Pull));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
|
||||
* @note Warning: only one pin can be passed as parameter.
|
||||
* @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PULL_NO
|
||||
* @arg @ref LL_GPIO_PULL_UP
|
||||
* @arg @ref LL_GPIO_PULL_DOWN
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPDR0)) / (Pin * Pin));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
|
||||
* @note Possible values are from AF0 to AF7 depending on target.
|
||||
* @note Warning: only one pin can be passed as parameter.
|
||||
* @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @param Alternate This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_AF_0
|
||||
* @arg @ref LL_GPIO_AF_1
|
||||
* @arg @ref LL_GPIO_AF_2
|
||||
* @arg @ref LL_GPIO_AF_3
|
||||
* @arg @ref LL_GPIO_AF_4
|
||||
* @arg @ref LL_GPIO_AF_5
|
||||
* @arg @ref LL_GPIO_AF_6
|
||||
* @arg @ref LL_GPIO_AF_7
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
|
||||
{
|
||||
MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0),
|
||||
((((Pin * Pin) * Pin) * Pin) * Alternate));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
|
||||
* @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_GPIO_AF_0
|
||||
* @arg @ref LL_GPIO_AF_1
|
||||
* @arg @ref LL_GPIO_AF_2
|
||||
* @arg @ref LL_GPIO_AF_3
|
||||
* @arg @ref LL_GPIO_AF_4
|
||||
* @arg @ref LL_GPIO_AF_5
|
||||
* @arg @ref LL_GPIO_AF_6
|
||||
* @arg @ref LL_GPIO_AF_7
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(GPIOx->AFR[0],
|
||||
((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pin) * Pin));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
|
||||
* @note Possible values are from AF0 to AF7 depending on target.
|
||||
* @note Warning: only one pin can be passed as parameter.
|
||||
* @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @param Alternate This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_AF_0
|
||||
* @arg @ref LL_GPIO_AF_1
|
||||
* @arg @ref LL_GPIO_AF_2
|
||||
* @arg @ref LL_GPIO_AF_3
|
||||
* @arg @ref LL_GPIO_AF_4
|
||||
* @arg @ref LL_GPIO_AF_5
|
||||
* @arg @ref LL_GPIO_AF_6
|
||||
* @arg @ref LL_GPIO_AF_7
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
|
||||
{
|
||||
MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8),
|
||||
(((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * Alternate));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
|
||||
* @note Possible values are from AF0 to AF7 depending on target.
|
||||
* @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_GPIO_AF_0
|
||||
* @arg @ref LL_GPIO_AF_1
|
||||
* @arg @ref LL_GPIO_AF_2
|
||||
* @arg @ref LL_GPIO_AF_3
|
||||
* @arg @ref LL_GPIO_AF_4
|
||||
* @arg @ref LL_GPIO_AF_5
|
||||
* @arg @ref LL_GPIO_AF_6
|
||||
* @arg @ref LL_GPIO_AF_7
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(GPIOx->AFR[1],
|
||||
(((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8)) / ((((Pin >> 8U) *
|
||||
(Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Lock configuration of several pins for a dedicated port.
|
||||
* @note When the lock sequence has been applied on a port bit, the
|
||||
* value of this port bit can no longer be modified until the
|
||||
* next reset.
|
||||
* @note Each lock bit freezes a specific configuration register
|
||||
* (control and alternate function registers).
|
||||
* @rmtoll LCKR LCKK LL_GPIO_LockPin
|
||||
* @param GPIOx GPIO Port
|
||||
* @param PinMask This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @arg @ref LL_GPIO_PIN_ALL
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
||||
{
|
||||
__IO uint32_t temp;
|
||||
WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
|
||||
WRITE_REG(GPIOx->LCKR, PinMask);
|
||||
WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
|
||||
temp = READ_REG(GPIOx->LCKR);
|
||||
(void) temp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
|
||||
* @rmtoll LCKR LCKy LL_GPIO_IsPinLocked
|
||||
* @param GPIOx GPIO Port
|
||||
* @param PinMask This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @arg @ref LL_GPIO_PIN_ALL
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
||||
{
|
||||
return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return 1 if one of the pin of a dedicated port is locked. else return 0.
|
||||
* @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked
|
||||
* @param GPIOx GPIO Port
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
|
||||
{
|
||||
return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_LL_EF_Data_Access Data Access
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Return full input data register value for a dedicated port.
|
||||
* @rmtoll IDR IDy LL_GPIO_ReadInputPort
|
||||
* @param GPIOx GPIO Port
|
||||
* @retval Input data register value of port
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(GPIOx->IDR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return if input data level for several pins of dedicated port is high or low.
|
||||
* @rmtoll IDR IDy LL_GPIO_IsInputPinSet
|
||||
* @param GPIOx GPIO Port
|
||||
* @param PinMask This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @arg @ref LL_GPIO_PIN_ALL
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
||||
{
|
||||
return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write output data register for the port.
|
||||
* @rmtoll ODR ODy LL_GPIO_WriteOutputPort
|
||||
* @param GPIOx GPIO Port
|
||||
* @param PortValue Level value for each pin of the port
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
|
||||
{
|
||||
WRITE_REG(GPIOx->ODR, PortValue);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return full output data register value for a dedicated port.
|
||||
* @rmtoll ODR ODy LL_GPIO_ReadOutputPort
|
||||
* @param GPIOx GPIO Port
|
||||
* @retval Output data register value of port
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(GPIOx->ODR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return if input data level for several pins of dedicated port is high or low.
|
||||
* @rmtoll ODR ODy LL_GPIO_IsOutputPinSet
|
||||
* @param GPIOx GPIO Port
|
||||
* @param PinMask This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @arg @ref LL_GPIO_PIN_ALL
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
||||
{
|
||||
return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set several pins to high level on dedicated gpio port.
|
||||
* @rmtoll BSRR BSy LL_GPIO_SetOutputPin
|
||||
* @param GPIOx GPIO Port
|
||||
* @param PinMask This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @arg @ref LL_GPIO_PIN_ALL
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
||||
{
|
||||
WRITE_REG(GPIOx->BSRR, PinMask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set several pins to low level on dedicated gpio port.
|
||||
* @rmtoll BRR BRy LL_GPIO_ResetOutputPin
|
||||
* @param GPIOx GPIO Port
|
||||
* @param PinMask This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @arg @ref LL_GPIO_PIN_ALL
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
||||
{
|
||||
WRITE_REG(GPIOx->BRR, PinMask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Toggle data value for several pin of dedicated port.
|
||||
* @rmtoll ODR ODy LL_GPIO_TogglePin
|
||||
* @param GPIOx GPIO Port
|
||||
* @param PinMask This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @arg @ref LL_GPIO_PIN_ALL
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
||||
{
|
||||
uint32_t odr = READ_REG(GPIOx->ODR);
|
||||
WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
|
||||
ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
|
||||
void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0xx_LL_GPIO_H */
|
||||
|
||||
2281
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_i2c.h
Normal file
2281
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_i2c.h
Normal file
File diff suppressed because it is too large
Load Diff
338
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_iwdg.h
Normal file
338
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_iwdg.h
Normal file
@@ -0,0 +1,338 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_ll_iwdg.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of IWDG LL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F0xx_LL_IWDG_H
|
||||
#define STM32F0xx_LL_IWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(IWDG)
|
||||
|
||||
/** @defgroup IWDG_LL IWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */
|
||||
#define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */
|
||||
#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */
|
||||
#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
|
||||
* @brief Flags defines which can be used with LL_IWDG_ReadReg function
|
||||
* @{
|
||||
*/
|
||||
#define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */
|
||||
#define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */
|
||||
#define LL_IWDG_SR_WVU IWDG_SR_WVU /*!< Watchdog counter window value update */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider
|
||||
* @{
|
||||
*/
|
||||
#define LL_IWDG_PRESCALER_4 0x00000000U /*!< Divider by 4 */
|
||||
#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */
|
||||
#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */
|
||||
#define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */
|
||||
#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2) /*!< Divider by 64 */
|
||||
#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */
|
||||
#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< Divider by 256 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write a value in IWDG register
|
||||
* @param __INSTANCE__ IWDG Instance
|
||||
* @param __REG__ Register to be written
|
||||
* @param __VALUE__ Value to be written in the register
|
||||
* @retval None
|
||||
*/
|
||||
#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Read a value in IWDG register
|
||||
* @param __INSTANCE__ IWDG Instance
|
||||
* @param __REG__ Register to be read
|
||||
* @retval Register value
|
||||
*/
|
||||
#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup IWDG_LL_EF_Configuration Configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Start the Independent Watchdog
|
||||
* @note Except if the hardware watchdog option is selected
|
||||
* @rmtoll KR KEY LL_IWDG_Enable
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reloads IWDG counter with value defined in the reload register
|
||||
* @rmtoll KR KEY LL_IWDG_ReloadCounter
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
|
||||
* @rmtoll KR KEY LL_IWDG_EnableWriteAccess
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
|
||||
* @rmtoll KR KEY LL_IWDG_DisableWriteAccess
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Select the prescaler of the IWDG
|
||||
* @rmtoll PR PR LL_IWDG_SetPrescaler
|
||||
* @param IWDGx IWDG Instance
|
||||
* @param Prescaler This parameter can be one of the following values:
|
||||
* @arg @ref LL_IWDG_PRESCALER_4
|
||||
* @arg @ref LL_IWDG_PRESCALER_8
|
||||
* @arg @ref LL_IWDG_PRESCALER_16
|
||||
* @arg @ref LL_IWDG_PRESCALER_32
|
||||
* @arg @ref LL_IWDG_PRESCALER_64
|
||||
* @arg @ref LL_IWDG_PRESCALER_128
|
||||
* @arg @ref LL_IWDG_PRESCALER_256
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)
|
||||
{
|
||||
WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the selected prescaler of the IWDG
|
||||
* @rmtoll PR PR LL_IWDG_GetPrescaler
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_IWDG_PRESCALER_4
|
||||
* @arg @ref LL_IWDG_PRESCALER_8
|
||||
* @arg @ref LL_IWDG_PRESCALER_16
|
||||
* @arg @ref LL_IWDG_PRESCALER_32
|
||||
* @arg @ref LL_IWDG_PRESCALER_64
|
||||
* @arg @ref LL_IWDG_PRESCALER_128
|
||||
* @arg @ref LL_IWDG_PRESCALER_256
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(const IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return (READ_REG(IWDGx->PR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Specify the IWDG down-counter reload value
|
||||
* @rmtoll RLR RL LL_IWDG_SetReloadCounter
|
||||
* @param IWDGx IWDG Instance
|
||||
* @param Counter Value between Min_Data=0 and Max_Data=0x0FFF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)
|
||||
{
|
||||
WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the specified IWDG down-counter reload value
|
||||
* @rmtoll RLR RL LL_IWDG_GetReloadCounter
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval Value between Min_Data=0 and Max_Data=0x0FFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(const IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return (READ_REG(IWDGx->RLR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Specify high limit of the window value to be compared to the down-counter.
|
||||
* @rmtoll WINR WIN LL_IWDG_SetWindow
|
||||
* @param IWDGx IWDG Instance
|
||||
* @param Window Value between Min_Data=0 and Max_Data=0x0FFF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window)
|
||||
{
|
||||
WRITE_REG(IWDGx->WINR, IWDG_WINR_WIN & Window);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the high limit of the window value specified.
|
||||
* @rmtoll WINR WIN LL_IWDG_GetWindow
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval Value between Min_Data=0 and Max_Data=0x0FFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_GetWindow(const IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return (READ_REG(IWDGx->WINR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Check if flag Prescaler Value Update is set or not
|
||||
* @rmtoll SR PVU LL_IWDG_IsActiveFlag_PVU
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(const IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if flag Reload Value Update is set or not
|
||||
* @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(const IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if flag Window Value Update is set or not
|
||||
* @rmtoll SR WVU LL_IWDG_IsActiveFlag_WVU
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(const IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return ((READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not
|
||||
* @rmtoll SR PVU LL_IWDG_IsReady\n
|
||||
* SR RVU LL_IWDG_IsReady\n
|
||||
* SR WVU LL_IWDG_IsReady
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval State of bits (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_IsReady(const IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* IWDG */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F0xx_LL_IWDG_H */
|
||||
549
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_pwr.h
Normal file
549
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_pwr.h
Normal file
@@ -0,0 +1,549 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_ll_pwr.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of PWR LL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0xx_LL_PWR_H
|
||||
#define __STM32F0xx_LL_PWR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(PWR)
|
||||
|
||||
/** @defgroup PWR_LL PWR
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
|
||||
* @brief Flags defines which can be used with LL_PWR_WriteReg function
|
||||
* @{
|
||||
*/
|
||||
#define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */
|
||||
#define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
|
||||
* @brief Flags defines which can be used with LL_PWR_ReadReg function
|
||||
* @{
|
||||
*/
|
||||
#define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */
|
||||
#define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */
|
||||
#if defined(PWR_PVD_SUPPORT)
|
||||
#define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */
|
||||
#endif /* PWR_PVD_SUPPORT */
|
||||
#if defined(PWR_CSR_VREFINTRDYF)
|
||||
#define LL_PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF /*!< VREFINT ready flag */
|
||||
#endif /* PWR_CSR_VREFINTRDYF */
|
||||
#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */
|
||||
#define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */
|
||||
#if defined(PWR_CSR_EWUP3)
|
||||
#define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */
|
||||
#endif /* PWR_CSR_EWUP3 */
|
||||
#if defined(PWR_CSR_EWUP4)
|
||||
#define LL_PWR_CSR_EWUP4 PWR_CSR_EWUP4 /*!< Enable WKUP pin 4 */
|
||||
#endif /* PWR_CSR_EWUP4 */
|
||||
#if defined(PWR_CSR_EWUP5)
|
||||
#define LL_PWR_CSR_EWUP5 PWR_CSR_EWUP5 /*!< Enable WKUP pin 5 */
|
||||
#endif /* PWR_CSR_EWUP5 */
|
||||
#if defined(PWR_CSR_EWUP6)
|
||||
#define LL_PWR_CSR_EWUP6 PWR_CSR_EWUP6 /*!< Enable WKUP pin 6 */
|
||||
#endif /* PWR_CSR_EWUP6 */
|
||||
#if defined(PWR_CSR_EWUP7)
|
||||
#define LL_PWR_CSR_EWUP7 PWR_CSR_EWUP7 /*!< Enable WKUP pin 7 */
|
||||
#endif /* PWR_CSR_EWUP7 */
|
||||
#if defined(PWR_CSR_EWUP8)
|
||||
#define LL_PWR_CSR_EWUP8 PWR_CSR_EWUP8 /*!< Enable WKUP pin 8 */
|
||||
#endif /* PWR_CSR_EWUP8 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup PWR_LL_EC_MODE_PWR Mode Power
|
||||
* @{
|
||||
*/
|
||||
#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */
|
||||
#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
|
||||
#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(PWR_CR_LPDS)
|
||||
/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
|
||||
* @{
|
||||
*/
|
||||
#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */
|
||||
#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* PWR_CR_LPDS */
|
||||
|
||||
#if defined(PWR_PVD_SUPPORT)
|
||||
/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
|
||||
* @{
|
||||
*/
|
||||
#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold 0 */
|
||||
#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold 1 */
|
||||
#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold 2 */
|
||||
#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold 3 */
|
||||
#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold 4 */
|
||||
#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold 5 */
|
||||
#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold 6 */
|
||||
#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold 7 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* PWR_PVD_SUPPORT */
|
||||
/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
|
||||
* @{
|
||||
*/
|
||||
#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */
|
||||
#define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC13 */
|
||||
#if defined(PWR_CSR_EWUP3)
|
||||
#define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PE6 or PA2 according to device */
|
||||
#endif /* PWR_CSR_EWUP3 */
|
||||
#if defined(PWR_CSR_EWUP4)
|
||||
#define LL_PWR_WAKEUP_PIN4 (PWR_CSR_EWUP4) /*!< WKUP pin 4 : PA2 */
|
||||
#endif /* PWR_CSR_EWUP4 */
|
||||
#if defined(PWR_CSR_EWUP5)
|
||||
#define LL_PWR_WAKEUP_PIN5 (PWR_CSR_EWUP5) /*!< WKUP pin 5 : PC5 */
|
||||
#endif /* PWR_CSR_EWUP5 */
|
||||
#if defined(PWR_CSR_EWUP6)
|
||||
#define LL_PWR_WAKEUP_PIN6 (PWR_CSR_EWUP6) /*!< WKUP pin 6 : PB5 */
|
||||
#endif /* PWR_CSR_EWUP6 */
|
||||
#if defined(PWR_CSR_EWUP7)
|
||||
#define LL_PWR_WAKEUP_PIN7 (PWR_CSR_EWUP7) /*!< WKUP pin 7 : PB15 */
|
||||
#endif /* PWR_CSR_EWUP7 */
|
||||
#if defined(PWR_CSR_EWUP8)
|
||||
#define LL_PWR_WAKEUP_PIN8 (PWR_CSR_EWUP8) /*!< WKUP pin 8 : PF2 */
|
||||
#endif /* PWR_CSR_EWUP8 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write a value in PWR register
|
||||
* @param __REG__ Register to be written
|
||||
* @param __VALUE__ Value to be written in the register
|
||||
* @retval None
|
||||
*/
|
||||
#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Read a value in PWR register
|
||||
* @param __REG__ Register to be read
|
||||
* @retval Register value
|
||||
*/
|
||||
#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_LL_EF_Configuration Configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable access to the backup domain
|
||||
* @rmtoll CR DBP LL_PWR_EnableBkUpAccess
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
|
||||
{
|
||||
SET_BIT(PWR->CR, PWR_CR_DBP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable access to the backup domain
|
||||
* @rmtoll CR DBP LL_PWR_DisableBkUpAccess
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
|
||||
{
|
||||
CLEAR_BIT(PWR->CR, PWR_CR_DBP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if the backup domain is enabled
|
||||
* @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
|
||||
{
|
||||
return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
|
||||
}
|
||||
|
||||
#if defined(PWR_CR_LPDS)
|
||||
/**
|
||||
* @brief Set voltage Regulator mode during deep sleep mode
|
||||
* @rmtoll CR LPDS LL_PWR_SetRegulModeDS
|
||||
* @param RegulMode This parameter can be one of the following values:
|
||||
* @arg @ref LL_PWR_REGU_DSMODE_MAIN
|
||||
* @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
|
||||
{
|
||||
MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get voltage Regulator mode during deep sleep mode
|
||||
* @rmtoll CR LPDS LL_PWR_GetRegulModeDS
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_PWR_REGU_DSMODE_MAIN
|
||||
* @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
|
||||
}
|
||||
#endif /* PWR_CR_LPDS */
|
||||
|
||||
/**
|
||||
* @brief Set Power Down mode when CPU enters deepsleep
|
||||
* @rmtoll CR PDDS LL_PWR_SetPowerMode\n
|
||||
* @rmtoll CR LPDS LL_PWR_SetPowerMode
|
||||
* @param PDMode This parameter can be one of the following values:
|
||||
* @arg @ref LL_PWR_MODE_STOP_MAINREGU
|
||||
* @arg @ref LL_PWR_MODE_STOP_LPREGU
|
||||
* @arg @ref LL_PWR_MODE_STANDBY
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
|
||||
{
|
||||
MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Power Down mode when CPU enters deepsleep
|
||||
* @rmtoll CR PDDS LL_PWR_GetPowerMode\n
|
||||
* @rmtoll CR LPDS LL_PWR_GetPowerMode
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_PWR_MODE_STOP_MAINREGU
|
||||
* @arg @ref LL_PWR_MODE_STOP_LPREGU
|
||||
* @arg @ref LL_PWR_MODE_STANDBY
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
|
||||
}
|
||||
|
||||
#if defined(PWR_PVD_SUPPORT)
|
||||
/**
|
||||
* @brief Configure the voltage threshold detected by the Power Voltage Detector
|
||||
* @rmtoll CR PLS LL_PWR_SetPVDLevel
|
||||
* @param PVDLevel This parameter can be one of the following values:
|
||||
* @arg @ref LL_PWR_PVDLEVEL_0
|
||||
* @arg @ref LL_PWR_PVDLEVEL_1
|
||||
* @arg @ref LL_PWR_PVDLEVEL_2
|
||||
* @arg @ref LL_PWR_PVDLEVEL_3
|
||||
* @arg @ref LL_PWR_PVDLEVEL_4
|
||||
* @arg @ref LL_PWR_PVDLEVEL_5
|
||||
* @arg @ref LL_PWR_PVDLEVEL_6
|
||||
* @arg @ref LL_PWR_PVDLEVEL_7
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
|
||||
{
|
||||
MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the voltage threshold detection
|
||||
* @rmtoll CR PLS LL_PWR_GetPVDLevel
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_PWR_PVDLEVEL_0
|
||||
* @arg @ref LL_PWR_PVDLEVEL_1
|
||||
* @arg @ref LL_PWR_PVDLEVEL_2
|
||||
* @arg @ref LL_PWR_PVDLEVEL_3
|
||||
* @arg @ref LL_PWR_PVDLEVEL_4
|
||||
* @arg @ref LL_PWR_PVDLEVEL_5
|
||||
* @arg @ref LL_PWR_PVDLEVEL_6
|
||||
* @arg @ref LL_PWR_PVDLEVEL_7
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Power Voltage Detector
|
||||
* @rmtoll CR PVDE LL_PWR_EnablePVD
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_EnablePVD(void)
|
||||
{
|
||||
SET_BIT(PWR->CR, PWR_CR_PVDE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Power Voltage Detector
|
||||
* @rmtoll CR PVDE LL_PWR_DisablePVD
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_DisablePVD(void)
|
||||
{
|
||||
CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Power Voltage Detector is enabled
|
||||
* @rmtoll CR PVDE LL_PWR_IsEnabledPVD
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
|
||||
{
|
||||
return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
|
||||
}
|
||||
#endif /* PWR_PVD_SUPPORT */
|
||||
|
||||
/**
|
||||
* @brief Enable the WakeUp PINx functionality
|
||||
* @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n
|
||||
* @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n
|
||||
* @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin\n
|
||||
* @rmtoll CSR EWUP4 LL_PWR_EnableWakeUpPin\n
|
||||
* @rmtoll CSR EWUP5 LL_PWR_EnableWakeUpPin\n
|
||||
* @rmtoll CSR EWUP6 LL_PWR_EnableWakeUpPin\n
|
||||
* @rmtoll CSR EWUP7 LL_PWR_EnableWakeUpPin\n
|
||||
* @rmtoll CSR EWUP8 LL_PWR_EnableWakeUpPin
|
||||
* @param WakeUpPin This parameter can be one of the following values:
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN1
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN2
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN3 (*)
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN4 (*)
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN5 (*)
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN6 (*)
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN7 (*)
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN8 (*)
|
||||
*
|
||||
* (*) not available on all devices
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
|
||||
{
|
||||
SET_BIT(PWR->CSR, WakeUpPin);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the WakeUp PINx functionality
|
||||
* @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n
|
||||
* @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n
|
||||
* @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin\n
|
||||
* @rmtoll CSR EWUP4 LL_PWR_DisableWakeUpPin\n
|
||||
* @rmtoll CSR EWUP5 LL_PWR_DisableWakeUpPin\n
|
||||
* @rmtoll CSR EWUP6 LL_PWR_DisableWakeUpPin\n
|
||||
* @rmtoll CSR EWUP7 LL_PWR_DisableWakeUpPin\n
|
||||
* @rmtoll CSR EWUP8 LL_PWR_DisableWakeUpPin
|
||||
* @param WakeUpPin This parameter can be one of the following values:
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN1
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN2
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN3 (*)
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN4 (*)
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN5 (*)
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN6 (*)
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN7 (*)
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN8 (*)
|
||||
*
|
||||
* (*) not available on all devices
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
|
||||
{
|
||||
CLEAR_BIT(PWR->CSR, WakeUpPin);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if the WakeUp PINx functionality is enabled
|
||||
* @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n
|
||||
* @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n
|
||||
* @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin\n
|
||||
* @rmtoll CSR EWUP4 LL_PWR_IsEnabledWakeUpPin\n
|
||||
* @rmtoll CSR EWUP5 LL_PWR_IsEnabledWakeUpPin\n
|
||||
* @rmtoll CSR EWUP6 LL_PWR_IsEnabledWakeUpPin\n
|
||||
* @rmtoll CSR EWUP7 LL_PWR_IsEnabledWakeUpPin\n
|
||||
* @rmtoll CSR EWUP8 LL_PWR_IsEnabledWakeUpPin
|
||||
* @param WakeUpPin This parameter can be one of the following values:
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN1
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN2
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN3 (*)
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN4 (*)
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN5 (*)
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN6 (*)
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN7 (*)
|
||||
* @arg @ref LL_PWR_WAKEUP_PIN8 (*)
|
||||
*
|
||||
* (*) not available on all devices
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
|
||||
{
|
||||
return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get Wake-up Flag
|
||||
* @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
|
||||
{
|
||||
return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Standby Flag
|
||||
* @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
|
||||
{
|
||||
return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
|
||||
}
|
||||
|
||||
#if defined(PWR_PVD_SUPPORT)
|
||||
/**
|
||||
* @brief Indicate whether VDD voltage is below the selected PVD threshold
|
||||
* @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
|
||||
{
|
||||
return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
|
||||
}
|
||||
#endif /* PWR_PVD_SUPPORT */
|
||||
|
||||
#if defined(PWR_CSR_VREFINTRDYF)
|
||||
/**
|
||||
* @brief Get Internal Reference VrefInt Flag
|
||||
* @rmtoll CSR VREFINTRDYF LL_PWR_IsActiveFlag_VREFINTRDY
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY(void)
|
||||
{
|
||||
return (READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == (PWR_CSR_VREFINTRDYF));
|
||||
}
|
||||
#endif /* PWR_CSR_VREFINTRDYF */
|
||||
/**
|
||||
* @brief Clear Standby Flag
|
||||
* @rmtoll CR CSBF LL_PWR_ClearFlag_SB
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
|
||||
{
|
||||
SET_BIT(PWR->CR, PWR_CR_CSBF);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Wake-up Flags
|
||||
* @rmtoll CR CWUF LL_PWR_ClearFlag_WU
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
|
||||
{
|
||||
SET_BIT(PWR->CR, PWR_CR_CWUF);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup PWR_LL_EF_Init De-initialization function
|
||||
* @{
|
||||
*/
|
||||
ErrorStatus LL_PWR_DeInit(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined(PWR) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0xx_LL_PWR_H */
|
||||
2258
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h
Normal file
2258
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h
Normal file
File diff suppressed because it is too large
Load Diff
3109
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rtc.h
Normal file
3109
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rtc.h
Normal file
File diff suppressed because it is too large
Load Diff
2284
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_spi.h
Normal file
2284
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_spi.h
Normal file
File diff suppressed because it is too large
Load Diff
1851
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h
Normal file
1851
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h
Normal file
File diff suppressed because it is too large
Load Diff
4016
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_tim.h
Normal file
4016
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_tim.h
Normal file
File diff suppressed because it is too large
Load Diff
3849
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_usart.h
Normal file
3849
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_usart.h
Normal file
File diff suppressed because it is too large
Load Diff
243
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_usb.h
Normal file
243
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_usb.h
Normal file
@@ -0,0 +1,243 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_ll_usb.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of USB Low Layer HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F0xx_LL_USB_H
|
||||
#define STM32F0xx_LL_USB_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
#if defined (USB)
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USB_LL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief USB Mode definition
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
USB_DEVICE_MODE = 0
|
||||
} USB_ModeTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief USB Instance Initialization Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t dev_endpoints; /*!< Device Endpoints number.
|
||||
This parameter depends on the used USB core.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||
|
||||
uint8_t speed; /*!< USB Core speed.
|
||||
This parameter can be any value of @ref PCD_Speed/HCD_Speed
|
||||
(HCD_SPEED_xxx, HCD_SPEED_xxx) */
|
||||
|
||||
uint8_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
|
||||
|
||||
uint8_t phy_itface; /*!< Select the used PHY interface.
|
||||
This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */
|
||||
|
||||
uint8_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
|
||||
|
||||
uint8_t low_power_enable; /*!< Enable or disable the low Power Mode. */
|
||||
|
||||
uint8_t lpm_enable; /*!< Enable or disable Link Power Management. */
|
||||
|
||||
uint8_t battery_charging_enable; /*!< Enable or disable Battery charging. */
|
||||
} USB_CfgTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t num; /*!< Endpoint number
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||
|
||||
uint8_t is_in; /*!< Endpoint direction
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||
|
||||
uint8_t is_stall; /*!< Endpoint stall condition
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||
|
||||
uint8_t type; /*!< Endpoint type
|
||||
This parameter can be any value of @ref USB_LL_EP_Type */
|
||||
|
||||
uint8_t data_pid_start; /*!< Initial data PID
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||
|
||||
|
||||
uint16_t pmaadress; /*!< PMA Address
|
||||
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
|
||||
|
||||
uint16_t pmaaddr0; /*!< PMA Address0
|
||||
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
|
||||
|
||||
uint16_t pmaaddr1; /*!< PMA Address1
|
||||
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
|
||||
|
||||
uint8_t doublebuffer; /*!< Double buffer enable
|
||||
This parameter can be 0 or 1 */
|
||||
|
||||
|
||||
uint32_t maxpacket; /*!< Endpoint Max packet size
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
|
||||
|
||||
uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
|
||||
|
||||
uint32_t xfer_len; /*!< Current transfer length */
|
||||
|
||||
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
|
||||
|
||||
uint32_t xfer_len_db; /*!< double buffer transfer length used with bulk double buffer in */
|
||||
|
||||
uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */
|
||||
} USB_EPTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PCD_Exported_Constants PCD Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
|
||||
* @{
|
||||
*/
|
||||
#define EP_MPS_64 0U
|
||||
#define EP_MPS_32 1U
|
||||
#define EP_MPS_16 2U
|
||||
#define EP_MPS_8 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
|
||||
* @{
|
||||
*/
|
||||
#define EP_TYPE_CTRL 0U
|
||||
#define EP_TYPE_ISOC 1U
|
||||
#define EP_TYPE_BULK 2U
|
||||
#define EP_TYPE_INTR 3U
|
||||
#define EP_TYPE_MSK 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_LL Device Speed
|
||||
* @{
|
||||
*/
|
||||
#define USBD_FS_SPEED 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#define BTABLE_ADDRESS 0x000U
|
||||
#define PMA_ACCESS 1U
|
||||
|
||||
#ifndef USB_EP_RX_STRX
|
||||
#define USB_EP_RX_STRX (0x3U << 12)
|
||||
#endif /* USB_EP_RX_STRX */
|
||||
|
||||
#define EP_ADDR_MSK 0x7U
|
||||
|
||||
#ifndef USE_USB_DOUBLE_BUFFER
|
||||
#define USE_USB_DOUBLE_BUFFER 1U
|
||||
#endif /* USE_USB_DOUBLE_BUFFER */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg);
|
||||
HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg);
|
||||
HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode);
|
||||
|
||||
HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef const *USBx);
|
||||
HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef const *USBx, uint32_t num);
|
||||
|
||||
#if defined (HAL_PCD_MODULE_ENABLED)
|
||||
HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_EPStopXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep);
|
||||
#endif /* defined (HAL_PCD_MODULE_ENABLED) */
|
||||
|
||||
HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address);
|
||||
HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx);
|
||||
uint32_t USB_ReadInterrupts(USB_TypeDef const *USBx);
|
||||
HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx);
|
||||
|
||||
void USB_WritePMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf,
|
||||
uint16_t wPMABufAddr, uint16_t wNBytes);
|
||||
|
||||
void USB_ReadPMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf,
|
||||
uint16_t wPMABufAddr, uint16_t wNBytes);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* defined (USB) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
|
||||
#endif /* STM32F0xx_LL_USB_H */
|
||||
272
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h
Normal file
272
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h
Normal file
@@ -0,0 +1,272 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_ll_utils.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of UTILS LL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The LL UTILS driver contains a set of generic APIs that can be
|
||||
used by user:
|
||||
(+) Device electronic signature
|
||||
(+) Timing functions
|
||||
(+) PLL configuration functions
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0xx_LL_UTILS_H
|
||||
#define __STM32F0xx_LL_UTILS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_LL UTILS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Max delay can be used in LL_mDelay */
|
||||
#define LL_MAX_DELAY 0xFFFFFFFFU
|
||||
|
||||
/**
|
||||
* @brief Unique device ID register base address
|
||||
*/
|
||||
#define UID_BASE_ADDRESS UID_BASE
|
||||
|
||||
/**
|
||||
* @brief Flash size data register base address
|
||||
*/
|
||||
#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief UTILS PLL structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock.
|
||||
This parameter can be a value of @ref RCC_LL_EC_PLL_MUL
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
|
||||
|
||||
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
|
||||
uint32_t PLLDiv; /*!< Division factor for PLL VCO output clock.
|
||||
This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
|
||||
#else
|
||||
uint32_t Prediv; /*!< Division factor for HSE used as PLL clock source.
|
||||
This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
|
||||
#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
|
||||
} LL_UTILS_PLLInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief UTILS System, AHB and APB buses clock configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
|
||||
This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_SetAHBPrescaler(). */
|
||||
|
||||
uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
|
||||
This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_SetAPB1Prescaler(). */
|
||||
} LL_UTILS_ClkInitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
|
||||
* @{
|
||||
*/
|
||||
#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
|
||||
#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get Word0 of the unique device identifier (UID based on 96 bits)
|
||||
* @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
|
||||
{
|
||||
return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Word1 of the unique device identifier (UID based on 96 bits)
|
||||
* @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
|
||||
{
|
||||
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Word2 of the unique device identifier (UID based on 96 bits)
|
||||
* @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
|
||||
{
|
||||
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Flash memory size
|
||||
* @note This bitfield indicates the size of the device Flash memory expressed in
|
||||
* Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
|
||||
* @retval FLASH_SIZE[15:0]: Flash memory size
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GetFlashSize(void)
|
||||
{
|
||||
return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_LL_EF_DELAY DELAY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function configures the Cortex-M SysTick source of the time base.
|
||||
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
|
||||
* @note When a RTOS is used, it is recommended to avoid changing the SysTick
|
||||
* configuration by calling this function, for a delay use rather osDelay RTOS service.
|
||||
* @param Ticks Frequency of Ticks (Hz)
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
|
||||
{
|
||||
/* Configure the SysTick to have interrupt in 1ms time base */
|
||||
SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
|
||||
}
|
||||
|
||||
void LL_Init1msTick(uint32_t HCLKFrequency);
|
||||
void LL_mDelay(uint32_t Delay);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_EF_SYSTEM SYSTEM
|
||||
* @{
|
||||
*/
|
||||
|
||||
void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
|
||||
#if defined(FLASH_ACR_LATENCY)
|
||||
ErrorStatus LL_SetFlashLatency(uint32_t Frequency);
|
||||
#endif /* FLASH_ACR_LATENCY */
|
||||
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
|
||||
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
|
||||
#if defined(RCC_CFGR_SW_HSI48)
|
||||
ErrorStatus LL_PLL_ConfigSystemClock_HSI48(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
|
||||
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
|
||||
#endif /*RCC_CFGR_SW_HSI48*/
|
||||
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
|
||||
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0xx_LL_UTILS_H */
|
||||
316
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_wwdg.h
Normal file
316
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_wwdg.h
Normal file
@@ -0,0 +1,316 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_ll_wwdg.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of WWDG LL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F0xx_LL_WWDG_H
|
||||
#define STM32F0xx_LL_WWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (WWDG)
|
||||
|
||||
/** @defgroup WWDG_LL WWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_LL_EC_IT IT Defines
|
||||
* @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions
|
||||
* @{
|
||||
*/
|
||||
#define LL_WWDG_CFR_EWI WWDG_CFR_EWI
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
|
||||
* @{
|
||||
*/
|
||||
#define LL_WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
|
||||
#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
|
||||
#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
|
||||
#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Write a value in WWDG register
|
||||
* @param __INSTANCE__ WWDG Instance
|
||||
* @param __REG__ Register to be written
|
||||
* @param __VALUE__ Value to be written in the register
|
||||
* @retval None
|
||||
*/
|
||||
#define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Read a value in WWDG register
|
||||
* @param __INSTANCE__ WWDG Instance
|
||||
* @param __REG__ Register to be read
|
||||
* @retval Register value
|
||||
*/
|
||||
#define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_LL_EF_Configuration Configuration
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enable Window Watchdog. The watchdog is always disabled after a reset.
|
||||
* @note It is enabled by setting the WDGA bit in the WWDG_CR register,
|
||||
* then it cannot be disabled again except by a reset.
|
||||
* This bit is set by software and only cleared by hardware after a reset.
|
||||
* When WDGA = 1, the watchdog can generate a reset.
|
||||
* @rmtoll CR WDGA LL_WWDG_Enable
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks if Window Watchdog is enabled
|
||||
* @rmtoll CR WDGA LL_WWDG_IsEnabled
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(const WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Watchdog counter value to provided value (7-bits T[6:0])
|
||||
* @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
|
||||
* This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
|
||||
* A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
|
||||
* Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
|
||||
* @rmtoll CR T LL_WWDG_SetCounter
|
||||
* @param WWDGx WWDG Instance
|
||||
* @param Counter 0..0x7F (7 bit counter value)
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
|
||||
{
|
||||
MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return current Watchdog Counter Value (7 bits counter value)
|
||||
* @rmtoll CR T LL_WWDG_GetCounter
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval 7 bit Watchdog Counter value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_WWDG_GetCounter(const WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
return (READ_BIT(WWDGx->CR, WWDG_CR_T));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the time base of the prescaler (WDGTB).
|
||||
* @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
|
||||
* is decremented every (4096 x 2expWDGTB) PCLK cycles
|
||||
* @rmtoll CFR WDGTB LL_WWDG_SetPrescaler
|
||||
* @param WWDGx WWDG Instance
|
||||
* @param Prescaler This parameter can be one of the following values:
|
||||
* @arg @ref LL_WWDG_PRESCALER_1
|
||||
* @arg @ref LL_WWDG_PRESCALER_2
|
||||
* @arg @ref LL_WWDG_PRESCALER_4
|
||||
* @arg @ref LL_WWDG_PRESCALER_8
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
|
||||
{
|
||||
MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return current Watchdog Prescaler Value
|
||||
* @rmtoll CFR WDGTB LL_WWDG_GetPrescaler
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_WWDG_PRESCALER_1
|
||||
* @arg @ref LL_WWDG_PRESCALER_2
|
||||
* @arg @ref LL_WWDG_PRESCALER_4
|
||||
* @arg @ref LL_WWDG_PRESCALER_8
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(const WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
|
||||
* @note This window value defines when write in the WWDG_CR register
|
||||
* to program Watchdog counter is allowed.
|
||||
* Watchdog counter value update must occur only when the counter value
|
||||
* is lower than the Watchdog window register value.
|
||||
* Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
|
||||
* (in the control register) is refreshed before the downcounter has reached
|
||||
* the watchdog window register value.
|
||||
* Physically is possible to set the Window lower then 0x40 but it is not recommended.
|
||||
* To generate an immediate reset, it is possible to set the Counter lower than 0x40.
|
||||
* @rmtoll CFR W LL_WWDG_SetWindow
|
||||
* @param WWDGx WWDG Instance
|
||||
* @param Window 0x00..0x7F (7 bit Window value)
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
|
||||
{
|
||||
MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return current Watchdog Window Value (7 bits value)
|
||||
* @rmtoll CFR W LL_WWDG_GetWindow
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval 7 bit Watchdog Window value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_WWDG_GetWindow(const WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
return (READ_BIT(WWDGx->CFR, WWDG_CFR_W));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
|
||||
* @note This bit is set by hardware when the counter has reached the value 0x40.
|
||||
* It must be cleared by software by writing 0.
|
||||
* A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
|
||||
* @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(const WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF)
|
||||
* @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_LL_EF_IT_Management IT_Management
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enable the Early Wakeup Interrupt.
|
||||
* @note When set, an interrupt occurs whenever the counter reaches value 0x40.
|
||||
* This interrupt is only cleared by hardware after a reset
|
||||
* @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Early Wakeup Interrupt is enabled
|
||||
* @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(const WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* WWDG */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F0xx_LL_WWDG_H */
|
||||
6
Drivers/STM32F0xx_HAL_Driver/LICENSE.txt
Normal file
6
Drivers/STM32F0xx_HAL_Driver/LICENSE.txt
Normal file
@@ -0,0 +1,6 @@
|
||||
This software component is provided to you as part of a software package and
|
||||
applicable license terms are in the Package_license file. If you received this
|
||||
software component outside of a package or without applicable license terms,
|
||||
the terms of the BSD-3-Clause license shall apply.
|
||||
You may obtain a copy of the BSD-3-Clause at:
|
||||
https://opensource.org/licenses/BSD-3-Clause
|
||||
515
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c
Normal file
515
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c
Normal file
@@ -0,0 +1,515 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal.c
|
||||
* @author MCD Application Team
|
||||
* @brief HAL module driver.
|
||||
* This is the common part of the HAL initialization
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The common HAL driver contains a set of generic and common APIs that can be
|
||||
used by the PPP peripheral drivers and the user to start using the HAL.
|
||||
[..]
|
||||
The HAL contains two APIs categories:
|
||||
(+) HAL Initialization and de-initialization functions
|
||||
(+) HAL Control functions
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL HAL
|
||||
* @brief HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @defgroup HAL_Private_Constants HAL Private Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief STM32F0xx HAL Driver version number
|
||||
*/
|
||||
#define __STM32F0xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
|
||||
#define __STM32F0xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */
|
||||
#define __STM32F0xx_HAL_VERSION_SUB2 (0x08U) /*!< [15:8] sub2 version */
|
||||
#define __STM32F0xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
|
||||
#define __STM32F0xx_HAL_VERSION ((__STM32F0xx_HAL_VERSION_MAIN << 24U)\
|
||||
|(__STM32F0xx_HAL_VERSION_SUB1 << 16U)\
|
||||
|(__STM32F0xx_HAL_VERSION_SUB2 << 8U )\
|
||||
|(__STM32F0xx_HAL_VERSION_RC))
|
||||
|
||||
#define IDCODE_DEVID_MASK (0x00000FFFU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/** @defgroup HAL_Private_Macros HAL Private Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported variables ---------------------------------------------------------*/
|
||||
/** @defgroup HAL_Private_Variables HAL Exported Variables
|
||||
* @{
|
||||
*/
|
||||
__IO uint32_t uwTick;
|
||||
uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
|
||||
HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup HAL_Exported_Functions HAL Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
|
||||
* @brief Initialization and de-initialization functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Initializes the Flash interface, the NVIC allocation and initial clock
|
||||
configuration. It initializes the systick also when timeout is needed
|
||||
and the backup domain when enabled.
|
||||
(+) de-Initializes common part of the HAL.
|
||||
(+) Configure The time base source to have 1ms time base with a dedicated
|
||||
Tick interrupt priority.
|
||||
(++) SysTick timer is used by default as source of time base, but user
|
||||
can eventually implement his proper time base source (a general purpose
|
||||
timer for example or other time source), keeping in mind that Time base
|
||||
duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
|
||||
handled in milliseconds basis.
|
||||
(++) Time base configuration function (HAL_InitTick ()) is called automatically
|
||||
at the beginning of the program after reset by HAL_Init() or at any time
|
||||
when clock is configured, by HAL_RCC_ClockConfig().
|
||||
(++) Source of time base is configured to generate interrupts at regular
|
||||
time intervals. Care must be taken if HAL_Delay() is called from a
|
||||
peripheral ISR process, the Tick interrupt line must have higher priority
|
||||
(numerically lower) than the peripheral interrupt. Otherwise the caller
|
||||
ISR process will be blocked.
|
||||
(++) functions affecting time base configurations are declared as __Weak
|
||||
to make override possible in case of other implementations in user file.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function configures the Flash prefetch,
|
||||
* Configures time base source, NVIC and Low level hardware
|
||||
* @note This function is called at the beginning of program after reset and before
|
||||
* the clock configuration
|
||||
* @note The time base configuration is based on HSI clock when exiting from Reset.
|
||||
* Once done, time base tick start incrementing.
|
||||
* In the default implementation,Systick is used as source of time base.
|
||||
* The tick variable is incremented each 1ms in its ISR.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_Init(void)
|
||||
{
|
||||
/* Configure Flash prefetch */
|
||||
#if (PREFETCH_ENABLE != 0)
|
||||
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
||||
#endif /* PREFETCH_ENABLE */
|
||||
|
||||
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
|
||||
|
||||
HAL_InitTick(TICK_INT_PRIORITY);
|
||||
|
||||
/* Init the low level hardware */
|
||||
HAL_MspInit();
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function de-Initialize common part of the HAL and stops the SysTick
|
||||
* of time base.
|
||||
* @note This function is optional.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DeInit(void)
|
||||
{
|
||||
/* Reset of all peripherals */
|
||||
__HAL_RCC_APB1_FORCE_RESET();
|
||||
__HAL_RCC_APB1_RELEASE_RESET();
|
||||
|
||||
__HAL_RCC_APB2_FORCE_RESET();
|
||||
__HAL_RCC_APB2_RELEASE_RESET();
|
||||
|
||||
__HAL_RCC_AHB_FORCE_RESET();
|
||||
__HAL_RCC_AHB_RELEASE_RESET();
|
||||
|
||||
/* De-Init the low level hardware */
|
||||
HAL_MspDeInit();
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the MSP.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_MspInit(void)
|
||||
{
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_MspInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the MSP.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_MspDeInit(void)
|
||||
{
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_MspDeInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function configures the source of the time base.
|
||||
* The time source is configured to have 1ms time base with a dedicated
|
||||
* Tick interrupt priority.
|
||||
* @note This function is called automatically at the beginning of program after
|
||||
* reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
|
||||
* @note In the default implementation, SysTick timer is the source of time base.
|
||||
* It is used to generate interrupts at regular time intervals.
|
||||
* Care must be taken if HAL_Delay() is called from a peripheral ISR process,
|
||||
* The SysTick interrupt must have higher priority (numerically lower)
|
||||
* than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
|
||||
* The function is declared as __Weak to be overwritten in case of other
|
||||
* implementation in user file.
|
||||
* @param TickPriority Tick interrupt priority.
|
||||
* @retval HAL status
|
||||
*/
|
||||
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
||||
{
|
||||
/*Configure the SysTick to have interrupt in 1ms time basis*/
|
||||
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Configure the SysTick IRQ priority */
|
||||
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
||||
{
|
||||
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
||||
uwTickPrio = TickPriority;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
|
||||
* @brief HAL Control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### HAL Control functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Provide a tick value in millisecond
|
||||
(+) Provide a blocking delay in millisecond
|
||||
(+) Suspend the time base source interrupt
|
||||
(+) Resume the time base source interrupt
|
||||
(+) Get the HAL API driver version
|
||||
(+) Get the device identifier
|
||||
(+) Get the device revision identifier
|
||||
(+) Enable/Disable Debug module during Sleep mode
|
||||
(+) Enable/Disable Debug module during STOP mode
|
||||
(+) Enable/Disable Debug module during STANDBY mode
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function is called to increment a global variable "uwTick"
|
||||
* used as application time base.
|
||||
* @note In the default implementation, this variable is incremented each 1ms
|
||||
* in SysTick ISR.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_IncTick(void)
|
||||
{
|
||||
uwTick += uwTickFreq;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Provides a tick value in millisecond.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @retval tick value
|
||||
*/
|
||||
__weak uint32_t HAL_GetTick(void)
|
||||
{
|
||||
return uwTick;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function returns a tick priority.
|
||||
* @retval tick priority
|
||||
*/
|
||||
uint32_t HAL_GetTickPrio(void)
|
||||
{
|
||||
return uwTickPrio;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set new tick Freq.
|
||||
* @retval status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
HAL_TickFreqTypeDef prevTickFreq;
|
||||
|
||||
assert_param(IS_TICKFREQ(Freq));
|
||||
|
||||
if (uwTickFreq != Freq)
|
||||
{
|
||||
/* Back up uwTickFreq frequency */
|
||||
prevTickFreq = uwTickFreq;
|
||||
|
||||
/* Update uwTickFreq global variable used by HAL_InitTick() */
|
||||
uwTickFreq = Freq;
|
||||
|
||||
/* Apply the new tick Freq */
|
||||
status = HAL_InitTick(uwTickPrio);
|
||||
|
||||
if (status != HAL_OK)
|
||||
{
|
||||
/* Restore previous tick frequency */
|
||||
uwTickFreq = prevTickFreq;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief return tick frequency.
|
||||
* @retval Tick frequency.
|
||||
* Value of @ref HAL_TickFreqTypeDef.
|
||||
*/
|
||||
HAL_TickFreqTypeDef HAL_GetTickFreq(void)
|
||||
{
|
||||
return uwTickFreq;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function provides accurate delay (in milliseconds) based
|
||||
* on variable incremented.
|
||||
* @note In the default implementation , SysTick timer is the source of time base.
|
||||
* It is used to generate interrupts at regular time intervals where uwTick
|
||||
* is incremented.
|
||||
* @note ThiS function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @param Delay specifies the delay time length, in milliseconds.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_Delay(uint32_t Delay)
|
||||
{
|
||||
uint32_t tickstart = HAL_GetTick();
|
||||
uint32_t wait = Delay;
|
||||
|
||||
/* Add a freq to guarantee minimum wait */
|
||||
if (wait < HAL_MAX_DELAY)
|
||||
{
|
||||
wait += (uint32_t)(uwTickFreq);
|
||||
}
|
||||
|
||||
while((HAL_GetTick() - tickstart) < wait)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Suspend Tick increment.
|
||||
* @note In the default implementation , SysTick timer is the source of time base. It is
|
||||
* used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
|
||||
* is called, the the SysTick interrupt will be disabled and so Tick increment
|
||||
* is suspended.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_SuspendTick(void)
|
||||
|
||||
{
|
||||
/* Disable SysTick Interrupt */
|
||||
CLEAR_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resume Tick increment.
|
||||
* @note In the default implementation , SysTick timer is the source of time base. It is
|
||||
* used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
|
||||
* is called, the the SysTick interrupt will be enabled and so Tick increment
|
||||
* is resumed.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_ResumeTick(void)
|
||||
{
|
||||
/* Enable SysTick Interrupt */
|
||||
SET_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This method returns the HAL revision
|
||||
* @retval version 0xXYZR (8bits for each decimal, R for RC)
|
||||
*/
|
||||
uint32_t HAL_GetHalVersion(void)
|
||||
{
|
||||
return __STM32F0xx_HAL_VERSION;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the device revision identifier.
|
||||
* @retval Device revision identifier
|
||||
*/
|
||||
uint32_t HAL_GetREVID(void)
|
||||
{
|
||||
return((DBGMCU->IDCODE) >> 16U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the device identifier.
|
||||
* @retval Device identifier
|
||||
*/
|
||||
uint32_t HAL_GetDEVID(void)
|
||||
{
|
||||
return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns first word of the unique device identifier (UID based on 96 bits)
|
||||
* @retval Device identifier
|
||||
*/
|
||||
uint32_t HAL_GetUIDw0(void)
|
||||
{
|
||||
return(READ_REG(*((uint32_t *)UID_BASE)));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns second word of the unique device identifier (UID based on 96 bits)
|
||||
* @retval Device identifier
|
||||
*/
|
||||
uint32_t HAL_GetUIDw1(void)
|
||||
{
|
||||
return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns third word of the unique device identifier (UID based on 96 bits)
|
||||
* @retval Device identifier
|
||||
*/
|
||||
uint32_t HAL_GetUIDw2(void)
|
||||
{
|
||||
return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the Debug Module during STOP mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_EnableDBGStopMode(void)
|
||||
{
|
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Debug Module during STOP mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_DisableDBGStopMode(void)
|
||||
{
|
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the Debug Module during STANDBY mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_EnableDBGStandbyMode(void)
|
||||
{
|
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Debug Module during STANDBY mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_DisableDBGStandbyMode(void)
|
||||
{
|
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
2490
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c
Normal file
2490
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c
Normal file
File diff suppressed because it is too large
Load Diff
189
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.c
Normal file
189
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.c
Normal file
@@ -0,0 +1,189 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_adc_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Analog to Digital Convertor (ADC)
|
||||
* peripheral:
|
||||
* + Peripheral Control functions
|
||||
* Other functions (generic functions) are available in file
|
||||
* "stm32f0xx_hal_adc.c".
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
[..]
|
||||
(@) Sections "ADC peripheral features" and "How to use this driver" are
|
||||
available in file of generic functions "stm32l1xx_hal_adc.c".
|
||||
[..]
|
||||
@endverbatim
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ADCEx ADCEx
|
||||
* @brief ADC HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_ADC_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @defgroup ADCEx_Private_Constants ADCEx Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Fixed timeout values for ADC calibration, enable settling time, disable */
|
||||
/* settling time. */
|
||||
/* Values defined to be higher than worst cases: low clock frequency, */
|
||||
/* maximum prescaler. */
|
||||
/* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
|
||||
/* prescaler 4. */
|
||||
/* Unit: ms */
|
||||
#define ADC_DISABLE_TIMEOUT 2
|
||||
#define ADC_CALIBRATION_TIMEOUT 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ADCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions
|
||||
* @brief Extended Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Perform the ADC calibration.
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Perform an ADC automatic self-calibration
|
||||
* Calibration prerequisite: ADC must be disabled (execute this
|
||||
* function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
|
||||
* @note Calibration factor can be read after calibration, using function
|
||||
* HAL_ADC_GetValue() (value on 7 bits: from DR[6;0]).
|
||||
* @param hadc ADC handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
|
||||
{
|
||||
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
|
||||
uint32_t tickstart = 0U;
|
||||
uint32_t backup_setting_adc_dma_transfer = 0; /* Note: Variable not declared as volatile because register read is already declared as volatile */
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hadc);
|
||||
|
||||
/* Calibration prerequisite: ADC must be disabled. */
|
||||
if (ADC_IS_ENABLE(hadc) == RESET)
|
||||
{
|
||||
/* Set ADC state */
|
||||
ADC_STATE_CLR_SET(hadc->State,
|
||||
HAL_ADC_STATE_REG_BUSY,
|
||||
HAL_ADC_STATE_BUSY_INTERNAL);
|
||||
|
||||
/* Disable ADC DMA transfer request during calibration */
|
||||
/* Note: Specificity of this STM32 series: Calibration factor is */
|
||||
/* available in data register and also transferred by DMA. */
|
||||
/* To not insert ADC calibration factor among ADC conversion data */
|
||||
/* in array variable, DMA transfer must be disabled during */
|
||||
/* calibration. */
|
||||
backup_setting_adc_dma_transfer = READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG);
|
||||
CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG);
|
||||
|
||||
/* Start ADC calibration */
|
||||
hadc->Instance->CR |= ADC_CR_ADCAL;
|
||||
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait for calibration completion */
|
||||
while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL))
|
||||
{
|
||||
if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
|
||||
{
|
||||
/* New check to avoid false timeout detection in case of preemption */
|
||||
if(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL))
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
ADC_STATE_CLR_SET(hadc->State,
|
||||
HAL_ADC_STATE_BUSY_INTERNAL,
|
||||
HAL_ADC_STATE_ERROR_INTERNAL);
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hadc);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Restore ADC DMA transfer request after calibration */
|
||||
SET_BIT(hadc->Instance->CFGR1, backup_setting_adc_dma_transfer);
|
||||
|
||||
/* Set ADC state */
|
||||
ADC_STATE_CLR_SET(hadc->State,
|
||||
HAL_ADC_STATE_BUSY_INTERNAL,
|
||||
HAL_ADC_STATE_READY);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
||||
|
||||
tmp_hal_status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hadc);
|
||||
|
||||
/* Return function status */
|
||||
return tmp_hal_status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_ADC_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
2432
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c
Normal file
2432
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c
Normal file
File diff suppressed because it is too large
Load Diff
997
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cec.c
Normal file
997
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cec.c
Normal file
@@ -0,0 +1,997 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_cec.c
|
||||
* @author MCD Application Team
|
||||
* @brief CEC HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the High Definition Multimedia Interface
|
||||
* Consumer Electronics Control Peripheral (CEC).
|
||||
* + Initialization and de-initialization function
|
||||
* + IO operation function
|
||||
* + Peripheral Control function
|
||||
*
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### How to use this driver #####
|
||||
===============================================================================
|
||||
[..]
|
||||
The CEC HAL driver can be used as follow:
|
||||
|
||||
(#) Declare a CEC_HandleTypeDef handle structure.
|
||||
(#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
|
||||
(##) Enable the CEC interface clock.
|
||||
(##) CEC pins configuration:
|
||||
(+++) Enable the clock for the CEC GPIOs.
|
||||
(+++) Configure these CEC pins as alternate function pull-up.
|
||||
(##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
|
||||
and HAL_CEC_Receive_IT() APIs):
|
||||
(+++) Configure the CEC interrupt priority.
|
||||
(+++) Enable the NVIC CEC IRQ handle.
|
||||
(+++) The specific CEC interrupts (Transmission complete interrupt,
|
||||
RXNE interrupt and Error Interrupts) will be managed using the macros
|
||||
__HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
|
||||
and receive process.
|
||||
|
||||
(#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in
|
||||
in case of Bit Rising Error, Error-Bit generation conditions, device logical
|
||||
address and Listen mode in the hcec Init structure.
|
||||
|
||||
(#) Initialize the CEC registers by calling the HAL_CEC_Init() API.
|
||||
|
||||
[..]
|
||||
(@) This API (HAL_CEC_Init()) configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
|
||||
by calling the customed HAL_CEC_MspInit() API.
|
||||
*** Callback registration ***
|
||||
=============================================
|
||||
|
||||
The compilation define USE_HAL_CEC_REGISTER_CALLBACKS when set to 1
|
||||
allows the user to configure dynamically the driver callbacks.
|
||||
Use Functions HAL_CEC_RegisterCallback() or HAL_CEC_RegisterXXXCallback()
|
||||
to register an interrupt callback.
|
||||
|
||||
Function HAL_CEC_RegisterCallback() allows to register following callbacks:
|
||||
(+) TxCpltCallback : Tx Transfer completed callback.
|
||||
(+) ErrorCallback : callback for error detection.
|
||||
(+) MspInitCallback : CEC MspInit.
|
||||
(+) MspDeInitCallback : CEC MspDeInit.
|
||||
This function takes as parameters the HAL peripheral handle, the Callback ID
|
||||
and a pointer to the user callback function.
|
||||
|
||||
For specific callback HAL_CEC_RxCpltCallback use dedicated register callbacks
|
||||
HAL_CEC_RegisterRxCpltCallback().
|
||||
|
||||
Use function HAL_CEC_UnRegisterCallback() to reset a callback to the default
|
||||
weak function.
|
||||
HAL_CEC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
|
||||
and the Callback ID.
|
||||
This function allows to reset following callbacks:
|
||||
(+) TxCpltCallback : Tx Transfer completed callback.
|
||||
(+) ErrorCallback : callback for error detection.
|
||||
(+) MspInitCallback : CEC MspInit.
|
||||
(+) MspDeInitCallback : CEC MspDeInit.
|
||||
|
||||
For callback HAL_CEC_RxCpltCallback use dedicated unregister callback :
|
||||
HAL_CEC_UnRegisterRxCpltCallback().
|
||||
|
||||
By default, after the HAL_CEC_Init() and when the state is HAL_CEC_STATE_RESET
|
||||
all callbacks are set to the corresponding weak functions :
|
||||
examples HAL_CEC_TxCpltCallback() , HAL_CEC_RxCpltCallback().
|
||||
Exception done for MspInit and MspDeInit functions that are
|
||||
reset to the legacy weak function in the HAL_CEC_Init()/ HAL_CEC_DeInit() only when
|
||||
these callbacks are null (not registered beforehand).
|
||||
if not, MspInit or MspDeInit are not null, the HAL_CEC_Init() / HAL_CEC_DeInit()
|
||||
keep and use the user MspInit/MspDeInit functions (registered beforehand)
|
||||
|
||||
Callbacks can be registered/unregistered in HAL_CEC_STATE_READY state only.
|
||||
Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
|
||||
in HAL_CEC_STATE_READY or HAL_CEC_STATE_RESET state,
|
||||
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
|
||||
In that case first register the MspInit/MspDeInit user callbacks
|
||||
using HAL_CEC_RegisterCallback() before calling HAL_CEC_DeInit()
|
||||
or HAL_CEC_Init() function.
|
||||
|
||||
When the compilation define USE_HAL_CEC_REGISTER_CALLBACKS is set to 0 or
|
||||
not defined, the callback registration feature is not available and all callbacks
|
||||
are set to the corresponding weak functions.
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CEC CEC
|
||||
* @brief HAL CEC module driver
|
||||
* @{
|
||||
*/
|
||||
#ifdef HAL_CEC_MODULE_ENABLED
|
||||
#if defined (CEC)
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @defgroup CEC_Private_Constants CEC Private Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup CEC_Private_Functions CEC Private Functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CEC_Exported_Functions CEC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Configuration functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to initialize the CEC
|
||||
(+) The following parameters need to be configured:
|
||||
(++) SignalFreeTime
|
||||
(++) Tolerance
|
||||
(++) BRERxStop (RX stopped or not upon Bit Rising Error)
|
||||
(++) BREErrorBitGen (Error-Bit generation in case of Bit Rising Error)
|
||||
(++) LBPEErrorBitGen (Error-Bit generation in case of Long Bit Period Error)
|
||||
(++) BroadcastMsgNoErrorBitGen (Error-bit generation in case of broadcast message error)
|
||||
(++) SignalFreeTimeOption (SFT Timer start definition)
|
||||
(++) OwnAddress (CEC device address)
|
||||
(++) ListenMode
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the CEC mode according to the specified
|
||||
* parameters in the CEC_InitTypeDef and creates the associated handle .
|
||||
* @param hcec CEC handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
|
||||
{
|
||||
/* Check the CEC handle allocation */
|
||||
if ((hcec == NULL) || (hcec->Init.RxBuffer == NULL))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
|
||||
assert_param(IS_CEC_SIGNALFREETIME(hcec->Init.SignalFreeTime));
|
||||
assert_param(IS_CEC_TOLERANCE(hcec->Init.Tolerance));
|
||||
assert_param(IS_CEC_BRERXSTOP(hcec->Init.BRERxStop));
|
||||
assert_param(IS_CEC_BREERRORBITGEN(hcec->Init.BREErrorBitGen));
|
||||
assert_param(IS_CEC_LBPEERRORBITGEN(hcec->Init.LBPEErrorBitGen));
|
||||
assert_param(IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(hcec->Init.BroadcastMsgNoErrorBitGen));
|
||||
assert_param(IS_CEC_SFTOP(hcec->Init.SignalFreeTimeOption));
|
||||
assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode));
|
||||
assert_param(IS_CEC_OWN_ADDRESS(hcec->Init.OwnAddress));
|
||||
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
if (hcec->gState == HAL_CEC_STATE_RESET)
|
||||
{
|
||||
/* Allocate lock resource and initialize it */
|
||||
hcec->Lock = HAL_UNLOCKED;
|
||||
|
||||
hcec->TxCpltCallback = HAL_CEC_TxCpltCallback; /* Legacy weak TxCpltCallback */
|
||||
hcec->RxCpltCallback = HAL_CEC_RxCpltCallback; /* Legacy weak RxCpltCallback */
|
||||
hcec->ErrorCallback = HAL_CEC_ErrorCallback; /* Legacy weak ErrorCallback */
|
||||
|
||||
if (hcec->MspInitCallback == NULL)
|
||||
{
|
||||
hcec->MspInitCallback = HAL_CEC_MspInit; /* Legacy weak MspInit */
|
||||
}
|
||||
|
||||
/* Init the low level hardware */
|
||||
hcec->MspInitCallback(hcec);
|
||||
}
|
||||
#else
|
||||
if (hcec->gState == HAL_CEC_STATE_RESET)
|
||||
{
|
||||
/* Allocate lock resource and initialize it */
|
||||
hcec->Lock = HAL_UNLOCKED;
|
||||
/* Init the low level hardware : GPIO, CLOCK */
|
||||
HAL_CEC_MspInit(hcec);
|
||||
}
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
|
||||
hcec->gState = HAL_CEC_STATE_BUSY;
|
||||
|
||||
/* Disable the Peripheral */
|
||||
__HAL_CEC_DISABLE(hcec);
|
||||
|
||||
/* Write to CEC Control Register */
|
||||
hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop | \
|
||||
hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | \
|
||||
hcec->Init.BroadcastMsgNoErrorBitGen | \
|
||||
hcec->Init.SignalFreeTimeOption | ((uint32_t)(hcec->Init.OwnAddress) << 16U) | \
|
||||
hcec->Init.ListenMode;
|
||||
|
||||
/* Enable the following CEC Transmission/Reception interrupts as
|
||||
* well as the following CEC Transmission/Reception Errors interrupts
|
||||
* Rx Byte Received IT
|
||||
* End of Reception IT
|
||||
* Rx overrun
|
||||
* Rx bit rising error
|
||||
* Rx short bit period error
|
||||
* Rx long bit period error
|
||||
* Rx missing acknowledge
|
||||
* Tx Byte Request IT
|
||||
* End of Transmission IT
|
||||
* Tx Missing Acknowledge IT
|
||||
* Tx-Error IT
|
||||
* Tx-Buffer Underrun IT
|
||||
* Tx arbitration lost */
|
||||
__HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR | CEC_IT_RXEND | CEC_IER_RX_ALL_ERR | CEC_IT_TXBR | CEC_IT_TXEND |
|
||||
CEC_IER_TX_ALL_ERR);
|
||||
|
||||
/* Enable the CEC Peripheral */
|
||||
__HAL_CEC_ENABLE(hcec);
|
||||
|
||||
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
|
||||
hcec->gState = HAL_CEC_STATE_READY;
|
||||
hcec->RxState = HAL_CEC_STATE_READY;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the CEC peripheral
|
||||
* @param hcec CEC handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
|
||||
{
|
||||
/* Check the CEC handle allocation */
|
||||
if (hcec == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
|
||||
|
||||
hcec->gState = HAL_CEC_STATE_BUSY;
|
||||
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
if (hcec->MspDeInitCallback == NULL)
|
||||
{
|
||||
hcec->MspDeInitCallback = HAL_CEC_MspDeInit; /* Legacy weak MspDeInit */
|
||||
}
|
||||
|
||||
/* DeInit the low level hardware */
|
||||
hcec->MspDeInitCallback(hcec);
|
||||
|
||||
#else
|
||||
/* DeInit the low level hardware */
|
||||
HAL_CEC_MspDeInit(hcec);
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
|
||||
/* Disable the Peripheral */
|
||||
__HAL_CEC_DISABLE(hcec);
|
||||
|
||||
/* Clear Flags */
|
||||
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND | CEC_FLAG_TXBR | CEC_FLAG_RXBR | CEC_FLAG_RXEND | CEC_ISR_ALL_ERROR);
|
||||
|
||||
/* Disable the following CEC Transmission/Reception interrupts as
|
||||
* well as the following CEC Transmission/Reception Errors interrupts
|
||||
* Rx Byte Received IT
|
||||
* End of Reception IT
|
||||
* Rx overrun
|
||||
* Rx bit rising error
|
||||
* Rx short bit period error
|
||||
* Rx long bit period error
|
||||
* Rx missing acknowledge
|
||||
* Tx Byte Request IT
|
||||
* End of Transmission IT
|
||||
* Tx Missing Acknowledge IT
|
||||
* Tx-Error IT
|
||||
* Tx-Buffer Underrun IT
|
||||
* Tx arbitration lost */
|
||||
__HAL_CEC_DISABLE_IT(hcec, CEC_IT_RXBR | CEC_IT_RXEND | CEC_IER_RX_ALL_ERR | CEC_IT_TXBR | CEC_IT_TXEND |
|
||||
CEC_IER_TX_ALL_ERR);
|
||||
|
||||
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
|
||||
hcec->gState = HAL_CEC_STATE_RESET;
|
||||
hcec->RxState = HAL_CEC_STATE_RESET;
|
||||
|
||||
/* Process Unlock */
|
||||
__HAL_UNLOCK(hcec);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the Own Address of the CEC device
|
||||
* @param hcec CEC handle
|
||||
* @param CEC_OwnAddress The CEC own address.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CEC_OWN_ADDRESS(CEC_OwnAddress));
|
||||
|
||||
if ((hcec->gState == HAL_CEC_STATE_READY) && (hcec->RxState == HAL_CEC_STATE_READY))
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hcec);
|
||||
|
||||
hcec->gState = HAL_CEC_STATE_BUSY;
|
||||
|
||||
/* Disable the Peripheral */
|
||||
__HAL_CEC_DISABLE(hcec);
|
||||
|
||||
if (CEC_OwnAddress != CEC_OWN_ADDRESS_NONE)
|
||||
{
|
||||
hcec->Instance->CFGR |= ((uint32_t)CEC_OwnAddress << 16);
|
||||
}
|
||||
else
|
||||
{
|
||||
hcec->Instance->CFGR &= ~(CEC_CFGR_OAR);
|
||||
}
|
||||
|
||||
hcec->gState = HAL_CEC_STATE_READY;
|
||||
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hcec);
|
||||
|
||||
/* Enable the Peripheral */
|
||||
__HAL_CEC_ENABLE(hcec);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief CEC MSP Init
|
||||
* @param hcec CEC handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcec);
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_CEC_MspInit can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief CEC MSP DeInit
|
||||
* @param hcec CEC handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcec);
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_CEC_MspDeInit can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief Register a User CEC Callback
|
||||
* To be used instead of the weak predefined callback
|
||||
* @param hcec CEC handle
|
||||
* @param CallbackID ID of the callback to be registered
|
||||
* This parameter can be one of the following values:
|
||||
* @arg HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
|
||||
* @arg HAL_CEC_ERROR_CB_ID Error callback ID
|
||||
* @arg HAL_CEC_MSPINIT_CB_ID MspInit callback ID
|
||||
* @arg HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
|
||||
* @param pCallback pointer to the Callback function
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID,
|
||||
pCEC_CallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
if (pCallback == NULL)
|
||||
{
|
||||
/* Update the error code */
|
||||
hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hcec);
|
||||
|
||||
if (hcec->gState == HAL_CEC_STATE_READY)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_CEC_TX_CPLT_CB_ID :
|
||||
hcec->TxCpltCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_CEC_ERROR_CB_ID :
|
||||
hcec->ErrorCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_CEC_MSPINIT_CB_ID :
|
||||
hcec->MspInitCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_CEC_MSPDEINIT_CB_ID :
|
||||
hcec->MspDeInitCallback = pCallback;
|
||||
break;
|
||||
|
||||
default :
|
||||
/* Update the error code */
|
||||
hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else if (hcec->gState == HAL_CEC_STATE_RESET)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_CEC_MSPINIT_CB_ID :
|
||||
hcec->MspInitCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_CEC_MSPDEINIT_CB_ID :
|
||||
hcec->MspDeInitCallback = pCallback;
|
||||
break;
|
||||
|
||||
default :
|
||||
/* Update the error code */
|
||||
hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update the error code */
|
||||
hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hcec);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unregister an CEC Callback
|
||||
* CEC callback is redirected to the weak predefined callback
|
||||
* @param hcec uart handle
|
||||
* @param CallbackID ID of the callback to be unregistered
|
||||
* This parameter can be one of the following values:
|
||||
* @arg HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
|
||||
* @arg HAL_CEC_ERROR_CB_ID Error callback ID
|
||||
* @arg HAL_CEC_MSPINIT_CB_ID MspInit callback ID
|
||||
* @arg HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
|
||||
* @retval status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hcec);
|
||||
|
||||
if (hcec->gState == HAL_CEC_STATE_READY)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_CEC_TX_CPLT_CB_ID :
|
||||
hcec->TxCpltCallback = HAL_CEC_TxCpltCallback; /* Legacy weak TxCpltCallback */
|
||||
break;
|
||||
|
||||
case HAL_CEC_ERROR_CB_ID :
|
||||
hcec->ErrorCallback = HAL_CEC_ErrorCallback; /* Legacy weak ErrorCallback */
|
||||
break;
|
||||
|
||||
case HAL_CEC_MSPINIT_CB_ID :
|
||||
hcec->MspInitCallback = HAL_CEC_MspInit;
|
||||
break;
|
||||
|
||||
case HAL_CEC_MSPDEINIT_CB_ID :
|
||||
hcec->MspDeInitCallback = HAL_CEC_MspDeInit;
|
||||
break;
|
||||
|
||||
default :
|
||||
/* Update the error code */
|
||||
hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else if (hcec->gState == HAL_CEC_STATE_RESET)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_CEC_MSPINIT_CB_ID :
|
||||
hcec->MspInitCallback = HAL_CEC_MspInit;
|
||||
break;
|
||||
|
||||
case HAL_CEC_MSPDEINIT_CB_ID :
|
||||
hcec->MspDeInitCallback = HAL_CEC_MspDeInit;
|
||||
break;
|
||||
|
||||
default :
|
||||
/* Update the error code */
|
||||
hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update the error code */
|
||||
hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hcec);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Register CEC RX complete Callback
|
||||
* To be used instead of the weak HAL_CEC_RxCpltCallback() predefined callback
|
||||
* @param hcec CEC handle
|
||||
* @param pCallback pointer to the Rx transfer compelete Callback function
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback(CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
if (pCallback == NULL)
|
||||
{
|
||||
/* Update the error code */
|
||||
hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hcec);
|
||||
|
||||
if (HAL_CEC_STATE_READY == hcec->RxState)
|
||||
{
|
||||
hcec->RxCpltCallback = pCallback;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update the error code */
|
||||
hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hcec);
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief UnRegister CEC RX complete Callback
|
||||
* CEC RX complete Callback is redirected to the weak HAL_CEC_RxCpltCallback() predefined callback
|
||||
* @param hcec CEC handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hcec);
|
||||
|
||||
if (HAL_CEC_STATE_READY == hcec->RxState)
|
||||
{
|
||||
hcec->RxCpltCallback = HAL_CEC_RxCpltCallback; /* Legacy weak CEC RxCpltCallback */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update the error code */
|
||||
hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hcec);
|
||||
return status;
|
||||
}
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @brief CEC Transmit/Receive functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
This subsection provides a set of functions allowing to manage the CEC data transfers.
|
||||
|
||||
(#) The CEC handle must contain the initiator (TX side) and the destination (RX side)
|
||||
logical addresses (4-bit long addresses, 0xF for broadcast messages destination)
|
||||
|
||||
(#) The communication is performed using Interrupts.
|
||||
These API's return the HAL status.
|
||||
The end of the data processing will be indicated through the
|
||||
dedicated CEC IRQ when using Interrupt mode.
|
||||
The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks
|
||||
will be executed respectively at the end of the transmit or Receive process
|
||||
The HAL_CEC_ErrorCallback() user callback will be executed when a communication
|
||||
error is detected
|
||||
|
||||
(#) API's with Interrupt are :
|
||||
(+) HAL_CEC_Transmit_IT()
|
||||
(+) HAL_CEC_IRQHandler()
|
||||
|
||||
(#) A set of User Callbacks are provided:
|
||||
(+) HAL_CEC_TxCpltCallback()
|
||||
(+) HAL_CEC_RxCpltCallback()
|
||||
(+) HAL_CEC_ErrorCallback()
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Send data in interrupt mode
|
||||
* @param hcec CEC handle
|
||||
* @param InitiatorAddress Initiator address
|
||||
* @param DestinationAddress destination logical address
|
||||
* @param pData pointer to input byte data buffer
|
||||
* @param Size amount of data to be sent in bytes (without counting the header).
|
||||
* 0 means only the header is sent (ping operation).
|
||||
* Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress,
|
||||
const uint8_t *pData, uint32_t Size)
|
||||
{
|
||||
/* if the peripheral isn't already busy and if there is no previous transmission
|
||||
already pending due to arbitration lost */
|
||||
if (hcec->gState == HAL_CEC_STATE_READY)
|
||||
{
|
||||
if ((pData == NULL) && (Size > 0U))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
assert_param(IS_CEC_ADDRESS(DestinationAddress));
|
||||
assert_param(IS_CEC_ADDRESS(InitiatorAddress));
|
||||
assert_param(IS_CEC_MSGSIZE(Size));
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hcec);
|
||||
hcec->pTxBuffPtr = pData;
|
||||
hcec->gState = HAL_CEC_STATE_BUSY_TX;
|
||||
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
|
||||
|
||||
/* initialize the number of bytes to send,
|
||||
* 0 means only one header is sent (ping operation) */
|
||||
hcec->TxXferCount = (uint16_t)Size;
|
||||
|
||||
/* in case of no payload (Size = 0), sender is only pinging the system;
|
||||
Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
|
||||
if (Size == 0U)
|
||||
{
|
||||
__HAL_CEC_LAST_BYTE_TX_SET(hcec);
|
||||
}
|
||||
|
||||
/* send header block */
|
||||
hcec->Instance->TXDR = (uint32_t)(((uint32_t)InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress);
|
||||
|
||||
/* Set TX Start of Message (TXSOM) bit */
|
||||
__HAL_CEC_FIRST_BYTE_TX_SET(hcec);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hcec);
|
||||
|
||||
return HAL_OK;
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get size of the received frame.
|
||||
* @param hcec CEC handle
|
||||
* @retval Frame size
|
||||
*/
|
||||
uint32_t HAL_CEC_GetLastReceivedFrameSize(const CEC_HandleTypeDef *hcec)
|
||||
{
|
||||
return hcec->RxXferSize;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Change Rx Buffer.
|
||||
* @param hcec CEC handle
|
||||
* @param Rxbuffer Rx Buffer
|
||||
* @note This function can be called only inside the HAL_CEC_RxCpltCallback()
|
||||
* @retval Frame size
|
||||
*/
|
||||
void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer)
|
||||
{
|
||||
hcec->Init.RxBuffer = Rxbuffer;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles CEC interrupt requests.
|
||||
* @param hcec CEC handle
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
|
||||
{
|
||||
|
||||
/* save interrupts register for further error or interrupts handling purposes */
|
||||
uint32_t itflag;
|
||||
itflag = hcec->Instance->ISR;
|
||||
|
||||
|
||||
/* ----------------------------Arbitration Lost Management----------------------------------*/
|
||||
/* CEC TX arbitration error interrupt occurred --------------------------------------*/
|
||||
if (HAL_IS_BIT_SET(itflag, CEC_FLAG_ARBLST))
|
||||
{
|
||||
hcec->ErrorCode = HAL_CEC_ERROR_ARBLST;
|
||||
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST);
|
||||
}
|
||||
|
||||
/* ----------------------------Rx Management----------------------------------*/
|
||||
/* CEC RX byte received interrupt ---------------------------------------------------*/
|
||||
if (HAL_IS_BIT_SET(itflag, CEC_FLAG_RXBR))
|
||||
{
|
||||
/* reception is starting */
|
||||
hcec->RxState = HAL_CEC_STATE_BUSY_RX;
|
||||
hcec->RxXferSize++;
|
||||
/* read received byte */
|
||||
*hcec->Init.RxBuffer = (uint8_t) hcec->Instance->RXDR;
|
||||
hcec->Init.RxBuffer++;
|
||||
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR);
|
||||
}
|
||||
|
||||
/* CEC RX end received interrupt ---------------------------------------------------*/
|
||||
if (HAL_IS_BIT_SET(itflag, CEC_FLAG_RXEND))
|
||||
{
|
||||
/* clear IT */
|
||||
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND);
|
||||
|
||||
/* Rx process is completed, restore hcec->RxState to Ready */
|
||||
hcec->RxState = HAL_CEC_STATE_READY;
|
||||
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
|
||||
hcec->Init.RxBuffer -= hcec->RxXferSize;
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1U)
|
||||
hcec->RxCpltCallback(hcec, hcec->RxXferSize);
|
||||
#else
|
||||
HAL_CEC_RxCpltCallback(hcec, hcec->RxXferSize);
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
hcec->RxXferSize = 0U;
|
||||
}
|
||||
|
||||
/* ----------------------------Tx Management----------------------------------*/
|
||||
/* CEC TX byte request interrupt ------------------------------------------------*/
|
||||
if (HAL_IS_BIT_SET(itflag, CEC_FLAG_TXBR))
|
||||
{
|
||||
--hcec->TxXferCount;
|
||||
if (hcec->TxXferCount == 0U)
|
||||
{
|
||||
/* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
|
||||
__HAL_CEC_LAST_BYTE_TX_SET(hcec);
|
||||
}
|
||||
/* In all cases transmit the byte */
|
||||
hcec->Instance->TXDR = (uint8_t) * hcec->pTxBuffPtr;
|
||||
hcec->pTxBuffPtr++;
|
||||
/* clear Tx-Byte request flag */
|
||||
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR);
|
||||
}
|
||||
|
||||
/* CEC TX end interrupt ------------------------------------------------*/
|
||||
if (HAL_IS_BIT_SET(itflag, CEC_FLAG_TXEND))
|
||||
{
|
||||
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND);
|
||||
|
||||
/* Tx process is ended, restore hcec->gState to Ready */
|
||||
hcec->gState = HAL_CEC_STATE_READY;
|
||||
/* Call the Process Unlocked before calling the Tx call back API to give the possibility to
|
||||
start again the Transmission under the Tx call back API */
|
||||
__HAL_UNLOCK(hcec);
|
||||
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1U)
|
||||
hcec->TxCpltCallback(hcec);
|
||||
#else
|
||||
HAL_CEC_TxCpltCallback(hcec);
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
}
|
||||
|
||||
/* ----------------------------Rx/Tx Error Management----------------------------------*/
|
||||
if ((itflag & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE | CEC_ISR_TXUDR |
|
||||
CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U)
|
||||
{
|
||||
hcec->ErrorCode = itflag;
|
||||
__HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR | HAL_CEC_ERROR_BRE | CEC_FLAG_LBPE | CEC_FLAG_SBPE |
|
||||
HAL_CEC_ERROR_RXACKE | HAL_CEC_ERROR_TXUDR | HAL_CEC_ERROR_TXERR | HAL_CEC_ERROR_TXACKE);
|
||||
|
||||
|
||||
if ((itflag & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE)) != 0U)
|
||||
{
|
||||
hcec->Init.RxBuffer -= hcec->RxXferSize;
|
||||
hcec->RxXferSize = 0U;
|
||||
hcec->RxState = HAL_CEC_STATE_READY;
|
||||
}
|
||||
else if (((itflag & CEC_ISR_ARBLST) == 0U) && ((itflag & (CEC_ISR_TXUDR | CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U))
|
||||
{
|
||||
/* Set the CEC state ready to be able to start again the process */
|
||||
hcec->gState = HAL_CEC_STATE_READY;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Nothing todo*/
|
||||
}
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1U)
|
||||
hcec->ErrorCallback(hcec);
|
||||
#else
|
||||
/* Error Call Back */
|
||||
HAL_CEC_ErrorCallback(hcec);
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Nothing todo*/
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Tx Transfer completed callback
|
||||
* @param hcec CEC handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcec);
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_CEC_TxCpltCallback can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Rx Transfer completed callback
|
||||
* @param hcec CEC handle
|
||||
* @param RxFrameSize Size of frame
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcec);
|
||||
UNUSED(RxFrameSize);
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_CEC_RxCpltCallback can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief CEC error callbacks
|
||||
* @param hcec CEC handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcec);
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_CEC_ErrorCallback can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control function
|
||||
* @brief CEC control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control function #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the CEC.
|
||||
(+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral.
|
||||
(+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral.
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief return the CEC state
|
||||
* @param hcec pointer to a CEC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified CEC module.
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_CEC_StateTypeDef HAL_CEC_GetState(const CEC_HandleTypeDef *hcec)
|
||||
{
|
||||
uint32_t temp1;
|
||||
uint32_t temp2;
|
||||
temp1 = hcec->gState;
|
||||
temp2 = hcec->RxState;
|
||||
|
||||
return (HAL_CEC_StateTypeDef)(temp1 | temp2);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the CEC error code
|
||||
* @param hcec pointer to a CEC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified CEC.
|
||||
* @retval CEC Error Code
|
||||
*/
|
||||
uint32_t HAL_CEC_GetError(const CEC_HandleTypeDef *hcec)
|
||||
{
|
||||
return hcec->ErrorCode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* CEC */
|
||||
#endif /* HAL_CEC_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
983
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_comp.c
Normal file
983
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_comp.c
Normal file
@@ -0,0 +1,983 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_comp.c
|
||||
* @author MCD Application Team
|
||||
* @brief COMP HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the COMP peripheral:
|
||||
* + Initialization/de-initialization functions
|
||||
* + Peripheral Control functions
|
||||
* + Peripheral State functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
================================================================================
|
||||
##### COMP Peripheral features #####
|
||||
================================================================================
|
||||
|
||||
[..]
|
||||
The STM32F0xx device family integrates up to 2 analog comparators COMP1 and COMP2:
|
||||
(+) The non inverting input and inverting input can be set to GPIO pins.
|
||||
|
||||
(+) The COMP output is available using HAL_COMP_GetOutputLevel()
|
||||
and can be set on GPIO pins.
|
||||
|
||||
(+) The COMP output can be redirected to embedded timers (TIM1, TIM2 and TIM3).
|
||||
|
||||
(+) The comparators COMP1 and COMP2 can be combined in window mode.
|
||||
|
||||
(+) The comparators have interrupt capability with wake-up
|
||||
from Sleep and Stop modes (through the EXTI controller):
|
||||
(++) COMP1 is internally connected to EXTI Line 21
|
||||
(++) COMP2 is internally connected to EXTI Line 22
|
||||
|
||||
(+) From the corresponding IRQ handler, the right interrupt source can be retrieved with the
|
||||
macros __HAL_COMP_COMP1_EXTI_GET_FLAG() and __HAL_COMP_COMP2_EXTI_GET_FLAG().
|
||||
|
||||
|
||||
##### How to use this driver #####
|
||||
================================================================================
|
||||
[..]
|
||||
This driver provides functions to configure and program the Comparators of STM32F05x, STM32F07x and STM32F09x devices.
|
||||
|
||||
To use the comparator, perform the following steps:
|
||||
|
||||
(#) Fill in the HAL_COMP_MspInit() to
|
||||
(++) Configure the comparator input in analog mode using HAL_GPIO_Init()
|
||||
(++) Configure the comparator output in alternate function mode using HAL_GPIO_Init() to map the comparator
|
||||
output to the GPIO pin
|
||||
(++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and
|
||||
selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator
|
||||
interrupt vector using HAL_NVIC_EnableIRQ() function.
|
||||
|
||||
(#) Configure the comparator using HAL_COMP_Init() function:
|
||||
(++) Select the inverting input (input minus)
|
||||
(++) Select the non inverting input (input plus)
|
||||
(++) Select the output polarity
|
||||
(++) Select the output redirection
|
||||
(++) Select the hysteresis level
|
||||
(++) Select the power mode
|
||||
(++) Select the event/interrupt mode
|
||||
(++) Select the window mode
|
||||
|
||||
-@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE() in order
|
||||
to access the comparator(s) registers.
|
||||
|
||||
(#) Enable the comparator using HAL_COMP_Start() function or HAL_COMP_Start_IT() function for interrupt mode.
|
||||
|
||||
(#) Use HAL_COMP_TriggerCallback() and/or HAL_COMP_GetOutputLevel() functions
|
||||
to manage comparator outputs (event/interrupt triggered and output level).
|
||||
|
||||
(#) Disable the comparator using HAL_COMP_Stop() or HAL_COMP_Stop_IT()
|
||||
function.
|
||||
|
||||
(#) De-initialize the comparator using HAL_COMP_DeInit() function.
|
||||
|
||||
(#) For safety purposes comparator(s) can be locked using HAL_COMP_Lock() function.
|
||||
Only a MCU reset can reset that protection.
|
||||
|
||||
*** Callback registration ***
|
||||
=============================================
|
||||
[..]
|
||||
|
||||
The compilation flag USE_HAL_COMP_REGISTER_CALLBACKS, when set to 1,
|
||||
allows the user to configure dynamically the driver callbacks.
|
||||
Use Functions HAL_COMP_RegisterCallback()
|
||||
to register an interrupt callback.
|
||||
[..]
|
||||
|
||||
Function HAL_COMP_RegisterCallback() allows to register following callbacks:
|
||||
(+) OperationCpltCallback : callback for End of operation.
|
||||
(+) ErrorCallback : callback for error detection.
|
||||
(+) MspInitCallback : callback for Msp Init.
|
||||
(+) MspDeInitCallback : callback for Msp DeInit.
|
||||
This function takes as parameters the HAL peripheral handle, the Callback ID
|
||||
and a pointer to the user callback function.
|
||||
[..]
|
||||
|
||||
Use function HAL_COMP_UnRegisterCallback to reset a callback to the default
|
||||
weak function.
|
||||
[..]
|
||||
|
||||
HAL_COMP_UnRegisterCallback takes as parameters the HAL peripheral handle,
|
||||
and the Callback ID.
|
||||
This function allows to reset following callbacks:
|
||||
(+) OperationCpltCallback : callback for End of operation.
|
||||
(+) ErrorCallback : callback for error detection.
|
||||
(+) MspInitCallback : callback for Msp Init.
|
||||
(+) MspDeInitCallback : callback for Msp DeInit.
|
||||
[..]
|
||||
|
||||
By default, after the HAL_COMP_Init() and when the state is HAL_COMP_STATE_RESET
|
||||
all callbacks are set to the corresponding weak functions:
|
||||
examples HAL_COMP_OperationCpltCallback(), HAL_COMP_ErrorCallback().
|
||||
Exception done for MspInit and MspDeInit functions that are
|
||||
reset to the legacy weak functions in the HAL_COMP_Init()/ HAL_COMP_DeInit() only when
|
||||
these callbacks are null (not registered beforehand).
|
||||
[..]
|
||||
|
||||
If MspInit or MspDeInit are not null, the HAL_COMP_Init()/ HAL_COMP_DeInit()
|
||||
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
|
||||
[..]
|
||||
|
||||
Callbacks can be registered/unregistered in HAL_COMP_STATE_READY state only.
|
||||
Exception done MspInit/MspDeInit functions that can be registered/unregistered
|
||||
in HAL_COMP_STATE_READY or HAL_COMP_STATE_RESET state,
|
||||
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
|
||||
[..]
|
||||
|
||||
Then, the user first registers the MspInit/MspDeInit user callbacks
|
||||
using HAL_COMP_RegisterCallback() before calling HAL_COMP_DeInit()
|
||||
or HAL_COMP_Init() function.
|
||||
[..]
|
||||
|
||||
When the compilation flag USE_HAL_COMP_REGISTER_CALLBACKS is set to 0 or
|
||||
not defined, the callback registration feature is not available and all callbacks
|
||||
are set to the corresponding weak functions.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/*
|
||||
Additional Tables:
|
||||
|
||||
Table 1. COMP Inputs for the STM32F05x, STM32F07x and STM32F09x devices
|
||||
+--------------------------------------------------+
|
||||
| | | COMP1 | COMP2 |
|
||||
|-----------------|----------------|---------------|
|
||||
| | 1/4 VREFINT | OK | OK |
|
||||
| | 1/2 VREFINT | OK | OK |
|
||||
| | 3/4 VREFINT | OK | OK |
|
||||
| Inverting Input | VREFINT | OK | OK |
|
||||
| | DAC1 OUT (PA4) | OK | OK |
|
||||
| | DAC2 OUT (PA5) | OK | OK |
|
||||
| | IO1 | PA0 | PA2 |
|
||||
|-----------------|----------------|-------|-------|
|
||||
| Non Inverting | | PA1 | PA3 |
|
||||
| Input | | | |
|
||||
+--------------------------------------------------+
|
||||
|
||||
Table 2. COMP Outputs for the STM32F05x, STM32F07x and STM32F09x devices
|
||||
+---------------+
|
||||
| COMP1 | COMP2 |
|
||||
|-------|-------|
|
||||
| PA0 | PA2 |
|
||||
| PA6 | PA7 |
|
||||
| PA11 | PA12 |
|
||||
+---------------+
|
||||
|
||||
Table 3. COMP Outputs redirection to embedded timers for the STM32F05x, STM32F07x and STM32F09x devices
|
||||
+---------------------------------+
|
||||
| COMP1 | COMP2 |
|
||||
|----------------|----------------|
|
||||
| TIM1 BKIN | TIM1 BKIN |
|
||||
| | |
|
||||
| TIM1 OCREFCLR | TIM1 OCREFCLR |
|
||||
| | |
|
||||
| TIM1 IC1 | TIM1 IC1 |
|
||||
| | |
|
||||
| TIM2 IC4 | TIM2 IC4 |
|
||||
| | |
|
||||
| TIM2 OCREFCLR | TIM2 OCREFCLR |
|
||||
| | |
|
||||
| TIM3 IC1 | TIM3 IC1 |
|
||||
| | |
|
||||
| TIM3 OCREFCLR | TIM3 OCREFCLR |
|
||||
+---------------------------------+
|
||||
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
#ifdef HAL_COMP_MODULE_ENABLED
|
||||
|
||||
#if defined (COMP1) || defined (COMP2)
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP COMP
|
||||
* @brief COMP HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup COMP_Private_Constants COMP Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Delay for COMP startup time. */
|
||||
/* Note: Delay required to reach propagation delay specification. */
|
||||
/* Literal set to maximum value (refer to device datasheet, */
|
||||
/* parameter "tSTART"). */
|
||||
/* Unit: us */
|
||||
#define COMP_DELAY_STARTUP_US (60U) /*!< Delay for COMP startup time */
|
||||
|
||||
/* CSR register reset value */
|
||||
#define COMP_CSR_RESET_VALUE (0x00000000U)
|
||||
/* CSR register masks */
|
||||
#define COMP_CSR_RESET_PARAMETERS_MASK (0x00003FFFU)
|
||||
#define COMP_CSR_UPDATE_PARAMETERS_MASK (0x00003FFEU)
|
||||
/* CSR COMPx non inverting input mask */
|
||||
#define COMP_CSR_COMPxNONINSEL_MASK ((uint16_t)COMP_CSR_COMP1SW1)
|
||||
/* CSR COMP2 shift */
|
||||
#define COMP_CSR_COMP1_SHIFT 0U
|
||||
#define COMP_CSR_COMP2_SHIFT 16U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup COMP_Exported_Functions COMP Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Configuration functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions to initialize and de-initialize comparators
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the COMP according to the specified
|
||||
* parameters in the COMP_InitTypeDef and create the associated handle.
|
||||
* @note If the selected comparator is locked, initialization can't be performed.
|
||||
* To unlock the configuration, perform a system reset.
|
||||
* @param hcomp COMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint32_t regshift = COMP_CSR_COMP1_SHIFT;
|
||||
|
||||
/* Check the COMP handle allocation and lock status */
|
||||
if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
assert_param(IS_COMP_INVERTINGINPUT(hcomp->Init.InvertingInput));
|
||||
assert_param(IS_COMP_NONINVERTINGINPUT(hcomp->Init.NonInvertingInput));
|
||||
assert_param(IS_COMP_OUTPUT(hcomp->Init.Output));
|
||||
assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol));
|
||||
assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis));
|
||||
assert_param(IS_COMP_MODE(hcomp->Init.Mode));
|
||||
|
||||
if(hcomp->Init.NonInvertingInput == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED)
|
||||
{
|
||||
assert_param(IS_COMP_DAC1SWITCH_INSTANCE(hcomp->Instance));
|
||||
}
|
||||
|
||||
if(hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLE)
|
||||
{
|
||||
assert_param(IS_COMP_WINDOWMODE_INSTANCE(hcomp->Instance));
|
||||
}
|
||||
|
||||
/* Init SYSCFG and the low level hardware to access comparators */
|
||||
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||||
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
||||
/* Init the COMP Callback settings */
|
||||
hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */
|
||||
|
||||
if (hcomp->MspInitCallback == NULL)
|
||||
{
|
||||
hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */
|
||||
}
|
||||
|
||||
/* Init the low level hardware */
|
||||
hcomp->MspInitCallback(hcomp);
|
||||
#else
|
||||
/* Init the low level hardware : SYSCFG to access comparators */
|
||||
HAL_COMP_MspInit(hcomp);
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
|
||||
if(hcomp->State == HAL_COMP_STATE_RESET)
|
||||
{
|
||||
/* Allocate lock resource and initialize it */
|
||||
hcomp->Lock = HAL_UNLOCKED;
|
||||
}
|
||||
|
||||
/* Change COMP peripheral state */
|
||||
hcomp->State = HAL_COMP_STATE_BUSY;
|
||||
|
||||
/* Set COMP parameters */
|
||||
/* Set COMPxINSEL bits according to hcomp->Init.InvertingInput value */
|
||||
/* Set COMPxOUTSEL bits according to hcomp->Init.Output value */
|
||||
/* Set COMPxPOL bit according to hcomp->Init.OutputPol value */
|
||||
/* Set COMPxHYST bits according to hcomp->Init.Hysteresis value */
|
||||
/* Set COMPxMODE bits according to hcomp->Init.Mode value */
|
||||
if(hcomp->Instance == COMP2)
|
||||
{
|
||||
regshift = COMP_CSR_COMP2_SHIFT;
|
||||
}
|
||||
MODIFY_REG(COMP->CSR,
|
||||
(COMP_CSR_COMPxINSEL | COMP_CSR_COMPxNONINSEL_MASK | \
|
||||
COMP_CSR_COMPxOUTSEL | COMP_CSR_COMPxPOL | \
|
||||
COMP_CSR_COMPxHYST | COMP_CSR_COMPxMODE) << regshift,
|
||||
(hcomp->Init.InvertingInput | \
|
||||
hcomp->Init.NonInvertingInput | \
|
||||
hcomp->Init.Output | \
|
||||
hcomp->Init.OutputPol | \
|
||||
hcomp->Init.Hysteresis | \
|
||||
hcomp->Init.Mode) << regshift);
|
||||
|
||||
if(hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLE)
|
||||
{
|
||||
COMP->CSR |= COMP_CSR_WNDWEN;
|
||||
}
|
||||
|
||||
/* Initialize the COMP state*/
|
||||
hcomp->State = HAL_COMP_STATE_READY;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the COMP peripheral
|
||||
* @note Deinitialization can't be performed if the COMP configuration is locked.
|
||||
* To unlock the configuration, perform a system reset.
|
||||
* @param hcomp COMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint32_t regshift = COMP_CSR_COMP1_SHIFT;
|
||||
|
||||
/* Check the COMP handle allocation and lock status */
|
||||
if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
|
||||
/* Set COMP_CSR register to reset value for the corresponding COMP instance */
|
||||
if(hcomp->Instance == COMP2)
|
||||
{
|
||||
regshift = COMP_CSR_COMP2_SHIFT;
|
||||
}
|
||||
MODIFY_REG(COMP->CSR,
|
||||
COMP_CSR_RESET_PARAMETERS_MASK << regshift,
|
||||
COMP_CSR_RESET_VALUE << regshift);
|
||||
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
||||
if (hcomp->MspDeInitCallback == NULL)
|
||||
{
|
||||
hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */
|
||||
}
|
||||
|
||||
/* DeInit the low level hardware: SYSCFG, GPIO, CLOCK and NVIC */
|
||||
hcomp->MspDeInitCallback(hcomp);
|
||||
#else
|
||||
/* DeInit the low level hardware: SYSCFG, GPIO, CLOCK and NVIC */
|
||||
HAL_COMP_MspDeInit(hcomp);
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
|
||||
hcomp->State = HAL_COMP_STATE_RESET;
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hcomp);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the COMP MSP.
|
||||
* @param hcomp COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcomp);
|
||||
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_COMP_MspInit could be implenetd in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes COMP MSP.
|
||||
* @param hcomp COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcomp);
|
||||
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_COMP_MspDeInit could be implenetd in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief Register a User COMP Callback
|
||||
* To be used instead of the weak predefined callback
|
||||
* @param hcomp Pointer to a COMP_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified COMP.
|
||||
* @param CallbackID ID of the callback to be registered
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref HAL_COMP_TRIGGER_CB_ID Trigger callback ID
|
||||
* @arg @ref HAL_COMP_MSPINIT_CB_ID MspInit callback ID
|
||||
* @arg @ref HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID
|
||||
* @param pCallback pointer to the Callback function
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
if (pCallback == NULL)
|
||||
{
|
||||
/* Update the error code */
|
||||
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if (HAL_COMP_STATE_READY == hcomp->State)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_COMP_TRIGGER_CB_ID :
|
||||
hcomp->TriggerCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_COMP_MSPINIT_CB_ID :
|
||||
hcomp->MspInitCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_COMP_MSPDEINIT_CB_ID :
|
||||
hcomp->MspDeInitCallback = pCallback;
|
||||
break;
|
||||
|
||||
default :
|
||||
/* Update the error code */
|
||||
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
|
||||
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else if (HAL_COMP_STATE_RESET == hcomp->State)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_COMP_MSPINIT_CB_ID :
|
||||
hcomp->MspInitCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_COMP_MSPDEINIT_CB_ID :
|
||||
hcomp->MspDeInitCallback = pCallback;
|
||||
break;
|
||||
|
||||
default :
|
||||
/* Update the error code */
|
||||
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
|
||||
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update the error code */
|
||||
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
|
||||
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unregister a COMP Callback
|
||||
* COMP callback is redirected to the weak predefined callback
|
||||
* @param hcomp Pointer to a COMP_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified COMP.
|
||||
* @param CallbackID ID of the callback to be unregistered
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref HAL_COMP_TRIGGER_CB_ID Trigger callback ID
|
||||
* @arg @ref HAL_COMP_MSPINIT_CB_ID MspInit callback ID
|
||||
* @arg @ref HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
if (HAL_COMP_STATE_READY == hcomp->State)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_COMP_TRIGGER_CB_ID :
|
||||
hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */
|
||||
break;
|
||||
|
||||
case HAL_COMP_MSPINIT_CB_ID :
|
||||
hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */
|
||||
break;
|
||||
|
||||
case HAL_COMP_MSPDEINIT_CB_ID :
|
||||
hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */
|
||||
break;
|
||||
|
||||
default :
|
||||
/* Update the error code */
|
||||
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
|
||||
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else if (HAL_COMP_STATE_RESET == hcomp->State)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_COMP_MSPINIT_CB_ID :
|
||||
hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */
|
||||
break;
|
||||
|
||||
case HAL_COMP_MSPDEINIT_CB_ID :
|
||||
hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */
|
||||
break;
|
||||
|
||||
default :
|
||||
/* Update the error code */
|
||||
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
|
||||
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update the error code */
|
||||
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
|
||||
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Exported_Functions_Group2 I/O operation functions
|
||||
* @brief Data transfers functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to manage the COMP data
|
||||
transfers.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Start the comparator
|
||||
* @param hcomp COMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
uint32_t wait_loop_index = 0U;
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint32_t regshift = COMP_CSR_COMP1_SHIFT;
|
||||
|
||||
/* Check the COMP handle allocation and lock status */
|
||||
if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
|
||||
if(hcomp->State == HAL_COMP_STATE_READY)
|
||||
{
|
||||
/* Enable the selected comparator */
|
||||
if(hcomp->Instance == COMP2)
|
||||
{
|
||||
regshift = COMP_CSR_COMP2_SHIFT;
|
||||
}
|
||||
SET_BIT(COMP->CSR, COMP_CSR_COMPxEN << regshift);
|
||||
|
||||
/* Set HAL COMP handle state */
|
||||
hcomp->State = HAL_COMP_STATE_BUSY;
|
||||
|
||||
/* Delay for COMP startup time */
|
||||
wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / 1000000U));
|
||||
while(wait_loop_index != 0U)
|
||||
{
|
||||
wait_loop_index--;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stop the comparator
|
||||
* @param hcomp COMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint32_t regshift = COMP_CSR_COMP1_SHIFT;
|
||||
|
||||
/* Check the COMP handle allocation and lock status */
|
||||
if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
|
||||
if(hcomp->State == HAL_COMP_STATE_BUSY)
|
||||
{
|
||||
/* Disable the selected comparator */
|
||||
if(hcomp->Instance == COMP2)
|
||||
{
|
||||
regshift = COMP_CSR_COMP2_SHIFT;
|
||||
}
|
||||
CLEAR_BIT(COMP->CSR, COMP_CSR_COMPxEN << regshift);
|
||||
|
||||
hcomp->State = HAL_COMP_STATE_READY;
|
||||
}
|
||||
else
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the interrupt and starts the comparator
|
||||
* @param hcomp COMP handle
|
||||
* @retval HAL status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint32_t extiline = 0U;
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode));
|
||||
|
||||
status = HAL_COMP_Start(hcomp);
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Check the Exti Line output configuration */
|
||||
extiline = COMP_GET_EXTI_LINE(hcomp->Instance);
|
||||
/* Configure the rising edge */
|
||||
if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_RISING) != RESET)
|
||||
{
|
||||
SET_BIT(EXTI->RTSR, extiline);
|
||||
}
|
||||
else
|
||||
{
|
||||
CLEAR_BIT(EXTI->RTSR, extiline);
|
||||
}
|
||||
/* Configure the falling edge */
|
||||
if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_FALLING) != RESET)
|
||||
{
|
||||
SET_BIT(EXTI->FTSR, extiline);
|
||||
}
|
||||
else
|
||||
{
|
||||
CLEAR_BIT(EXTI->FTSR, extiline);
|
||||
}
|
||||
|
||||
/* Clear COMP EXTI pending bit */
|
||||
WRITE_REG(EXTI->PR, extiline);
|
||||
|
||||
/* Enable Exti interrupt mode */
|
||||
SET_BIT(EXTI->IMR, extiline);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the interrupt and Stop the comparator
|
||||
* @param hcomp COMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Disable the Exti Line interrupt mode */
|
||||
CLEAR_BIT(EXTI->IMR, COMP_GET_EXTI_LINE(hcomp->Instance));
|
||||
|
||||
status = HAL_COMP_Stop(hcomp);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Comparator IRQ Handler
|
||||
* @param hcomp COMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
uint32_t extiline = COMP_GET_EXTI_LINE(hcomp->Instance);
|
||||
|
||||
/* Check COMP Exti flag */
|
||||
if(READ_BIT(EXTI->PR, extiline) != RESET)
|
||||
{
|
||||
/* Clear COMP Exti pending bit */
|
||||
WRITE_REG(EXTI->PR, extiline);
|
||||
|
||||
/* COMP trigger callback */
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
||||
hcomp->TriggerCallback(hcomp);
|
||||
#else
|
||||
HAL_COMP_TriggerCallback(hcomp);
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @brief management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the COMP data
|
||||
transfers.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Lock the selected comparator configuration.
|
||||
* @param hcomp COMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint32_t regshift = COMP_CSR_COMP1_SHIFT;
|
||||
|
||||
/* Check the COMP handle allocation and lock status */
|
||||
if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
|
||||
/* Set lock flag */
|
||||
hcomp->State |= COMP_STATE_BIT_LOCK;
|
||||
|
||||
/* Set the lock bit corresponding to selected comparator */
|
||||
if(hcomp->Instance == COMP2)
|
||||
{
|
||||
regshift = COMP_CSR_COMP2_SHIFT;
|
||||
}
|
||||
SET_BIT(COMP->CSR, COMP_CSR_COMPxLOCK << regshift);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the output level (high or low) of the selected comparator.
|
||||
* The output level depends on the selected polarity.
|
||||
* If the polarity is not inverted:
|
||||
* - Comparator output is low when the non-inverting input is at a lower
|
||||
* voltage than the inverting input
|
||||
* - Comparator output is high when the non-inverting input is at a higher
|
||||
* voltage than the inverting input
|
||||
* If the polarity is inverted:
|
||||
* - Comparator output is high when the non-inverting input is at a lower
|
||||
* voltage than the inverting input
|
||||
* - Comparator output is low when the non-inverting input is at a higher
|
||||
* voltage than the inverting input
|
||||
* @param hcomp COMP handle
|
||||
* @retval Returns the selected comparator output level: COMP_OUTPUTLEVEL_LOW or COMP_OUTPUTLEVEL_HIGH.
|
||||
*
|
||||
*/
|
||||
uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
uint32_t level=0;
|
||||
uint32_t regshift = COMP_CSR_COMP1_SHIFT;
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
|
||||
if(hcomp->Instance == COMP2)
|
||||
{
|
||||
regshift = COMP_CSR_COMP2_SHIFT;
|
||||
}
|
||||
level = READ_BIT(COMP->CSR, COMP_CSR_COMPxOUT << regshift);
|
||||
|
||||
if(level != 0U)
|
||||
{
|
||||
return(COMP_OUTPUTLEVEL_HIGH);
|
||||
}
|
||||
return(COMP_OUTPUTLEVEL_LOW);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Comparator trigger callback.
|
||||
* @param hcomp COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcomp);
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_COMP_TriggerCallback should be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral State functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection permit to get in run-time the status of the peripheral
|
||||
and the data flow.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Return the COMP state
|
||||
* @param hcomp COMP handle
|
||||
* @retval HAL state
|
||||
*/
|
||||
uint32_t HAL_COMP_GetState(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
/* Check the COMP handle allocation */
|
||||
if(hcomp == NULL)
|
||||
{
|
||||
return HAL_COMP_STATE_RESET;
|
||||
}
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
|
||||
return hcomp->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the COMP error code.
|
||||
* @param hcomp COMP handle
|
||||
* @retval COMP error code
|
||||
*/
|
||||
uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
|
||||
return hcomp->ErrorCode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* COMP1 || COMP2 */
|
||||
|
||||
#endif /* HAL_COMP_MODULE_ENABLED */
|
||||
|
||||
|
||||
342
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c
Normal file
342
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c
Normal file
@@ -0,0 +1,342 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_cortex.c
|
||||
* @author MCD Application Team
|
||||
* @brief CORTEX HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the CORTEX:
|
||||
* + Initialization and de-initialization functions
|
||||
* + Peripheral Control functions
|
||||
*
|
||||
* @verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
|
||||
[..]
|
||||
*** How to configure Interrupts using CORTEX HAL driver ***
|
||||
===========================================================
|
||||
[..]
|
||||
This section provides functions allowing to configure the NVIC interrupts (IRQ).
|
||||
The Cortex-M0 exceptions are managed by CMSIS functions.
|
||||
(#) Enable and Configure the priority of the selected IRQ Channels.
|
||||
The priority can be 0..3.
|
||||
|
||||
-@- Lower priority values gives higher priority.
|
||||
-@- Priority Order:
|
||||
(#@) Lowest priority.
|
||||
(#@) Lowest hardware priority (IRQn position).
|
||||
|
||||
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
|
||||
|
||||
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
|
||||
|
||||
-@- Negative value of IRQn_Type are not allowed.
|
||||
|
||||
|
||||
[..]
|
||||
*** How to configure Systick using CORTEX HAL driver ***
|
||||
========================================================
|
||||
[..]
|
||||
Setup SysTick Timer for time base.
|
||||
|
||||
(+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
|
||||
is a CMSIS function that:
|
||||
(++) Configures the SysTick Reload register with value passed as function parameter.
|
||||
(++) Configures the SysTick IRQ priority to the lowest value (0x03).
|
||||
(++) Resets the SysTick Counter register.
|
||||
(++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
|
||||
(++) Enables the SysTick Interrupt.
|
||||
(++) Starts the SysTick Counter.
|
||||
|
||||
(+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
|
||||
HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
|
||||
HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() macro is defined
|
||||
inside the stm32f0xx_hal_cortex.h file.
|
||||
|
||||
(+) You can change the SysTick IRQ priority by calling the
|
||||
HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
|
||||
call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
|
||||
|
||||
(+) To adjust the SysTick time base, use the following formula:
|
||||
|
||||
Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
|
||||
(++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
|
||||
(++) Reload Value should not exceed 0xFFFFFF
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX CORTEX
|
||||
* @brief CORTEX CORTEX HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This section provides the CORTEX HAL driver functions allowing to configure Interrupts
|
||||
Systick functionalities
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Sets the priority of an interrupt.
|
||||
* @param IRQn External interrupt number .
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32f0xx.h file)
|
||||
* @param PreemptPriority The preemption priority for the IRQn channel.
|
||||
* This parameter can be a value between 0 and 3.
|
||||
* A lower priority value indicates a higher priority
|
||||
* @param SubPriority the subpriority level for the IRQ channel.
|
||||
* with stm32f0xx devices, this parameter is a dummy value and it is ignored, because
|
||||
* no subpriority supported in Cortex M0 based products.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
||||
NVIC_SetPriority(IRQn,PreemptPriority);
|
||||
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(SubPriority);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables a device specific interrupt in the NVIC interrupt controller.
|
||||
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
|
||||
* function should be called before.
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Enable interrupt */
|
||||
NVIC_EnableIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables a device specific interrupt in the NVIC interrupt controller.
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Disable interrupt */
|
||||
NVIC_DisableIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initiates a system reset request to reset the MCU.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SystemReset(void)
|
||||
{
|
||||
/* System Reset */
|
||||
NVIC_SystemReset();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
* Counter is in free running mode to generate periodic interrupts.
|
||||
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
|
||||
* @retval status: - 0 Function succeeded.
|
||||
* - 1 Function failed.
|
||||
*/
|
||||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
||||
{
|
||||
return SysTick_Config(TicksNumb);
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief Cortex control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the CORTEX
|
||||
(NVIC, SYSTICK) functionalities.
|
||||
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Gets the priority of an interrupt.
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn)
|
||||
{
|
||||
/* Get priority for Cortex-M system or device specific interrupts */
|
||||
return NVIC_GetPriority(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets Pending bit of an external interrupt.
|
||||
* @param IRQn External interrupt number
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Set interrupt pending */
|
||||
NVIC_SetPendingIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets Pending Interrupt (reads the pending register in the NVIC
|
||||
* and returns the pending bit for the specified interrupt).
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
|
||||
* @retval status: - 0 Interrupt status is not pending.
|
||||
* - 1 Interrupt status is pending.
|
||||
*/
|
||||
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Return 1 if pending else 0 */
|
||||
return NVIC_GetPendingIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the pending bit of an external interrupt.
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Clear pending interrupt */
|
||||
NVIC_ClearPendingIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the SysTick clock source.
|
||||
* @param CLKSource specifies the SysTick clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
|
||||
* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
|
||||
if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
|
||||
{
|
||||
SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
|
||||
}
|
||||
else
|
||||
{
|
||||
SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles SYSTICK interrupt request.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SYSTICK_IRQHandler(void)
|
||||
{
|
||||
HAL_SYSTICK_Callback();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SYSTICK callback.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_SYSTICK_Callback(void)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_SYSTICK_Callback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
518
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_crc.c
Normal file
518
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_crc.c
Normal file
@@ -0,0 +1,518 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_crc.c
|
||||
* @author MCD Application Team
|
||||
* @brief CRC HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Cyclic Redundancy Check (CRC) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + Peripheral Control functions
|
||||
* + Peripheral State functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### How to use this driver #####
|
||||
===============================================================================
|
||||
[..]
|
||||
(+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
|
||||
(+) Initialize CRC calculator
|
||||
(++) specify generating polynomial (peripheral default or non-default one)
|
||||
(++) specify initialization value (peripheral default or non-default one)
|
||||
(++) specify input data format
|
||||
(++) specify input or output data inversion mode if any
|
||||
(+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
|
||||
input data buffer starting with the previously computed CRC as
|
||||
initialization value
|
||||
(+) Use HAL_CRC_Calculate() function to compute the CRC value of the
|
||||
input data buffer starting with the defined initialization value
|
||||
(default or non-default) to initiate CRC calculation
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC CRC
|
||||
* @brief CRC HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_CRC_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup CRC_Private_Functions CRC Private Functions
|
||||
* @{
|
||||
*/
|
||||
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
|
||||
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRC_Exported_Functions CRC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Initialize the CRC according to the specified parameters
|
||||
in the CRC_InitTypeDef and create the associated handle
|
||||
(+) DeInitialize the CRC peripheral
|
||||
(+) Initialize the CRC MSP (MCU Specific Package)
|
||||
(+) DeInitialize the CRC MSP
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initialize the CRC according to the specified
|
||||
* parameters in the CRC_InitTypeDef and create the associated handle.
|
||||
* @param hcrc CRC handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
/* Check the CRC handle allocation */
|
||||
if (hcrc == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
|
||||
|
||||
if (hcrc->State == HAL_CRC_STATE_RESET)
|
||||
{
|
||||
/* Allocate lock resource and initialize it */
|
||||
hcrc->Lock = HAL_UNLOCKED;
|
||||
/* Init the low level hardware */
|
||||
HAL_CRC_MspInit(hcrc);
|
||||
}
|
||||
|
||||
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||
|
||||
#if defined(CRC_POL_POL)
|
||||
/* check whether or not non-default generating polynomial has been
|
||||
* picked up by user */
|
||||
assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
|
||||
if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
|
||||
{
|
||||
/* initialize peripheral with default generating polynomial */
|
||||
WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
|
||||
MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* initialize CRC peripheral with generating polynomial defined by user */
|
||||
if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
#endif /* CRC_POL_POL */
|
||||
|
||||
/* check whether or not non-default CRC initial value has been
|
||||
* picked up by user */
|
||||
assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
|
||||
if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
|
||||
{
|
||||
WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
|
||||
}
|
||||
else
|
||||
{
|
||||
WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
|
||||
}
|
||||
|
||||
|
||||
/* set input data inversion mode */
|
||||
assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
|
||||
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
|
||||
|
||||
/* set output data inversion mode */
|
||||
assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
|
||||
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
|
||||
|
||||
/* makes sure the input data format (bytes, halfwords or words stream)
|
||||
* is properly specified by user */
|
||||
assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_READY;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitialize the CRC peripheral.
|
||||
* @param hcrc CRC handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
/* Check the CRC handle allocation */
|
||||
if (hcrc == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
|
||||
|
||||
/* Check the CRC peripheral state */
|
||||
if (hcrc->State == HAL_CRC_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||
|
||||
/* Reset CRC calculation unit */
|
||||
__HAL_CRC_DR_RESET(hcrc);
|
||||
|
||||
/* Reset IDR register content */
|
||||
__HAL_CRC_SET_IDR(hcrc, 0);
|
||||
|
||||
/* DeInit the low level hardware */
|
||||
HAL_CRC_MspDeInit(hcrc);
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_RESET;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hcrc);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the CRC MSP.
|
||||
* @param hcrc CRC handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcrc);
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_CRC_MspInit can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitialize the CRC MSP.
|
||||
* @param hcrc CRC handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcrc);
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_CRC_MspDeInit can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief management functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
|
||||
using combination of the previous CRC value and the new one.
|
||||
|
||||
[..] or
|
||||
|
||||
(+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
|
||||
independently of the previous CRC value.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
|
||||
* starting with the previously computed CRC as initialization value.
|
||||
* @param hcrc CRC handle
|
||||
* @param pBuffer pointer to the input data buffer, exact input data format is
|
||||
* provided by hcrc->InputDataFormat.
|
||||
* @param BufferLength input data buffer length (number of bytes if pBuffer
|
||||
* type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
|
||||
* number of words if pBuffer type is * uint32_t).
|
||||
* @note By default, the API expects a uint32_t pointer as input buffer parameter.
|
||||
* Input buffer pointers with other types simply need to be cast in uint32_t
|
||||
* and the API will internally adjust its input data processing based on the
|
||||
* handle field hcrc->InputDataFormat.
|
||||
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
|
||||
*/
|
||||
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
|
||||
{
|
||||
uint32_t index; /* CRC input data buffer index */
|
||||
uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||
|
||||
switch (hcrc->InputDataFormat)
|
||||
{
|
||||
case CRC_INPUTDATA_FORMAT_WORDS:
|
||||
/* Enter Data to the CRC calculator */
|
||||
for (index = 0U; index < BufferLength; index++)
|
||||
{
|
||||
hcrc->Instance->DR = pBuffer[index];
|
||||
}
|
||||
temp = hcrc->Instance->DR;
|
||||
break;
|
||||
|
||||
case CRC_INPUTDATA_FORMAT_BYTES:
|
||||
temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
|
||||
break;
|
||||
|
||||
case CRC_INPUTDATA_FORMAT_HALFWORDS:
|
||||
temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_READY;
|
||||
|
||||
/* Return the CRC computed value */
|
||||
return temp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
|
||||
* starting with hcrc->Instance->INIT as initialization value.
|
||||
* @param hcrc CRC handle
|
||||
* @param pBuffer pointer to the input data buffer, exact input data format is
|
||||
* provided by hcrc->InputDataFormat.
|
||||
* @param BufferLength input data buffer length (number of bytes if pBuffer
|
||||
* type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
|
||||
* number of words if pBuffer type is * uint32_t).
|
||||
* @note By default, the API expects a uint32_t pointer as input buffer parameter.
|
||||
* Input buffer pointers with other types simply need to be cast in uint32_t
|
||||
* and the API will internally adjust its input data processing based on the
|
||||
* handle field hcrc->InputDataFormat.
|
||||
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
|
||||
*/
|
||||
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
|
||||
{
|
||||
uint32_t index; /* CRC input data buffer index */
|
||||
uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||
|
||||
/* Reset CRC Calculation Unit (hcrc->Instance->INIT is
|
||||
* written in hcrc->Instance->DR) */
|
||||
__HAL_CRC_DR_RESET(hcrc);
|
||||
|
||||
switch (hcrc->InputDataFormat)
|
||||
{
|
||||
case CRC_INPUTDATA_FORMAT_WORDS:
|
||||
/* Enter 32-bit input data to the CRC calculator */
|
||||
for (index = 0U; index < BufferLength; index++)
|
||||
{
|
||||
hcrc->Instance->DR = pBuffer[index];
|
||||
}
|
||||
temp = hcrc->Instance->DR;
|
||||
break;
|
||||
|
||||
case CRC_INPUTDATA_FORMAT_BYTES:
|
||||
/* Specific 8-bit input data handling */
|
||||
temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
|
||||
break;
|
||||
|
||||
case CRC_INPUTDATA_FORMAT_HALFWORDS:
|
||||
/* Specific 16-bit input data handling */
|
||||
temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_READY;
|
||||
|
||||
/* Return the CRC computed value */
|
||||
return temp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
|
||||
* @brief Peripheral State functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral State functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection permits to get in run-time the status of the peripheral.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Return the CRC handle state.
|
||||
* @param hcrc CRC handle
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
/* Return CRC handle state */
|
||||
return hcrc->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enter 8-bit input data to the CRC calculator.
|
||||
* Specific data handling to optimize processing time.
|
||||
* @param hcrc CRC handle
|
||||
* @param pBuffer pointer to the input data buffer
|
||||
* @param BufferLength input data buffer length
|
||||
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
|
||||
*/
|
||||
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
|
||||
{
|
||||
uint32_t i; /* input data buffer index */
|
||||
uint16_t data;
|
||||
__IO uint16_t *pReg;
|
||||
|
||||
/* Processing time optimization: 4 bytes are entered in a row with a single word write,
|
||||
* last bytes must be carefully fed to the CRC calculator to ensure a correct type
|
||||
* handling by the peripheral */
|
||||
for (i = 0U; i < (BufferLength / 4U); i++)
|
||||
{
|
||||
hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \
|
||||
((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \
|
||||
((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \
|
||||
(uint32_t)pBuffer[(4U * i) + 3U];
|
||||
}
|
||||
/* last bytes specific handling */
|
||||
if ((BufferLength % 4U) != 0U)
|
||||
{
|
||||
if ((BufferLength % 4U) == 1U)
|
||||
{
|
||||
*(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */
|
||||
}
|
||||
if ((BufferLength % 4U) == 2U)
|
||||
{
|
||||
data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
|
||||
pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
|
||||
*pReg = data;
|
||||
}
|
||||
if ((BufferLength % 4U) == 3U)
|
||||
{
|
||||
data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
|
||||
pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
|
||||
*pReg = data;
|
||||
|
||||
*(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */
|
||||
}
|
||||
}
|
||||
|
||||
/* Return the CRC computed value */
|
||||
return hcrc->Instance->DR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enter 16-bit input data to the CRC calculator.
|
||||
* Specific data handling to optimize processing time.
|
||||
* @param hcrc CRC handle
|
||||
* @param pBuffer pointer to the input data buffer
|
||||
* @param BufferLength input data buffer length
|
||||
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
|
||||
*/
|
||||
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
|
||||
{
|
||||
uint32_t i; /* input data buffer index */
|
||||
__IO uint16_t *pReg;
|
||||
|
||||
/* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
|
||||
* in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
|
||||
* a correct type handling by the peripheral */
|
||||
for (i = 0U; i < (BufferLength / 2U); i++)
|
||||
{
|
||||
hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U];
|
||||
}
|
||||
if ((BufferLength % 2U) != 0U)
|
||||
{
|
||||
pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
|
||||
*pReg = pBuffer[2U * i];
|
||||
}
|
||||
|
||||
/* Return the CRC computed value */
|
||||
return hcrc->Instance->DR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
232
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_crc_ex.c
Normal file
232
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_crc_ex.c
Normal file
@@ -0,0 +1,232 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_crc_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief Extended CRC HAL module driver.
|
||||
* This file provides firmware functions to manage the extended
|
||||
* functionalities of the CRC peripheral.
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
================================================================================
|
||||
##### How to use this driver #####
|
||||
================================================================================
|
||||
[..]
|
||||
(+) Set user-defined generating polynomial through HAL_CRCEx_Polynomial_Set()
|
||||
(+) Configure Input or Output data inversion
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRCEx CRCEx
|
||||
* @brief CRC Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_CRC_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions
|
||||
* @brief Extended Initialization and Configuration functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extended configuration functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure the generating polynomial
|
||||
(+) Configure the input data inversion
|
||||
(+) Configure the output data inversion
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
#if defined(CRC_POL_POL)
|
||||
/**
|
||||
* @brief Initialize the CRC polynomial if different from default one.
|
||||
* @param hcrc CRC handle
|
||||
* @param Pol CRC generating polynomial (7, 8, 16 or 32-bit long).
|
||||
* This parameter is written in normal representation, e.g.
|
||||
* @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
|
||||
* @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
|
||||
* @param PolyLength CRC polynomial length.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CRC_POLYLENGTH_7B 7-bit long CRC (generating polynomial of degree 7)
|
||||
* @arg @ref CRC_POLYLENGTH_8B 8-bit long CRC (generating polynomial of degree 8)
|
||||
* @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16)
|
||||
* @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32)
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CRC_POL_LENGTH(PolyLength));
|
||||
|
||||
/* Ensure that the generating polynomial is odd */
|
||||
if ((Pol & (uint32_t)(0x1U)) == 0U)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* check polynomial definition vs polynomial size:
|
||||
* polynomial length must be aligned with polynomial
|
||||
* definition. HAL_ERROR is reported if Pol degree is
|
||||
* larger than that indicated by PolyLength.
|
||||
* Look for MSB position: msb will contain the degree of
|
||||
* the second to the largest polynomial member. E.g., for
|
||||
* X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
|
||||
while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
|
||||
{
|
||||
}
|
||||
|
||||
switch (PolyLength)
|
||||
{
|
||||
|
||||
case CRC_POLYLENGTH_7B:
|
||||
if (msb >= HAL_CRC_LENGTH_7B)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
break;
|
||||
case CRC_POLYLENGTH_8B:
|
||||
if (msb >= HAL_CRC_LENGTH_8B)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
break;
|
||||
case CRC_POLYLENGTH_16B:
|
||||
if (msb >= HAL_CRC_LENGTH_16B)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
break;
|
||||
|
||||
case CRC_POLYLENGTH_32B:
|
||||
/* no polynomial definition vs. polynomial length issue possible */
|
||||
break;
|
||||
default:
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (status == HAL_OK)
|
||||
{
|
||||
/* set generating polynomial */
|
||||
WRITE_REG(hcrc->Instance->POL, Pol);
|
||||
|
||||
/* set generating polynomial size */
|
||||
MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
|
||||
}
|
||||
/* Return function status */
|
||||
return status;
|
||||
}
|
||||
#endif /* CRC_POL_POL */
|
||||
|
||||
/**
|
||||
* @brief Set the Reverse Input data mode.
|
||||
* @param hcrc CRC handle
|
||||
* @param InputReverseMode Input Data inversion mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CRC_INPUTDATA_INVERSION_NONE no change in bit order (default value)
|
||||
* @arg @ref CRC_INPUTDATA_INVERSION_BYTE Byte-wise bit reversal
|
||||
* @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD HalfWord-wise bit reversal
|
||||
* @arg @ref CRC_INPUTDATA_INVERSION_WORD Word-wise bit reversal
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode));
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||
|
||||
/* set input data inversion mode */
|
||||
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode);
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_READY;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Reverse Output data mode.
|
||||
* @param hcrc CRC handle
|
||||
* @param OutputReverseMode Output Data inversion mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion (default value)
|
||||
* @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD)
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode));
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||
|
||||
/* set output data inversion mode */
|
||||
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode);
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_READY;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
1088
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dac.c
Normal file
1088
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dac.c
Normal file
File diff suppressed because it is too large
Load Diff
1182
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dac_ex.c
Normal file
1182
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dac_ex.c
Normal file
File diff suppressed because it is too large
Load Diff
899
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c
Normal file
899
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c
Normal file
@@ -0,0 +1,899 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_dma.c
|
||||
* @author MCD Application Team
|
||||
* @brief DMA HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Direct Memory Access (DMA) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + IO operation functions
|
||||
* + Peripheral State and errors functions
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) Enable and configure the peripheral to be connected to the DMA Channel
|
||||
(except for internal SRAM / FLASH memories: no initialization is
|
||||
necessary). Please refer to Reference manual for connection between peripherals
|
||||
and DMA requests .
|
||||
|
||||
(#) For a given Channel, program the required configuration through the following parameters:
|
||||
Transfer Direction, Source and Destination data formats,
|
||||
Circular or Normal mode, Channel Priority level, Source and Destination Increment mode,
|
||||
using HAL_DMA_Init() function.
|
||||
|
||||
(#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
|
||||
detection.
|
||||
|
||||
(#) Use HAL_DMA_Abort() function to abort the current transfer
|
||||
|
||||
-@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
|
||||
*** Polling mode IO operation ***
|
||||
=================================
|
||||
[..]
|
||||
(+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
|
||||
address and destination address and the Length of data to be transferred
|
||||
(+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
|
||||
case a fixed Timeout can be configured by User depending from his application.
|
||||
|
||||
*** Interrupt mode IO operation ***
|
||||
===================================
|
||||
[..]
|
||||
(+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
|
||||
(+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
|
||||
(+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
|
||||
Source address and destination address and the Length of data to be transferred.
|
||||
In this case the DMA interrupt is configured
|
||||
(+) Use HAL_DMA_Channel_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
|
||||
(+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
|
||||
add his own function by customization of function pointer XferCpltCallback and
|
||||
XferErrorCallback (i.e a member of DMA handle structure).
|
||||
|
||||
*** DMA HAL driver macros list ***
|
||||
=============================================
|
||||
[..]
|
||||
Below the list of most used macros in DMA HAL driver.
|
||||
|
||||
[..]
|
||||
(@) You can refer to the DMA HAL driver header file for more useful macros
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA DMA
|
||||
* @brief DMA HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup DMA_Private_Functions DMA Private Functions
|
||||
* @{
|
||||
*/
|
||||
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||||
static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions DMA Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and de-initialization functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This section provides functions allowing to initialize the DMA Channel source
|
||||
and destination addresses, incrementation and data sizes, transfer direction,
|
||||
circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
|
||||
[..]
|
||||
The HAL_DMA_Init() function follows the DMA configuration procedures as described in
|
||||
reference manual.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initialize the DMA according to the specified
|
||||
* parameters in the DMA_InitTypeDef and initialize the associated handle.
|
||||
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
/* Check the DMA handle allocation */
|
||||
if (NULL == hdma)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
|
||||
assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
|
||||
assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
|
||||
assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
|
||||
assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
|
||||
assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
|
||||
assert_param(IS_DMA_MODE(hdma->Init.Mode));
|
||||
assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
|
||||
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
|
||||
/* Get the CR register value */
|
||||
tmp = hdma->Instance->CCR;
|
||||
|
||||
/* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
|
||||
tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
|
||||
DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
|
||||
DMA_CCR_DIR));
|
||||
|
||||
/* Prepare the DMA Channel configuration */
|
||||
tmp |= hdma->Init.Direction |
|
||||
hdma->Init.PeriphInc | hdma->Init.MemInc |
|
||||
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
|
||||
hdma->Init.Mode | hdma->Init.Priority;
|
||||
|
||||
/* Write to DMA Channel CR register */
|
||||
hdma->Instance->CCR = tmp;
|
||||
|
||||
/* Initialize DmaBaseAddress and ChannelIndex parameters used
|
||||
by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
|
||||
DMA_CalcBaseAndBitshift(hdma);
|
||||
|
||||
/* Initialise the error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
||||
|
||||
/* Initialize the DMA state*/
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Allocate lock resource and initialize it */
|
||||
hdma->Lock = HAL_UNLOCKED;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitialize the DMA peripheral
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
/* Check the DMA handle allocation */
|
||||
if (NULL == hdma)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
|
||||
|
||||
/* Disable the selected DMA Channelx */
|
||||
hdma->Instance->CCR &= ~DMA_CCR_EN;
|
||||
|
||||
/* Reset DMA Channel control register */
|
||||
hdma->Instance->CCR = 0U;
|
||||
|
||||
/* Reset DMA Channel Number of Data to Transfer register */
|
||||
hdma->Instance->CNDTR = 0U;
|
||||
|
||||
/* Reset DMA Channel peripheral address register */
|
||||
hdma->Instance->CPAR = 0U;
|
||||
|
||||
/* Reset DMA Channel memory address register */
|
||||
hdma->Instance->CMAR = 0U;
|
||||
|
||||
/* Get DMA Base Address */
|
||||
DMA_CalcBaseAndBitshift(hdma);
|
||||
|
||||
/* Clear all flags */
|
||||
hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
|
||||
|
||||
/* Clean callbacks */
|
||||
hdma->XferCpltCallback = NULL;
|
||||
hdma->XferHalfCpltCallback = NULL;
|
||||
hdma->XferErrorCallback = NULL;
|
||||
hdma->XferAbortCallback = NULL;
|
||||
|
||||
/* Reset the error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
||||
|
||||
/* Reset the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_RESET;
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @brief I/O operation functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure the source, destination address and data length and Start DMA transfer
|
||||
(+) Configure the source, destination address and data length and
|
||||
Start DMA transfer with interrupt
|
||||
(+) Abort DMA transfer
|
||||
(+) Poll for transfer complete
|
||||
(+) Handle DMA interrupt request
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Start the DMA Transfer.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @param SrcAddress The source memory Buffer address
|
||||
* @param DstAddress The destination memory Buffer address
|
||||
* @param DataLength The length of data to be transferred from source to destination
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
if (HAL_DMA_STATE_READY == hdma->State)
|
||||
{
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
||||
|
||||
/* Disable the peripheral */
|
||||
hdma->Instance->CCR &= ~DMA_CCR_EN;
|
||||
|
||||
/* Configure the source, destination address and the data length */
|
||||
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
|
||||
|
||||
/* Enable the Peripheral */
|
||||
hdma->Instance->CCR |= DMA_CCR_EN;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
/* Remain BUSY */
|
||||
status = HAL_BUSY;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Start the DMA Transfer with interrupt enabled.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @param SrcAddress The source memory Buffer address
|
||||
* @param DstAddress The destination memory Buffer address
|
||||
* @param DataLength The length of data to be transferred from source to destination
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
if (HAL_DMA_STATE_READY == hdma->State)
|
||||
{
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
||||
|
||||
/* Disable the peripheral */
|
||||
hdma->Instance->CCR &= ~DMA_CCR_EN;
|
||||
|
||||
/* Configure the source, destination address and the data length */
|
||||
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
|
||||
|
||||
/* Enable the transfer complete, & transfer error interrupts */
|
||||
/* Half transfer interrupt is optional: enable it only if associated callback is available */
|
||||
if (NULL != hdma->XferHalfCpltCallback)
|
||||
{
|
||||
hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
|
||||
}
|
||||
else
|
||||
{
|
||||
hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE);
|
||||
hdma->Instance->CCR &= ~DMA_IT_HT;
|
||||
}
|
||||
|
||||
/* Enable the Peripheral */
|
||||
hdma->Instance->CCR |= DMA_CCR_EN;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
/* Remain BUSY */
|
||||
status = HAL_BUSY;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Abort the DMA Transfer.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
if (hdma->State != HAL_DMA_STATE_BUSY)
|
||||
{
|
||||
/* no transfer ongoing */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable DMA IT */
|
||||
hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
|
||||
|
||||
/* Disable the channel */
|
||||
hdma->Instance->CCR &= ~DMA_CCR_EN;
|
||||
|
||||
/* Clear all flags */
|
||||
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex);
|
||||
}
|
||||
/* Change the DMA state*/
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Abort the DMA Transfer in Interrupt mode.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
if (HAL_DMA_STATE_BUSY != hdma->State)
|
||||
{
|
||||
/* no transfer ongoing */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
||||
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
||||
/* Disable DMA IT */
|
||||
hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
|
||||
|
||||
/* Disable the channel */
|
||||
hdma->Instance->CCR &= ~DMA_CCR_EN;
|
||||
|
||||
/* Clear all flags */
|
||||
hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
/* Call User Abort callback */
|
||||
if (hdma->XferAbortCallback != NULL)
|
||||
{
|
||||
hdma->XferAbortCallback(hdma);
|
||||
}
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Polling for transfer complete.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @param CompleteLevel Specifies the DMA level complete.
|
||||
* @param Timeout Timeout duration.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
|
||||
{
|
||||
uint32_t temp;
|
||||
uint32_t tickstart = 0U;
|
||||
|
||||
if (HAL_DMA_STATE_BUSY != hdma->State)
|
||||
{
|
||||
/* no transfer ongoing */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
||||
__HAL_UNLOCK(hdma);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Polling mode not supported in circular mode */
|
||||
if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC))
|
||||
{
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Get the level transfer complete flag */
|
||||
if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
|
||||
{
|
||||
/* Transfer Complete flag */
|
||||
temp = DMA_FLAG_TC1 << hdma->ChannelIndex;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Half Transfer Complete flag */
|
||||
temp = DMA_FLAG_HT1 << hdma->ChannelIndex;
|
||||
}
|
||||
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
while (RESET == (hdma->DmaBaseAddress->ISR & temp))
|
||||
{
|
||||
if (RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex)))
|
||||
{
|
||||
/* When a DMA transfer error occurs */
|
||||
/* A hardware clear of its EN bits is performed */
|
||||
/* Clear all flags */
|
||||
hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
|
||||
|
||||
/* Update error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_TE;
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Check for the Timeout */
|
||||
if (Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
|
||||
{
|
||||
/* Update error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
|
||||
{
|
||||
/* Clear the transfer complete flag */
|
||||
hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
|
||||
|
||||
/* The selected Channelx EN bit is cleared (DMA is disabled and
|
||||
all transfers are complete) */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear the half transfer complete flag */
|
||||
hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
|
||||
}
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handle DMA interrupt request.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
uint32_t flag_it = hdma->DmaBaseAddress->ISR;
|
||||
uint32_t source_it = hdma->Instance->CCR;
|
||||
|
||||
/* Half Transfer Complete Interrupt management ******************************/
|
||||
if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT)))
|
||||
{
|
||||
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
|
||||
if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
|
||||
{
|
||||
/* Disable the half transfer interrupt */
|
||||
hdma->Instance->CCR &= ~DMA_IT_HT;
|
||||
}
|
||||
|
||||
/* Clear the half transfer complete flag */
|
||||
hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
|
||||
|
||||
/* DMA peripheral state is not updated in Half Transfer */
|
||||
/* State is updated only in Transfer Complete case */
|
||||
|
||||
if (hdma->XferHalfCpltCallback != NULL)
|
||||
{
|
||||
/* Half transfer callback */
|
||||
hdma->XferHalfCpltCallback(hdma);
|
||||
}
|
||||
}
|
||||
|
||||
/* Transfer Complete Interrupt management ***********************************/
|
||||
else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC)))
|
||||
{
|
||||
if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
|
||||
{
|
||||
/* Disable the transfer complete & transfer error interrupts */
|
||||
/* if the DMA mode is not CIRCULAR */
|
||||
hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE);
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
}
|
||||
|
||||
/* Clear the transfer complete flag */
|
||||
hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
if (hdma->XferCpltCallback != NULL)
|
||||
{
|
||||
/* Transfer complete callback */
|
||||
hdma->XferCpltCallback(hdma);
|
||||
}
|
||||
}
|
||||
|
||||
/* Transfer Error Interrupt management ***************************************/
|
||||
else if ((RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
|
||||
{
|
||||
/* When a DMA transfer error occurs */
|
||||
/* A hardware clear of its EN bits is performed */
|
||||
/* Then, disable all DMA interrupts */
|
||||
hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
|
||||
|
||||
/* Clear all flags */
|
||||
hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
|
||||
|
||||
/* Update error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_TE;
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
if (hdma->XferErrorCallback != NULL)
|
||||
{
|
||||
/* Transfer error callback */
|
||||
hdma->XferErrorCallback(hdma);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Register callbacks
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @param CallbackID User Callback identifier
|
||||
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
|
||||
* @param pCallback pointer to private callback function which has pointer to
|
||||
* a DMA_HandleTypeDef structure as parameter.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
if (HAL_DMA_STATE_READY == hdma->State)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_DMA_XFER_CPLT_CB_ID:
|
||||
hdma->XferCpltCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_HALFCPLT_CB_ID:
|
||||
hdma->XferHalfCpltCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_ERROR_CB_ID:
|
||||
hdma->XferErrorCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_ABORT_CB_ID:
|
||||
hdma->XferAbortCallback = pCallback;
|
||||
break;
|
||||
|
||||
default:
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief UnRegister callbacks
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @param CallbackID User Callback identifier
|
||||
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
if (HAL_DMA_STATE_READY == hdma->State)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_DMA_XFER_CPLT_CB_ID:
|
||||
hdma->XferCpltCallback = NULL;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_HALFCPLT_CB_ID:
|
||||
hdma->XferHalfCpltCallback = NULL;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_ERROR_CB_ID:
|
||||
hdma->XferErrorCallback = NULL;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_ABORT_CB_ID:
|
||||
hdma->XferAbortCallback = NULL;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_ALL_CB_ID:
|
||||
hdma->XferCpltCallback = NULL;
|
||||
hdma->XferHalfCpltCallback = NULL;
|
||||
hdma->XferErrorCallback = NULL;
|
||||
hdma->XferAbortCallback = NULL;
|
||||
break;
|
||||
|
||||
default:
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### State and Errors functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides functions allowing to
|
||||
(+) Check the DMA state
|
||||
(+) Get error code
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Returns the DMA state.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
return hdma->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the DMA error code
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval DMA Error Code
|
||||
*/
|
||||
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
return hdma->ErrorCode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set the DMA Transfer parameters.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @param SrcAddress The source memory Buffer address
|
||||
* @param DstAddress The destination memory Buffer address
|
||||
* @param DataLength The length of data to be transferred from source to destination
|
||||
* @retval HAL status
|
||||
*/
|
||||
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
||||
{
|
||||
/* Clear all flags */
|
||||
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex);
|
||||
|
||||
/* Configure DMA Channel data length */
|
||||
hdma->Instance->CNDTR = DataLength;
|
||||
|
||||
/* Memory to Peripheral */
|
||||
if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
|
||||
{
|
||||
/* Configure DMA Channel destination address */
|
||||
hdma->Instance->CPAR = DstAddress;
|
||||
|
||||
/* Configure DMA Channel source address */
|
||||
hdma->Instance->CMAR = SrcAddress;
|
||||
}
|
||||
/* Peripheral to Memory */
|
||||
else
|
||||
{
|
||||
/* Configure DMA Channel source address */
|
||||
hdma->Instance->CPAR = SrcAddress;
|
||||
|
||||
/* Configure DMA Channel destination address */
|
||||
hdma->Instance->CMAR = DstAddress;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set the DMA base address and channel index depending on DMA instance
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @retval None
|
||||
*/
|
||||
static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
#if defined (DMA2)
|
||||
/* calculation of the channel index */
|
||||
if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
|
||||
{
|
||||
/* DMA1 */
|
||||
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
|
||||
hdma->DmaBaseAddress = DMA1;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DMA2 */
|
||||
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
|
||||
hdma->DmaBaseAddress = DMA2;
|
||||
}
|
||||
#else
|
||||
/* calculation of the channel index */
|
||||
/* DMA1 */
|
||||
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
|
||||
hdma->DmaBaseAddress = DMA1;
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
547
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c
Normal file
547
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c
Normal file
@@ -0,0 +1,547 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_exti.c
|
||||
* @author MCD Application Team
|
||||
* @brief EXTI HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Extended Interrupts and events controller (EXTI) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + IO operation functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### EXTI Peripheral features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(+) Each Exti line can be configured within this driver.
|
||||
|
||||
(+) Exti line can be configured in 3 different modes
|
||||
(++) Interrupt
|
||||
(++) Event
|
||||
(++) Both of them
|
||||
|
||||
(+) Configurable Exti lines can be configured with 3 different triggers
|
||||
(++) Rising
|
||||
(++) Falling
|
||||
(++) Both of them
|
||||
|
||||
(+) When set in interrupt mode, configurable Exti lines have two different
|
||||
interrupts pending registers which allow to distinguish which transition
|
||||
occurs:
|
||||
(++) Rising edge pending interrupt
|
||||
(++) Falling
|
||||
|
||||
(+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
|
||||
be selected through multiplexer.
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
|
||||
(#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
|
||||
(++) Choose the interrupt line number by setting "Line" member from
|
||||
EXTI_ConfigTypeDef structure.
|
||||
(++) Configure the interrupt and/or event mode using "Mode" member from
|
||||
EXTI_ConfigTypeDef structure.
|
||||
(++) For configurable lines, configure rising and/or falling trigger
|
||||
"Trigger" member from EXTI_ConfigTypeDef structure.
|
||||
(++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
|
||||
member from GPIO_InitTypeDef structure.
|
||||
|
||||
(#) Get current Exti configuration of a dedicated line using
|
||||
HAL_EXTI_GetConfigLine().
|
||||
(++) Provide exiting handle as parameter.
|
||||
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
|
||||
|
||||
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine().
|
||||
(++) Provide exiting handle as parameter.
|
||||
|
||||
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
|
||||
(++) Provide exiting handle as first parameter.
|
||||
(++) Provide which callback will be registered using one value from
|
||||
EXTI_CallbackIDTypeDef.
|
||||
(++) Provide callback function pointer.
|
||||
|
||||
(#) Get interrupt pending bit using HAL_EXTI_GetPending().
|
||||
|
||||
(#) Clear interrupt pending bit using HAL_EXTI_ClearPending().
|
||||
|
||||
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
|
||||
|
||||
@endverbatim
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI
|
||||
* @{
|
||||
*/
|
||||
/** MISRA C:2012 deviation rule has been granted for following rule:
|
||||
* Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
|
||||
* of bounds [0,3] in following API :
|
||||
* HAL_EXTI_SetConfigLine
|
||||
* HAL_EXTI_GetConfigLine
|
||||
* HAL_EXTI_ClearConfigLine
|
||||
*/
|
||||
|
||||
#ifdef HAL_EXTI_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Private_Constants EXTI Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup EXTI_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI_Exported_Functions_Group1
|
||||
* @brief Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Configuration functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set configuration of a dedicated Exti line.
|
||||
* @param hexti Exti handle.
|
||||
* @param pExtiConfig Pointer on EXTI configuration to be set.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t linepos;
|
||||
uint32_t maskline;
|
||||
|
||||
/* Check null pointer */
|
||||
if ((hexti == NULL) || (pExtiConfig == NULL))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_EXTI_LINE(pExtiConfig->Line));
|
||||
assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
|
||||
|
||||
/* Assign line number to handle */
|
||||
hexti->Line = pExtiConfig->Line;
|
||||
|
||||
/* Compute line mask */
|
||||
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
|
||||
maskline = (1uL << linepos);
|
||||
|
||||
/* Configure triggers for configurable lines */
|
||||
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
|
||||
{
|
||||
assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
|
||||
|
||||
/* Configure rising trigger */
|
||||
/* Mask or set line */
|
||||
if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
|
||||
{
|
||||
EXTI->RTSR |= maskline;
|
||||
}
|
||||
else
|
||||
{
|
||||
EXTI->RTSR &= ~maskline;
|
||||
}
|
||||
|
||||
/* Configure falling trigger */
|
||||
/* Mask or set line */
|
||||
if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
|
||||
{
|
||||
EXTI->FTSR |= maskline;
|
||||
}
|
||||
else
|
||||
{
|
||||
EXTI->FTSR &= ~maskline;
|
||||
}
|
||||
|
||||
|
||||
/* Configure gpio port selection in case of gpio exti line */
|
||||
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
|
||||
{
|
||||
assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
|
||||
assert_param(IS_EXTI_GPIO_PIN(linepos));
|
||||
|
||||
regval = SYSCFG->EXTICR[linepos >> 2u];
|
||||
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
|
||||
regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
|
||||
SYSCFG->EXTICR[linepos >> 2u] = regval;
|
||||
}
|
||||
}
|
||||
|
||||
/* Configure interrupt mode : read current mode */
|
||||
/* Mask or set line */
|
||||
if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
|
||||
{
|
||||
EXTI->IMR |= maskline;
|
||||
}
|
||||
else
|
||||
{
|
||||
EXTI->IMR &= ~maskline;
|
||||
}
|
||||
|
||||
/* Configure event mode : read current mode */
|
||||
/* Mask or set line */
|
||||
if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
|
||||
{
|
||||
EXTI->EMR |= maskline;
|
||||
}
|
||||
else
|
||||
{
|
||||
EXTI->EMR &= ~maskline;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get configuration of a dedicated Exti line.
|
||||
* @param hexti Exti handle.
|
||||
* @param pExtiConfig Pointer on structure to store Exti configuration.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t linepos;
|
||||
uint32_t maskline;
|
||||
|
||||
/* Check null pointer */
|
||||
if ((hexti == NULL) || (pExtiConfig == NULL))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
|
||||
/* Store handle line number to configuration structure */
|
||||
pExtiConfig->Line = hexti->Line;
|
||||
|
||||
/* Compute line mask */
|
||||
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
|
||||
maskline = (1uL << linepos);
|
||||
|
||||
/* 1] Get core mode : interrupt */
|
||||
|
||||
/* Check if selected line is enable */
|
||||
if ((EXTI->IMR & maskline) != 0x00u)
|
||||
{
|
||||
pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
|
||||
}
|
||||
else
|
||||
{
|
||||
pExtiConfig->Mode = EXTI_MODE_NONE;
|
||||
}
|
||||
|
||||
/* Get event mode */
|
||||
/* Check if selected line is enable */
|
||||
if ((EXTI->EMR & maskline) != 0x00u)
|
||||
{
|
||||
pExtiConfig->Mode |= EXTI_MODE_EVENT;
|
||||
}
|
||||
|
||||
/* Get default Trigger and GPIOSel configuration */
|
||||
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
|
||||
pExtiConfig->GPIOSel = 0x00u;
|
||||
|
||||
/* 2] Get trigger for configurable lines : rising */
|
||||
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
|
||||
{
|
||||
/* Check if configuration of selected line is enable */
|
||||
if ((EXTI->RTSR & maskline) != 0x00u)
|
||||
{
|
||||
pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
|
||||
}
|
||||
|
||||
/* Get falling configuration */
|
||||
/* Check if configuration of selected line is enable */
|
||||
if ((EXTI->FTSR & maskline) != 0x00u)
|
||||
{
|
||||
pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
|
||||
}
|
||||
|
||||
/* Get Gpio port selection for gpio lines */
|
||||
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
|
||||
{
|
||||
assert_param(IS_EXTI_GPIO_PIN(linepos));
|
||||
|
||||
regval = SYSCFG->EXTICR[linepos >> 2u];
|
||||
pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EXTICR1_EXTI0;
|
||||
}
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear whole configuration of a dedicated Exti line.
|
||||
* @param hexti Exti handle.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t linepos;
|
||||
uint32_t maskline;
|
||||
|
||||
/* Check null pointer */
|
||||
if (hexti == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
|
||||
/* compute line mask */
|
||||
linepos = (hexti->Line & EXTI_PIN_MASK);
|
||||
maskline = (1uL << linepos);
|
||||
|
||||
/* 1] Clear interrupt mode */
|
||||
EXTI->IMR = (EXTI->IMR & ~maskline);
|
||||
|
||||
/* 2] Clear event mode */
|
||||
EXTI->EMR = (EXTI->EMR & ~maskline);
|
||||
|
||||
/* 3] Clear triggers in case of configurable lines */
|
||||
if ((hexti->Line & EXTI_CONFIG) != 0x00u)
|
||||
{
|
||||
EXTI->RTSR = (EXTI->RTSR & ~maskline);
|
||||
EXTI->FTSR = (EXTI->FTSR & ~maskline);
|
||||
|
||||
/* Get Gpio port selection for gpio lines */
|
||||
if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
|
||||
{
|
||||
assert_param(IS_EXTI_GPIO_PIN(linepos));
|
||||
|
||||
regval = SYSCFG->EXTICR[linepos >> 2u];
|
||||
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
|
||||
SYSCFG->EXTICR[linepos >> 2u] = regval;
|
||||
}
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Register callback for a dedicated Exti line.
|
||||
* @param hexti Exti handle.
|
||||
* @param CallbackID User callback identifier.
|
||||
* This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
|
||||
* @param pPendingCbfn function pointer to be stored as callback.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_EXTI_COMMON_CB_ID:
|
||||
hexti->PendingCallback = pPendingCbfn;
|
||||
break;
|
||||
|
||||
default:
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Store line number as handle private field.
|
||||
* @param hexti Exti handle.
|
||||
* @param ExtiLine Exti line number.
|
||||
* This parameter can be from 0 to @ref EXTI_LINE_NB.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_LINE(ExtiLine));
|
||||
|
||||
/* Check null pointer */
|
||||
if (hexti == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Store line number as handle private field */
|
||||
hexti->Line = ExtiLine;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI_Exported_Functions_Group2
|
||||
* @brief EXTI IO functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Handle EXTI interrupt request.
|
||||
* @param hexti Exti handle.
|
||||
* @retval none.
|
||||
*/
|
||||
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t maskline;
|
||||
|
||||
/* Compute line mask */
|
||||
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
|
||||
|
||||
/* Get pending bit */
|
||||
regval = (EXTI->PR & maskline);
|
||||
if (regval != 0x00u)
|
||||
{
|
||||
/* Clear pending bit */
|
||||
EXTI->PR = maskline;
|
||||
|
||||
/* Call callback */
|
||||
if (hexti->PendingCallback != NULL)
|
||||
{
|
||||
hexti->PendingCallback();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get interrupt pending bit of a dedicated line.
|
||||
* @param hexti Exti handle.
|
||||
* @param Edge Specify which pending edge as to be checked.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref EXTI_TRIGGER_RISING_FALLING
|
||||
* This parameter is kept for compatibility with other series.
|
||||
* @retval 1 if interrupt is pending else 0.
|
||||
*/
|
||||
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t linepos;
|
||||
uint32_t maskline;
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_PENDING_EDGE(Edge));
|
||||
|
||||
/* Compute line mask */
|
||||
linepos = (hexti->Line & EXTI_PIN_MASK);
|
||||
maskline = (1uL << linepos);
|
||||
|
||||
/* return 1 if bit is set else 0 */
|
||||
regval = ((EXTI->PR & maskline) >> linepos);
|
||||
return regval;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear interrupt pending bit of a dedicated line.
|
||||
* @param hexti Exti handle.
|
||||
* @param Edge Specify which pending edge as to be clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref EXTI_TRIGGER_RISING_FALLING
|
||||
* This parameter is kept for compatibility with other series.
|
||||
* @retval None.
|
||||
*/
|
||||
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
|
||||
{
|
||||
uint32_t maskline;
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_PENDING_EDGE(Edge));
|
||||
|
||||
/* Compute line mask */
|
||||
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
|
||||
|
||||
/* Clear Pending bit */
|
||||
EXTI->PR = maskline;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Generate a software interrupt for a dedicated line.
|
||||
* @param hexti Exti handle.
|
||||
* @retval None.
|
||||
*/
|
||||
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
|
||||
{
|
||||
uint32_t maskline;
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
|
||||
|
||||
/* Compute line mask */
|
||||
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
|
||||
|
||||
/* Generate Software interrupt */
|
||||
EXTI->SWIER = maskline;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_EXTI_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
691
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c
Normal file
691
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c
Normal file
@@ -0,0 +1,691 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_flash.c
|
||||
* @author MCD Application Team
|
||||
* @brief FLASH HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the internal FLASH memory:
|
||||
* + Program operations functions
|
||||
* + Memory Control functions
|
||||
* + Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### FLASH peripheral features #####
|
||||
==============================================================================
|
||||
[..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
|
||||
to the Flash memory. It implements the erase and program Flash memory operations
|
||||
and the read and write protection mechanisms.
|
||||
|
||||
[..] The Flash memory interface accelerates code execution with a system of instruction
|
||||
prefetch.
|
||||
|
||||
[..] The FLASH main features are:
|
||||
(+) Flash memory read operations
|
||||
(+) Flash memory program/erase operations
|
||||
(+) Read / write protections
|
||||
(+) Prefetch on I-Code
|
||||
(+) Option Bytes programming
|
||||
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This driver provides functions and macros to configure and program the FLASH
|
||||
memory of all STM32F0xx devices.
|
||||
|
||||
(#) FLASH Memory I/O Programming functions: this group includes all needed
|
||||
functions to erase and program the main memory:
|
||||
(++) Lock and Unlock the FLASH interface
|
||||
(++) Erase function: Erase page, erase all pages
|
||||
(++) Program functions: half word, word and doubleword
|
||||
(#) FLASH Option Bytes Programming functions: this group includes all needed
|
||||
functions to manage the Option Bytes:
|
||||
(++) Lock and Unlock the Option Bytes
|
||||
(++) Set/Reset the write protection
|
||||
(++) Set the Read protection Level
|
||||
(++) Program the user Option Bytes
|
||||
(++) Launch the Option Bytes loader
|
||||
(++) Erase Option Bytes
|
||||
(++) Program the data Option Bytes
|
||||
(++) Get the Write protection.
|
||||
(++) Get the user option bytes.
|
||||
|
||||
(#) Interrupts and flags management functions : this group
|
||||
includes all needed functions to:
|
||||
(++) Handle FLASH interrupts
|
||||
(++) Wait for last FLASH operation according to its status
|
||||
(++) Get error flag status
|
||||
|
||||
[..] In addition to these function, this driver includes a set of macros allowing
|
||||
to handle the following operations:
|
||||
|
||||
(+) Set/Get the latency
|
||||
(+) Enable/Disable the prefetch buffer
|
||||
(+) Enable/Disable the FLASH interrupts
|
||||
(+) Monitor the FLASH flags status
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
|
||||
/** @defgroup FLASH FLASH
|
||||
* @brief FLASH HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Constants FLASH Private Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro ---------------------------- ---------------------------------*/
|
||||
/** @defgroup FLASH_Private_Macros FLASH Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Variables FLASH Private Variables
|
||||
* @{
|
||||
*/
|
||||
/* Variables used for Erase pages under interruption*/
|
||||
FLASH_ProcessTypeDef pFlash;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Functions FLASH Private Functions
|
||||
* @{
|
||||
*/
|
||||
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
|
||||
static void FLASH_SetErrorCode(void);
|
||||
extern void FLASH_PageErase(uint32_t PageAddress);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ---------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
|
||||
* @brief Programming operation functions
|
||||
*
|
||||
@verbatim
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Program halfword, word or double word at a specified address
|
||||
* @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
|
||||
* The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
|
||||
*
|
||||
* @note If an erase and a program operations are requested simultaneously,
|
||||
* the erase operation is performed before the program one.
|
||||
*
|
||||
* @note FLASH should be previously erased before new programming (only exception to this
|
||||
* is when 0x0000 is programmed)
|
||||
*
|
||||
* @param TypeProgram Indicate the way to program at a specified address.
|
||||
* This parameter can be a value of @ref FLASH_Type_Program
|
||||
* @param Address Specifie the address to be programmed.
|
||||
* @param Data Specifie the data to be programmed
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_ERROR;
|
||||
uint8_t index = 0U;
|
||||
uint8_t nbiterations = 0U;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
|
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
|
||||
{
|
||||
/* Program halfword (16-bit) at a specified address. */
|
||||
nbiterations = 1U;
|
||||
}
|
||||
else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
|
||||
{
|
||||
/* Program word (32-bit = 2*16-bit) at a specified address. */
|
||||
nbiterations = 2U;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Program double word (64-bit = 4*16-bit) at a specified address. */
|
||||
nbiterations = 4U;
|
||||
}
|
||||
|
||||
for (index = 0U; index < nbiterations; index++)
|
||||
{
|
||||
FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index)));
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* If the program operation is completed, disable the PG Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
|
||||
/* In case of error, stop programming procedure */
|
||||
if (status != HAL_OK)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Program halfword, word or double word at a specified address with interrupt enabled.
|
||||
* @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
|
||||
* The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
|
||||
*
|
||||
* @note If an erase and a program operations are requested simultaneously,
|
||||
* the erase operation is performed before the program one.
|
||||
*
|
||||
* @param TypeProgram Indicate the way to program at a specified address.
|
||||
* This parameter can be a value of @ref FLASH_Type_Program
|
||||
* @param Address Specifie the address to be programmed.
|
||||
* @param Data Specifie the data to be programmed
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
|
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
|
||||
|
||||
/* Enable End of FLASH Operation and Error source interrupts */
|
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
|
||||
|
||||
pFlash.Address = Address;
|
||||
pFlash.Data = Data;
|
||||
|
||||
if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
|
||||
{
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD;
|
||||
/* Program halfword (16-bit) at a specified address. */
|
||||
pFlash.DataRemaining = 1U;
|
||||
}
|
||||
else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
|
||||
{
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD;
|
||||
/* Program word (32-bit : 2*16-bit) at a specified address. */
|
||||
pFlash.DataRemaining = 2U;
|
||||
}
|
||||
else
|
||||
{
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD;
|
||||
/* Program double word (64-bit : 4*16-bit) at a specified address. */
|
||||
pFlash.DataRemaining = 4U;
|
||||
}
|
||||
|
||||
/* Program halfword (16-bit) at a specified address. */
|
||||
FLASH_Program_HalfWord(Address, (uint16_t)Data);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles FLASH interrupt request.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASH_IRQHandler(void)
|
||||
{
|
||||
uint32_t addresstmp = 0U;
|
||||
|
||||
/* Check FLASH operation error flags */
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
|
||||
{
|
||||
/* Return the faulty address */
|
||||
addresstmp = pFlash.Address;
|
||||
/* Reset address */
|
||||
pFlash.Address = 0xFFFFFFFFU;
|
||||
|
||||
/* Save the Error code */
|
||||
FLASH_SetErrorCode();
|
||||
|
||||
/* FLASH error interrupt user callback */
|
||||
HAL_FLASH_OperationErrorCallback(addresstmp);
|
||||
|
||||
/* Stop the procedure ongoing */
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
|
||||
}
|
||||
|
||||
/* Check FLASH End of Operation flag */
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
|
||||
{
|
||||
/* Clear FLASH End of Operation pending bit */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
|
||||
|
||||
/* Process can continue only if no error detected */
|
||||
if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
|
||||
{
|
||||
if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
|
||||
{
|
||||
/* Nb of pages to erased can be decreased */
|
||||
pFlash.DataRemaining--;
|
||||
|
||||
/* Check if there are still pages to erase */
|
||||
if(pFlash.DataRemaining != 0U)
|
||||
{
|
||||
addresstmp = pFlash.Address;
|
||||
/*Indicate user which sector has been erased */
|
||||
HAL_FLASH_EndOfOperationCallback(addresstmp);
|
||||
|
||||
/*Increment sector number*/
|
||||
addresstmp = pFlash.Address + FLASH_PAGE_SIZE;
|
||||
pFlash.Address = addresstmp;
|
||||
|
||||
/* If the erase operation is completed, disable the PER Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
|
||||
|
||||
FLASH_PageErase(addresstmp);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* No more pages to Erase, user callback can be called. */
|
||||
/* Reset Sector and stop Erase pages procedure */
|
||||
pFlash.Address = addresstmp = 0xFFFFFFFFU;
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
|
||||
/* FLASH EOP interrupt user callback */
|
||||
HAL_FLASH_EndOfOperationCallback(addresstmp);
|
||||
}
|
||||
}
|
||||
else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
|
||||
{
|
||||
/* Operation is completed, disable the MER Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
|
||||
|
||||
/* MassErase ended. Return the selected bank */
|
||||
/* FLASH EOP interrupt user callback */
|
||||
HAL_FLASH_EndOfOperationCallback(0);
|
||||
|
||||
/* Stop Mass Erase procedure*/
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Nb of 16-bit data to program can be decreased */
|
||||
pFlash.DataRemaining--;
|
||||
|
||||
/* Check if there are still 16-bit data to program */
|
||||
if(pFlash.DataRemaining != 0U)
|
||||
{
|
||||
/* Increment address to 16-bit */
|
||||
pFlash.Address += 2;
|
||||
addresstmp = pFlash.Address;
|
||||
|
||||
/* Shift to have next 16-bit data */
|
||||
pFlash.Data = (pFlash.Data >> 16U);
|
||||
|
||||
/* Operation is completed, disable the PG Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
|
||||
|
||||
/*Program halfword (16-bit) at a specified address.*/
|
||||
FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Program ended. Return the selected address */
|
||||
/* FLASH EOP interrupt user callback */
|
||||
if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD)
|
||||
{
|
||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address);
|
||||
}
|
||||
else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD)
|
||||
{
|
||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U);
|
||||
}
|
||||
else
|
||||
{
|
||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U);
|
||||
}
|
||||
|
||||
/* Reset Address and stop Program procedure */
|
||||
pFlash.Address = 0xFFFFFFFFU;
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
|
||||
{
|
||||
/* Operation is completed, disable the PG, PER and MER Bits */
|
||||
CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER));
|
||||
|
||||
/* Disable End of FLASH Operation and Error source interrupts */
|
||||
__HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief FLASH end of operation interrupt callback
|
||||
* @param ReturnValue The value saved in this parameter depends on the ongoing procedure
|
||||
* - Mass Erase: No return value expected
|
||||
* - Pages Erase: Address of the page which has been erased
|
||||
* (if 0xFFFFFFFF, it means that all the selected pages have been erased)
|
||||
* - Program: Address which was selected for data program
|
||||
* @retval none
|
||||
*/
|
||||
__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(ReturnValue);
|
||||
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief FLASH operation error interrupt callback
|
||||
* @param ReturnValue The value saved in this parameter depends on the ongoing procedure
|
||||
* - Mass Erase: No return value expected
|
||||
* - Pages Erase: Address of the page which returned an error
|
||||
* - Program: Address which was selected for data program
|
||||
* @retval none
|
||||
*/
|
||||
__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(ReturnValue);
|
||||
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_FLASH_OperationErrorCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the FLASH
|
||||
memory operations.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Unlock the FLASH control register access
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
|
||||
{
|
||||
/* Authorize the FLASH Registers access */
|
||||
WRITE_REG(FLASH->KEYR, FLASH_KEY1);
|
||||
WRITE_REG(FLASH->KEYR, FLASH_KEY2);
|
||||
|
||||
/* Verify Flash is unlocked */
|
||||
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Locks the FLASH control register access
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Lock(void)
|
||||
{
|
||||
/* Set the LOCK Bit to lock the FLASH Registers access */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_LOCK);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unlock the FLASH Option Control Registers access.
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
|
||||
{
|
||||
if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE))
|
||||
{
|
||||
/* Authorizes the Option Byte register programming */
|
||||
WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
|
||||
WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Lock the FLASH Option Control Registers access.
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
|
||||
{
|
||||
/* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Launch the option byte loading.
|
||||
* @note This function will reset automatically the MCU.
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
|
||||
{
|
||||
/* Set the OBL_Launch bit to launch the option byte loading */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
return(FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions
|
||||
* @brief Peripheral errors functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Errors functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection permit to get in run-time errors of the FLASH peripheral.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get the specific FLASH error flag.
|
||||
* @retval FLASH_ErrorCode The returned value can be:
|
||||
* @ref FLASH_Error_Codes
|
||||
*/
|
||||
uint32_t HAL_FLASH_GetError(void)
|
||||
{
|
||||
return pFlash.ErrorCode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Program a half-word (16-bit) at a specified address.
|
||||
* @param Address specify the address to be programmed.
|
||||
* @param Data specify the data to be programmed.
|
||||
* @retval None
|
||||
*/
|
||||
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
|
||||
{
|
||||
/* Clean the error context */
|
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
|
||||
/* Proceed to program the new data */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_PG);
|
||||
|
||||
/* Write data in the address */
|
||||
*(__IO uint16_t*)Address = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Wait for a FLASH operation to complete.
|
||||
* @param Timeout maximum flash operation timeout
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
|
||||
{
|
||||
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
|
||||
Even if the FLASH operation fails, the BUSY flag will be reset and an error
|
||||
flag will be set */
|
||||
|
||||
uint32_t tickstart = HAL_GetTick();
|
||||
|
||||
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
|
||||
{
|
||||
if (Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Check FLASH End of Operation flag */
|
||||
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
|
||||
{
|
||||
/* Clear FLASH End of Operation pending bit */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
|
||||
}
|
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
|
||||
{
|
||||
/*Save the error code*/
|
||||
FLASH_SetErrorCode();
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* There is no error flag set */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Set the specific FLASH error flag.
|
||||
* @retval None
|
||||
*/
|
||||
static void FLASH_SetErrorCode(void)
|
||||
{
|
||||
uint32_t flags = 0U;
|
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
|
||||
flags |= FLASH_FLAG_WRPERR;
|
||||
}
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;
|
||||
flags |= FLASH_FLAG_PGERR;
|
||||
}
|
||||
/* Clear FLASH error pending bits */
|
||||
__HAL_FLASH_CLEAR_FLAG(flags);
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
981
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c
Normal file
981
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c
Normal file
@@ -0,0 +1,981 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_flash_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief Extended FLASH HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the FLASH peripheral:
|
||||
* + Extended Initialization/de-initialization functions
|
||||
* + Extended I/O operation functions
|
||||
* + Extended Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Flash peripheral extended features #####
|
||||
==============================================================================
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..] This driver provides functions to configure and program the FLASH memory
|
||||
of all STM32F0xxx devices. It includes
|
||||
|
||||
(++) Set/Reset the write protection
|
||||
(++) Program the user Option Bytes
|
||||
(++) Get the Read protection Level
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
/** @addtogroup FLASH_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/* Variables used for Erase pages under interruption*/
|
||||
extern FLASH_ProcessTypeDef pFlash;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx FLASHEx
|
||||
* @brief FLASH HAL Extension module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_POSITION_IWDGSW_BIT 8U
|
||||
#define FLASH_POSITION_OB_USERDATA0_BIT 16U
|
||||
#define FLASH_POSITION_OB_USERDATA1_BIT 24U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
|
||||
* @{
|
||||
*/
|
||||
/* Erase operations */
|
||||
static void FLASH_MassErase(void);
|
||||
void FLASH_PageErase(uint32_t PageAddress);
|
||||
|
||||
/* Option bytes control */
|
||||
static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage);
|
||||
static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage);
|
||||
static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel);
|
||||
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig);
|
||||
static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data);
|
||||
static uint32_t FLASH_OB_GetWRP(void);
|
||||
static uint32_t FLASH_OB_GetRDP(void);
|
||||
static uint8_t FLASH_OB_GetUser(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ---------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions
|
||||
* @brief FLASH Memory Erasing functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### FLASH Erasing Programming functions #####
|
||||
==============================================================================
|
||||
|
||||
[..] The FLASH Memory Erasing functions, includes the following functions:
|
||||
(+) HAL_FLASHEx_Erase: return only when erase has been done
|
||||
(+) HAL_FLASHEx_Erase_IT: end of erase is done when HAL_FLASH_EndOfOperationCallback
|
||||
is called with parameter 0xFFFFFFFF
|
||||
|
||||
[..] Any operation of erase should follow these steps:
|
||||
(#) Call the HAL_FLASH_Unlock() function to enable the flash control register and
|
||||
program memory access.
|
||||
(#) Call the desired function to erase page.
|
||||
(#) Call the HAL_FLASH_Lock() to disable the flash program memory access
|
||||
(recommended to protect the FLASH memory against possible unwanted operation).
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Perform a mass erase or erase the specified FLASH memory pages
|
||||
* @note To correctly run this function, the @ref HAL_FLASH_Unlock() function
|
||||
* must be called before.
|
||||
* Call the @ref HAL_FLASH_Lock() to disable the flash memory access
|
||||
* (recommended to protect the FLASH memory against possible unwanted operation)
|
||||
* @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
|
||||
* contains the configuration information for the erasing.
|
||||
*
|
||||
* @param[out] PageError pointer to variable that
|
||||
* contains the configuration information on faulty page in case of error
|
||||
* (0xFFFFFFFF means that all the pages have been correctly erased)
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_ERROR;
|
||||
uint32_t address = 0U;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
|
||||
|
||||
if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
|
||||
{
|
||||
/* Mass Erase requested for Bank1 */
|
||||
/* Wait for last operation to be completed */
|
||||
if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
|
||||
{
|
||||
/*Mass erase to be done*/
|
||||
FLASH_MassErase();
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* If the erase operation is completed, disable the MER Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Page Erase is requested */
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
|
||||
assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));
|
||||
|
||||
/* Page Erase requested on address located on bank1 */
|
||||
/* Wait for last operation to be completed */
|
||||
if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
|
||||
{
|
||||
/*Initialization of PageError variable*/
|
||||
*PageError = 0xFFFFFFFFU;
|
||||
|
||||
/* Erase page by page to be done*/
|
||||
for(address = pEraseInit->PageAddress;
|
||||
address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);
|
||||
address += FLASH_PAGE_SIZE)
|
||||
{
|
||||
FLASH_PageErase(address);
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* If the erase operation is completed, disable the PER Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
|
||||
|
||||
if (status != HAL_OK)
|
||||
{
|
||||
/* In case of error, stop erase procedure and return the faulty address */
|
||||
*PageError = address;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled
|
||||
* @note To correctly run this function, the @ref HAL_FLASH_Unlock() function
|
||||
* must be called before.
|
||||
* Call the @ref HAL_FLASH_Lock() to disable the flash memory access
|
||||
* (recommended to protect the FLASH memory against possible unwanted operation)
|
||||
* @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
|
||||
* contains the configuration information for the erasing.
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* If procedure already ongoing, reject the next one */
|
||||
if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
|
||||
|
||||
/* Enable End of FLASH Operation and Error source interrupts */
|
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
|
||||
|
||||
if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
|
||||
{
|
||||
/*Mass erase to be done*/
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
|
||||
FLASH_MassErase();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Erase by page to be done*/
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
|
||||
assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));
|
||||
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE;
|
||||
pFlash.DataRemaining = pEraseInit->NbPages;
|
||||
pFlash.Address = pEraseInit->PageAddress;
|
||||
|
||||
/*Erase 1st page and wait for IT*/
|
||||
FLASH_PageErase(pEraseInit->PageAddress);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions
|
||||
* @brief Option Bytes Programming functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Option Bytes Programming functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the FLASH
|
||||
option bytes operations.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Erases the FLASH option bytes.
|
||||
* @note This functions erases all option bytes except the Read protection (RDP).
|
||||
* The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
|
||||
* The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
|
||||
* The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
|
||||
* (system reset will occur)
|
||||
* @retval HAL status
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OBErase(void)
|
||||
{
|
||||
uint8_t rdptmp = OB_RDP_LEVEL_0;
|
||||
HAL_StatusTypeDef status = HAL_ERROR;
|
||||
|
||||
/* Get the actual read protection Option Byte value */
|
||||
rdptmp = FLASH_OB_GetRDP();
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Clean the error context */
|
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
|
||||
/* If the previous operation is completed, proceed to erase the option bytes */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OPTER);
|
||||
SET_BIT(FLASH->CR, FLASH_CR_STRT);
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* If the erase operation is completed, disable the OPTER Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Restore the last read protection Option Byte value */
|
||||
status = FLASH_OB_RDP_LevelConfig(rdptmp);
|
||||
}
|
||||
}
|
||||
|
||||
/* Return the erase status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Program option bytes
|
||||
* @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
|
||||
* The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
|
||||
* The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
|
||||
* (system reset will occur)
|
||||
*
|
||||
* @param pOBInit pointer to an FLASH_OBInitStruct structure that
|
||||
* contains the configuration information for the programming.
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_ERROR;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
|
||||
|
||||
/* Write protection configuration */
|
||||
if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
|
||||
{
|
||||
assert_param(IS_WRPSTATE(pOBInit->WRPState));
|
||||
if (pOBInit->WRPState == OB_WRPSTATE_ENABLE)
|
||||
{
|
||||
/* Enable of Write protection on the selected page */
|
||||
status = FLASH_OB_EnableWRP(pOBInit->WRPPage);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable of Write protection on the selected page */
|
||||
status = FLASH_OB_DisableWRP(pOBInit->WRPPage);
|
||||
}
|
||||
if (status != HAL_OK)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
return status;
|
||||
}
|
||||
}
|
||||
|
||||
/* Read protection configuration */
|
||||
if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
|
||||
{
|
||||
status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);
|
||||
if (status != HAL_OK)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
return status;
|
||||
}
|
||||
}
|
||||
|
||||
/* USER configuration */
|
||||
if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
|
||||
{
|
||||
status = FLASH_OB_UserConfig(pOBInit->USERConfig);
|
||||
if (status != HAL_OK)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
return status;
|
||||
}
|
||||
}
|
||||
|
||||
/* DATA configuration*/
|
||||
if((pOBInit->OptionType & OPTIONBYTE_DATA) == OPTIONBYTE_DATA)
|
||||
{
|
||||
status = FLASH_OB_ProgramData(pOBInit->DATAAddress, pOBInit->DATAData);
|
||||
if (status != HAL_OK)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
return status;
|
||||
}
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the Option byte configuration
|
||||
* @param pOBInit pointer to an FLASH_OBInitStruct structure that
|
||||
* contains the configuration information for the programming.
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
|
||||
{
|
||||
pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER;
|
||||
|
||||
/*Get WRP*/
|
||||
pOBInit->WRPPage = FLASH_OB_GetWRP();
|
||||
|
||||
/*Get RDP Level*/
|
||||
pOBInit->RDPLevel = FLASH_OB_GetRDP();
|
||||
|
||||
/*Get USER*/
|
||||
pOBInit->USERConfig = FLASH_OB_GetUser();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the Option byte user data
|
||||
* @param DATAAdress Address of the option byte DATA
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref OB_DATA_ADDRESS_DATA0
|
||||
* @arg @ref OB_DATA_ADDRESS_DATA1
|
||||
* @retval Value programmed in USER data
|
||||
*/
|
||||
uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress)
|
||||
{
|
||||
uint32_t value = 0U;
|
||||
|
||||
if (DATAAdress == OB_DATA_ADDRESS_DATA0)
|
||||
{
|
||||
/* Get value programmed in OB USER Data0 */
|
||||
value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA0) >> FLASH_POSITION_OB_USERDATA0_BIT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Get value programmed in OB USER Data1 */
|
||||
value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA1) >> FLASH_POSITION_OB_USERDATA1_BIT;
|
||||
}
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Full erase of FLASH memory Bank
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
static void FLASH_MassErase(void)
|
||||
{
|
||||
/* Clean the error context */
|
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
|
||||
/* Only bank1 will be erased*/
|
||||
SET_BIT(FLASH->CR, FLASH_CR_MER);
|
||||
SET_BIT(FLASH->CR, FLASH_CR_STRT);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the write protection of the desired pages
|
||||
* @note An option byte erase is done automatically in this function.
|
||||
* @note When the memory read protection level is selected (RDP level = 1),
|
||||
* it is not possible to program or erase the flash page i if
|
||||
* debug features are connected or boot code is executed in RAM, even if nWRPi = 1
|
||||
*
|
||||
* @param WriteProtectPage specifies the page(s) to be write protected.
|
||||
* The value of this parameter depend on device used within the same series
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint16_t WRP0_Data = 0xFFFFU;
|
||||
#if defined(OB_WRP1_WRP1)
|
||||
uint16_t WRP1_Data = 0xFFFFU;
|
||||
#endif /* OB_WRP1_WRP1 */
|
||||
#if defined(OB_WRP2_WRP2)
|
||||
uint16_t WRP2_Data = 0xFFFFU;
|
||||
#endif /* OB_WRP2_WRP2 */
|
||||
#if defined(OB_WRP3_WRP3)
|
||||
uint16_t WRP3_Data = 0xFFFFU;
|
||||
#endif /* OB_WRP3_WRP3 */
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_WRP(WriteProtectPage));
|
||||
|
||||
/* Get current write protected pages and the new pages to be protected ******/
|
||||
WriteProtectPage = (uint32_t)(~((~FLASH_OB_GetWRP()) | WriteProtectPage));
|
||||
|
||||
#if defined(OB_WRP_PAGES0TO15MASK)
|
||||
WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
|
||||
#elif defined(OB_WRP_PAGES0TO31MASK)
|
||||
WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK);
|
||||
#endif /* OB_WRP_PAGES0TO31MASK */
|
||||
|
||||
#if defined(OB_WRP_PAGES16TO31MASK)
|
||||
WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U);
|
||||
#elif defined(OB_WRP_PAGES32TO63MASK)
|
||||
WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U);
|
||||
#endif /* OB_WRP_PAGES32TO63MASK */
|
||||
|
||||
#if defined(OB_WRP_PAGES32TO47MASK)
|
||||
WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U);
|
||||
#endif /* OB_WRP_PAGES32TO47MASK */
|
||||
|
||||
#if defined(OB_WRP_PAGES48TO63MASK)
|
||||
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO63MASK) >> 24U);
|
||||
#elif defined(OB_WRP_PAGES48TO127MASK)
|
||||
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U);
|
||||
#endif /* OB_WRP_PAGES48TO63MASK */
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Clean the error context */
|
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
|
||||
/* To be able to write again option byte, need to perform a option byte erase */
|
||||
status = HAL_FLASHEx_OBErase();
|
||||
if (status == HAL_OK)
|
||||
{
|
||||
/* Enable write protection */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
|
||||
#if defined(OB_WRP0_WRP0)
|
||||
if(WRP0_Data != 0xFFU)
|
||||
{
|
||||
OB->WRP0 &= WRP0_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
#endif /* OB_WRP0_WRP0 */
|
||||
|
||||
#if defined(OB_WRP1_WRP1)
|
||||
if((status == HAL_OK) && (WRP1_Data != 0xFFU))
|
||||
{
|
||||
OB->WRP1 &= WRP1_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
#endif /* OB_WRP1_WRP1 */
|
||||
|
||||
#if defined(OB_WRP2_WRP2)
|
||||
if((status == HAL_OK) && (WRP2_Data != 0xFFU))
|
||||
{
|
||||
OB->WRP2 &= WRP2_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
#endif /* OB_WRP2_WRP2 */
|
||||
|
||||
#if defined(OB_WRP3_WRP3)
|
||||
if((status == HAL_OK) && (WRP3_Data != 0xFFU))
|
||||
{
|
||||
OB->WRP3 &= WRP3_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
#endif /* OB_WRP3_WRP3 */
|
||||
|
||||
/* if the program operation is completed, disable the OPTPG Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the write protection of the desired pages
|
||||
* @note An option byte erase is done automatically in this function.
|
||||
* @note When the memory read protection level is selected (RDP level = 1),
|
||||
* it is not possible to program or erase the flash page i if
|
||||
* debug features are connected or boot code is executed in RAM, even if nWRPi = 1
|
||||
*
|
||||
* @param WriteProtectPage specifies the page(s) to be write unprotected.
|
||||
* The value of this parameter depend on device used within the same series
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint16_t WRP0_Data = 0xFFFFU;
|
||||
#if defined(OB_WRP1_WRP1)
|
||||
uint16_t WRP1_Data = 0xFFFFU;
|
||||
#endif /* OB_WRP1_WRP1 */
|
||||
#if defined(OB_WRP2_WRP2)
|
||||
uint16_t WRP2_Data = 0xFFFFU;
|
||||
#endif /* OB_WRP2_WRP2 */
|
||||
#if defined(OB_WRP3_WRP3)
|
||||
uint16_t WRP3_Data = 0xFFFFU;
|
||||
#endif /* OB_WRP3_WRP3 */
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_WRP(WriteProtectPage));
|
||||
|
||||
/* Get current write protected pages and the new pages to be unprotected ******/
|
||||
WriteProtectPage = (FLASH_OB_GetWRP() | WriteProtectPage);
|
||||
|
||||
#if defined(OB_WRP_PAGES0TO15MASK)
|
||||
WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
|
||||
#elif defined(OB_WRP_PAGES0TO31MASK)
|
||||
WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK);
|
||||
#endif /* OB_WRP_PAGES0TO31MASK */
|
||||
|
||||
#if defined(OB_WRP_PAGES16TO31MASK)
|
||||
WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U);
|
||||
#elif defined(OB_WRP_PAGES32TO63MASK)
|
||||
WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U);
|
||||
#endif /* OB_WRP_PAGES32TO63MASK */
|
||||
|
||||
#if defined(OB_WRP_PAGES32TO47MASK)
|
||||
WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U);
|
||||
#endif /* OB_WRP_PAGES32TO47MASK */
|
||||
|
||||
#if defined(OB_WRP_PAGES48TO63MASK)
|
||||
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO63MASK) >> 24U);
|
||||
#elif defined(OB_WRP_PAGES48TO127MASK)
|
||||
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U);
|
||||
#endif /* OB_WRP_PAGES48TO63MASK */
|
||||
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Clean the error context */
|
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
|
||||
/* To be able to write again option byte, need to perform a option byte erase */
|
||||
status = HAL_FLASHEx_OBErase();
|
||||
if (status == HAL_OK)
|
||||
{
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
|
||||
#if defined(OB_WRP0_WRP0)
|
||||
if(WRP0_Data != 0xFFU)
|
||||
{
|
||||
OB->WRP0 &= WRP0_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
#endif /* OB_WRP0_WRP0 */
|
||||
|
||||
#if defined(OB_WRP1_WRP1)
|
||||
if((status == HAL_OK) && (WRP1_Data != 0xFFU))
|
||||
{
|
||||
OB->WRP1 &= WRP1_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
#endif /* OB_WRP1_WRP1 */
|
||||
|
||||
#if defined(OB_WRP2_WRP2)
|
||||
if((status == HAL_OK) && (WRP2_Data != 0xFFU))
|
||||
{
|
||||
OB->WRP2 &= WRP2_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
#endif /* OB_WRP2_WRP2 */
|
||||
|
||||
#if defined(OB_WRP3_WRP3)
|
||||
if((status == HAL_OK) && (WRP3_Data != 0xFFU))
|
||||
{
|
||||
OB->WRP3 &= WRP3_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
#endif /* OB_WRP3_WRP3 */
|
||||
|
||||
/* if the program operation is completed, disable the OPTPG Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
}
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the read protection level.
|
||||
* @param ReadProtectLevel specifies the read protection level.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref OB_RDP_LEVEL_0 No protection
|
||||
* @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
|
||||
* @arg @ref OB_RDP_LEVEL_2 Full chip protection
|
||||
* @note Warning: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel));
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Clean the error context */
|
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
|
||||
/* If the previous operation is completed, proceed to erase the option bytes */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OPTER);
|
||||
SET_BIT(FLASH->CR, FLASH_CR_STRT);
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* If the erase operation is completed, disable the OPTER Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Enable the Option Bytes Programming operation */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
|
||||
WRITE_REG(OB->RDP, ReadProtectLevel);
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* if the program operation is completed, disable the OPTPG Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Program the FLASH User Option Byte.
|
||||
* @note Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
|
||||
* @param UserConfig The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nBOOT1(Bit4),
|
||||
* VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6).
|
||||
* For few devices, following option bytes are available: nBOOT0(Bit3) & BOOT_SEL(Bit7).
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_IWDG_SOURCE((UserConfig&OB_IWDG_SW)));
|
||||
assert_param(IS_OB_STOP_SOURCE((UserConfig&OB_STOP_NO_RST)));
|
||||
assert_param(IS_OB_STDBY_SOURCE((UserConfig&OB_STDBY_NO_RST)));
|
||||
assert_param(IS_OB_BOOT1((UserConfig&OB_BOOT1_SET)));
|
||||
assert_param(IS_OB_VDDA_ANALOG((UserConfig&OB_VDDA_ANALOG_ON)));
|
||||
assert_param(IS_OB_SRAM_PARITY((UserConfig&OB_SRAM_PARITY_RESET)));
|
||||
#if defined(FLASH_OBR_BOOT_SEL)
|
||||
assert_param(IS_OB_BOOT_SEL((UserConfig&OB_BOOT_SEL_SET)));
|
||||
assert_param(IS_OB_BOOT0((UserConfig&OB_BOOT0_SET)));
|
||||
#endif /* FLASH_OBR_BOOT_SEL */
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Clean the error context */
|
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
|
||||
/* Enable the Option Bytes Programming operation */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
|
||||
#if defined(FLASH_OBR_BOOT_SEL)
|
||||
OB->USER = UserConfig;
|
||||
#else
|
||||
OB->USER = (UserConfig | 0x88U);
|
||||
#endif
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* if the program operation is completed, disable the OPTPG Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Programs a half word at a specified Option Byte Data address.
|
||||
* @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
|
||||
* The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
|
||||
* The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
|
||||
* (system reset will occur)
|
||||
* Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
|
||||
* @param Address specifies the address to be programmed.
|
||||
* This parameter can be 0x1FFFF804 or 0x1FFFF806.
|
||||
* @param Data specifies the data to be programmed.
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_ERROR;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_DATA_ADDRESS(Address));
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Clean the error context */
|
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
|
||||
/* Enables the Option Bytes Programming operation */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
*(__IO uint16_t*)Address = Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* If the program operation is completed, disable the OPTPG Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
}
|
||||
/* Return the Option Byte Data Program Status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the FLASH Write Protection Option Bytes value.
|
||||
* @retval The FLASH Write Protection Option Bytes value
|
||||
*/
|
||||
static uint32_t FLASH_OB_GetWRP(void)
|
||||
{
|
||||
/* Return the FLASH write protection Register value */
|
||||
return (uint32_t)(READ_REG(FLASH->WRPR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the FLASH Read Protection level.
|
||||
* @retval FLASH RDP level
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref OB_RDP_LEVEL_0 No protection
|
||||
* @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
|
||||
* @arg @ref OB_RDP_LEVEL_2 Full chip protection
|
||||
*/
|
||||
static uint32_t FLASH_OB_GetRDP(void)
|
||||
{
|
||||
uint32_t tmp_reg;
|
||||
|
||||
/* Read RDP level bits */
|
||||
tmp_reg = READ_BIT(FLASH->OBR, (FLASH_OBR_RDPRT1 | FLASH_OBR_RDPRT2));
|
||||
|
||||
if (tmp_reg == 0U)
|
||||
{
|
||||
return OB_RDP_LEVEL_0;
|
||||
}
|
||||
else if ((tmp_reg & FLASH_OBR_RDPRT2) == FLASH_OBR_RDPRT2)
|
||||
{
|
||||
return OB_RDP_LEVEL_2;
|
||||
}
|
||||
else
|
||||
{
|
||||
return OB_RDP_LEVEL_1;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the FLASH User Option Byte value.
|
||||
* @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nBOOT1(Bit4),
|
||||
* VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6).
|
||||
* For few devices, following option bytes are available: nBOOT0(Bit3) & BOOT_SEL(Bit7).
|
||||
*/
|
||||
static uint8_t FLASH_OB_GetUser(void)
|
||||
{
|
||||
/* Return the User Option Byte */
|
||||
return (uint8_t)((READ_REG(FLASH->OBR) & FLASH_OBR_USER) >> FLASH_POSITION_IWDGSW_BIT);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Erase the specified FLASH memory page
|
||||
* @param PageAddress FLASH page to erase
|
||||
* The value of this parameter depend on device used within the same series
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FLASH_PageErase(uint32_t PageAddress)
|
||||
{
|
||||
/* Clean the error context */
|
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
|
||||
/* Proceed to erase the page */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_PER);
|
||||
WRITE_REG(FLASH->AR, PageAddress);
|
||||
SET_BIT(FLASH->CR, FLASH_CR_STRT);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
539
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c
Normal file
539
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c
Normal file
@@ -0,0 +1,539 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_gpio.c
|
||||
* @author MCD Application Team
|
||||
* @brief GPIO HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + IO operation functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### GPIO Peripheral features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
|
||||
configured by software in several modes:
|
||||
(++) Input mode
|
||||
(++) Analog mode
|
||||
(++) Output mode
|
||||
(++) Alternate function mode
|
||||
(++) External interrupt/event lines
|
||||
|
||||
(+) During and just after reset, the alternate functions and external interrupt
|
||||
lines are not active and the I/O ports are configured in input floating mode.
|
||||
|
||||
(+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
|
||||
activated or not.
|
||||
|
||||
(+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
|
||||
type and the IO speed can be selected depending on the VDD value.
|
||||
|
||||
(+) The microcontroller IO pins are connected to onboard peripherals/modules through a
|
||||
multiplexer that allows only one peripheral alternate function (AF) connected
|
||||
to an IO pin at a time. In this way, there can be no conflict between peripherals
|
||||
sharing the same IO pin.
|
||||
|
||||
(+) All ports have external interrupt/event capability. To use external interrupt
|
||||
lines, the port must be configured in input mode. All available GPIO pins are
|
||||
connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
|
||||
|
||||
(+) The external interrupt/event controller consists of up to 28 edge detectors
|
||||
(16 lines are connected to GPIO) for generating event/interrupt requests (each
|
||||
input line can be independently configured to select the type (interrupt or event)
|
||||
and the corresponding trigger event (rising or falling or both). Each line can
|
||||
also be masked independently.
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) Enable the GPIO AHB clock using the following function : __HAL_RCC_GPIOx_CLK_ENABLE().
|
||||
|
||||
(#) Configure the GPIO pin(s) using HAL_GPIO_Init().
|
||||
(++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
|
||||
(++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
|
||||
structure.
|
||||
(++) In case of Output or alternate function mode selection: the speed is
|
||||
configured through "Speed" member from GPIO_InitTypeDef structure.
|
||||
(++) In alternate mode is selection, the alternate function connected to the IO
|
||||
is configured through "Alternate" member from GPIO_InitTypeDef structure.
|
||||
(++) Analog mode is required when a pin is to be used as ADC channel
|
||||
or DAC output.
|
||||
(++) In case of external interrupt/event selection the "Mode" member from
|
||||
GPIO_InitTypeDef structure select the type (interrupt or event) and
|
||||
the corresponding trigger event (rising or falling or both).
|
||||
|
||||
(#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
|
||||
mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
|
||||
HAL_NVIC_EnableIRQ().
|
||||
|
||||
(#) HAL_GPIO_DeInit allows to set register values to their reset value. It's also
|
||||
recommended to use it to unconfigure pin which was used as an external interrupt
|
||||
or in event mode. That's the only way to reset corresponding bit in EXTI & SYSCFG
|
||||
registers.
|
||||
|
||||
(#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
|
||||
|
||||
(#) To set/reset the level of a pin configured in output mode use
|
||||
HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
|
||||
|
||||
(#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
|
||||
|
||||
(#) During and just after reset, the alternate functions are not
|
||||
active and the GPIO pins are configured in input floating mode (except JTAG
|
||||
pins).
|
||||
|
||||
(#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
|
||||
(PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
|
||||
priority over the GPIO function.
|
||||
|
||||
(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
|
||||
general purpose PF0 and PF1, respectively, when the HSE oscillator is off.
|
||||
The HSE has priority over the GPIO function.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO GPIO
|
||||
* @brief GPIO HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** MISRA C:2012 deviation rule has been granted for following rules:
|
||||
* Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..]
|
||||
* which may be out of array bounds [..,UNKNOWN] in following APIs:
|
||||
* HAL_GPIO_Init
|
||||
* HAL_GPIO_DeInit
|
||||
*/
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/** @addtogroup GPIO_Private_Constants GPIO Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_NUMBER 16U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
|
||||
* @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family
|
||||
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
|
||||
* the configuration information for the specified GPIO peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
||||
{
|
||||
uint32_t position = 0x00u;
|
||||
uint32_t iocurrent;
|
||||
uint32_t temp;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
||||
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
||||
|
||||
/* Configure the port pins */
|
||||
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
||||
{
|
||||
/* Get current io position */
|
||||
iocurrent = (GPIO_Init->Pin) & (1uL << position);
|
||||
|
||||
if (iocurrent != 0x00u)
|
||||
{
|
||||
/*--------------------- GPIO Mode Configuration ------------------------*/
|
||||
/* In case of Output or Alternate function mode selection */
|
||||
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
|
||||
((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
|
||||
{
|
||||
/* Check the Speed parameter */
|
||||
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
||||
/* Configure the IO Speed */
|
||||
temp = GPIOx->OSPEEDR;
|
||||
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u));
|
||||
temp |= (GPIO_Init->Speed << (position * 2u));
|
||||
GPIOx->OSPEEDR = temp;
|
||||
|
||||
/* Configure the IO Output Type */
|
||||
temp = GPIOx->OTYPER;
|
||||
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
|
||||
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
|
||||
GPIOx->OTYPER = temp;
|
||||
}
|
||||
|
||||
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
|
||||
{
|
||||
/* Check the Pull parameter */
|
||||
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
||||
|
||||
/* Activate the Pull-up or Pull down resistor for the current IO */
|
||||
temp = GPIOx->PUPDR;
|
||||
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u));
|
||||
temp |= ((GPIO_Init->Pull) << (position * 2u));
|
||||
GPIOx->PUPDR = temp;
|
||||
}
|
||||
|
||||
/* In case of Alternate function mode selection */
|
||||
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
||||
{
|
||||
/* Check the Alternate function parameters */
|
||||
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
|
||||
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
||||
|
||||
/* Configure Alternate function mapped with the current IO */
|
||||
temp = GPIOx->AFR[position >> 3u];
|
||||
temp &= ~(0xFu << ((position & 0x07u) * 4u));
|
||||
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
|
||||
GPIOx->AFR[position >> 3u] = temp;
|
||||
}
|
||||
|
||||
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
||||
temp = GPIOx->MODER;
|
||||
temp &= ~(GPIO_MODER_MODER0 << (position * 2u));
|
||||
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
|
||||
GPIOx->MODER = temp;
|
||||
|
||||
/*--------------------- EXTI Mode Configuration ------------------------*/
|
||||
/* Configure the External Interrupt or event for the current IO */
|
||||
if((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
|
||||
{
|
||||
/* Enable SYSCFG Clock */
|
||||
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||||
|
||||
temp = SYSCFG->EXTICR[position >> 2u];
|
||||
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
|
||||
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
|
||||
SYSCFG->EXTICR[position >> 2u] = temp;
|
||||
|
||||
/* Clear Rising Falling edge configuration */
|
||||
temp = EXTI->RTSR;
|
||||
temp &= ~(iocurrent);
|
||||
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->RTSR = temp;
|
||||
|
||||
temp = EXTI->FTSR;
|
||||
temp &= ~(iocurrent);
|
||||
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->FTSR = temp;
|
||||
|
||||
/* Clear EXTI line configuration */
|
||||
temp = EXTI->EMR;
|
||||
temp &= ~(iocurrent);
|
||||
if((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->EMR = temp;
|
||||
|
||||
temp = EXTI->IMR;
|
||||
temp &= ~(iocurrent);
|
||||
if((GPIO_Init->Mode & EXTI_IT) != 0x00u)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->IMR = temp;
|
||||
}
|
||||
}
|
||||
|
||||
position++;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief De-initialize the GPIOx peripheral registers to their default reset values.
|
||||
* @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family
|
||||
* @param GPIO_Pin specifies the port bit to be written.
|
||||
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
|
||||
{
|
||||
uint32_t position = 0x00u;
|
||||
uint32_t iocurrent;
|
||||
uint32_t tmp;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
/* Configure the port pins */
|
||||
while ((GPIO_Pin >> position) != 0x00u)
|
||||
{
|
||||
/* Get current io position */
|
||||
iocurrent = (GPIO_Pin) & (1uL << position);
|
||||
|
||||
if (iocurrent != 0x00u)
|
||||
{
|
||||
/*------------------------- EXTI Mode Configuration --------------------*/
|
||||
/* Clear the External Interrupt or Event for the current IO */
|
||||
|
||||
tmp = SYSCFG->EXTICR[position >> 2u];
|
||||
tmp &= (0x0FuL << (4u * (position & 0x03u)));
|
||||
if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))))
|
||||
{
|
||||
/* Clear EXTI line configuration */
|
||||
EXTI->IMR &= ~((uint32_t)iocurrent);
|
||||
EXTI->EMR &= ~((uint32_t)iocurrent);
|
||||
|
||||
/* Clear Rising Falling edge configuration */
|
||||
EXTI->FTSR &= ~((uint32_t)iocurrent);
|
||||
EXTI->RTSR &= ~((uint32_t)iocurrent);
|
||||
|
||||
/* Configure the External Interrupt or event for the current IO */
|
||||
tmp = 0x0FuL << (4u * (position & 0x03u));
|
||||
SYSCFG->EXTICR[position >> 2u] &= ~tmp;
|
||||
}
|
||||
|
||||
/*------------------------- GPIO Mode Configuration --------------------*/
|
||||
/* Configure IO Direction in Input Floating Mode */
|
||||
GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2u));
|
||||
|
||||
/* Configure the default Alternate Function in current IO */
|
||||
GPIOx->AFR[position >> 3u] &= ~(0xFu << ((uint32_t)(position & 0x07u) * 4u)) ;
|
||||
|
||||
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
|
||||
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u));
|
||||
|
||||
/* Configure the default value IO Output Type */
|
||||
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
|
||||
|
||||
/* Configure the default value for IO Speed */
|
||||
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u));
|
||||
|
||||
}
|
||||
|
||||
position++;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
|
||||
* @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Read the specified input port pin.
|
||||
* @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family
|
||||
* @param GPIO_Pin specifies the port bit to read.
|
||||
* This parameter can be GPIO_PIN_x where x can be (0..15).
|
||||
* @retval The input port pin value.
|
||||
*/
|
||||
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
GPIO_PinState bitstatus;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
|
||||
{
|
||||
bitstatus = GPIO_PIN_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = GPIO_PIN_RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set or clear the selected data port bit.
|
||||
* @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify
|
||||
* accesses. In this way, there is no risk of an IRQ occurring between
|
||||
* the read and the modify access.
|
||||
*
|
||||
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32F0 family
|
||||
* @param GPIO_Pin specifies the port bit to be written.
|
||||
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
|
||||
* @param PinState specifies the value to be written to the selected bit.
|
||||
* This parameter can be one of the GPIO_PinState enum values:
|
||||
* @arg GPIO_PIN_RESET: to clear the port pin
|
||||
* @arg GPIO_PIN_SET: to set the port pin
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
||||
|
||||
if (PinState != GPIO_PIN_RESET)
|
||||
{
|
||||
GPIOx->BSRR = (uint32_t)GPIO_Pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Toggle the specified GPIO pin.
|
||||
* @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family
|
||||
* @param GPIO_Pin specifies the pin to be toggled.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint32_t odr;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
/* get current Output Data Register value */
|
||||
odr = GPIOx->ODR;
|
||||
|
||||
/* Set selected pins that were at low level, and reset ones that were high */
|
||||
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Locks GPIO Pins configuration registers.
|
||||
* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
|
||||
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
|
||||
* @note The configuration of the locked GPIO pins can no longer be modified
|
||||
* until the next reset.
|
||||
* @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family
|
||||
* @param GPIO_Pin specifies the port bits to be locked.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
__IO uint32_t tmp = GPIO_LCKR_LCKK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
/* Apply lock key write sequence */
|
||||
SET_BIT(tmp, GPIO_Pin);
|
||||
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
|
||||
GPIOx->LCKR = GPIO_Pin;
|
||||
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Read LCKK register. This read is mandatory to complete key lock sequence */
|
||||
tmp = GPIOx->LCKR;
|
||||
|
||||
/* read again in order to confirm lock is active */
|
||||
if((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u)
|
||||
{
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handle EXTI interrupt request.
|
||||
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
|
||||
{
|
||||
/* EXTI line interrupt detected */
|
||||
if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
|
||||
{
|
||||
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
|
||||
HAL_GPIO_EXTI_Callback(GPIO_Pin);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EXTI line detection callback.
|
||||
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(GPIO_Pin);
|
||||
|
||||
/* NOTE: This function should not be modified, when the callback is needed,
|
||||
the HAL_GPIO_EXTI_Callback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
7548
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c
Normal file
7548
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c
Normal file
File diff suppressed because it is too large
Load Diff
362
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c
Normal file
362
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c
Normal file
@@ -0,0 +1,362 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_i2c_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief I2C Extended HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of I2C Extended peripheral:
|
||||
* + Filter Mode Functions
|
||||
* + WakeUp Mode Functions
|
||||
* + FastModePlus Functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### I2C peripheral Extended features #####
|
||||
==============================================================================
|
||||
|
||||
[..] Comparing to other previous devices, the I2C interface for STM32F0xx
|
||||
devices contains the following additional features
|
||||
|
||||
(+) Possibility to disable or enable Analog Noise Filter
|
||||
(+) Use of a configured Digital Noise Filter
|
||||
(+) Disable or enable wakeup from Stop mode(s)
|
||||
(+) Disable or enable Fast Mode Plus
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..] This driver provides functions to configure Noise Filter and Wake Up Feature
|
||||
(#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
|
||||
(#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
|
||||
(#) Configure the enable or disable of I2C Wake Up Mode using the functions :
|
||||
(++) HAL_I2CEx_EnableWakeUp()
|
||||
(++) HAL_I2CEx_DisableWakeUp()
|
||||
(#) Configure the enable or disable of fast mode plus driving capability using the functions :
|
||||
(++) HAL_I2CEx_EnableFastModePlus()
|
||||
(++) HAL_I2CEx_DisableFastModePlus()
|
||||
@endverbatim
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx I2CEx
|
||||
* @brief I2C Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
|
||||
* @brief Filter Mode Functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Filter Mode Functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure Noise Filters
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configure I2C Analog noise filter.
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2Cx peripheral.
|
||||
* @param AnalogFilter New state of the Analog filter.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
||||
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_READY)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_BUSY;
|
||||
|
||||
/* Disable the selected I2C peripheral */
|
||||
__HAL_I2C_DISABLE(hi2c);
|
||||
|
||||
/* Reset I2Cx ANOFF bit */
|
||||
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
|
||||
|
||||
/* Set analog filter bit*/
|
||||
hi2c->Instance->CR1 |= AnalogFilter;
|
||||
|
||||
__HAL_I2C_ENABLE(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure I2C Digital noise filter.
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2Cx peripheral.
|
||||
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
|
||||
{
|
||||
uint32_t tmpreg;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
||||
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_READY)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_BUSY;
|
||||
|
||||
/* Disable the selected I2C peripheral */
|
||||
__HAL_I2C_DISABLE(hi2c);
|
||||
|
||||
/* Get the old register value */
|
||||
tmpreg = hi2c->Instance->CR1;
|
||||
|
||||
/* Reset I2Cx DNF bits [11:8] */
|
||||
tmpreg &= ~(I2C_CR1_DNF);
|
||||
|
||||
/* Set I2Cx DNF coefficient */
|
||||
tmpreg |= DigitalFilter << 8U;
|
||||
|
||||
/* Store the new register value */
|
||||
hi2c->Instance->CR1 = tmpreg;
|
||||
|
||||
__HAL_I2C_ENABLE(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#if defined(I2C_CR1_WUPEN)
|
||||
|
||||
/** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
|
||||
* @brief WakeUp Mode Functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### WakeUp Mode Functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure Wake Up Feature
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable I2C wakeup from Stop mode(s).
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2Cx peripheral.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_READY)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_BUSY;
|
||||
|
||||
/* Disable the selected I2C peripheral */
|
||||
__HAL_I2C_DISABLE(hi2c);
|
||||
|
||||
/* Enable wakeup from stop mode */
|
||||
hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
|
||||
|
||||
__HAL_I2C_ENABLE(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable I2C wakeup from Stop mode(s).
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2Cx peripheral.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_READY)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_BUSY;
|
||||
|
||||
/* Disable the selected I2C peripheral */
|
||||
__HAL_I2C_DISABLE(hi2c);
|
||||
|
||||
/* Enable wakeup from stop mode */
|
||||
hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
|
||||
|
||||
__HAL_I2C_ENABLE(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* I2C_CR1_WUPEN */
|
||||
|
||||
/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
|
||||
* @brief Fast Mode Plus Functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Fast Mode Plus Functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure Fast Mode Plus
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the I2C fast mode plus driving capability.
|
||||
* @param ConfigFastModePlus Selects the pin.
|
||||
* This parameter can be one of the @ref I2CEx_FastModePlus values
|
||||
* @note For I2C1, fast mode plus driving capability can be enabled on all selected
|
||||
* I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
|
||||
* on each one of the following pins PB6, PB7, PB8 and PB9.
|
||||
* @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
|
||||
* can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
|
||||
* @note For all I2C2 pins fast mode plus driving capability can be enabled
|
||||
* only by using I2C_FASTMODEPLUS_I2C2 parameter.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
|
||||
|
||||
/* Enable SYSCFG clock */
|
||||
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||||
|
||||
/* Enable fast mode plus driving capability for selected pin */
|
||||
SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the I2C fast mode plus driving capability.
|
||||
* @param ConfigFastModePlus Selects the pin.
|
||||
* This parameter can be one of the @ref I2CEx_FastModePlus values
|
||||
* @note For I2C1, fast mode plus driving capability can be disabled on all selected
|
||||
* I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
|
||||
* on each one of the following pins PB6, PB7, PB8 and PB9.
|
||||
* @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
|
||||
* can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
|
||||
* @note For all I2C2 pins fast mode plus driving capability can be disabled
|
||||
* only by using I2C_FASTMODEPLUS_I2C2 parameter.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
|
||||
|
||||
/* Enable SYSCFG clock */
|
||||
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||||
|
||||
/* Disable fast mode plus driving capability for selected pin */
|
||||
CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
1854
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2s.c
Normal file
1854
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2s.c
Normal file
File diff suppressed because it is too large
Load Diff
3011
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_irda.c
Normal file
3011
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_irda.c
Normal file
File diff suppressed because it is too large
Load Diff
282
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_iwdg.c
Normal file
282
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_iwdg.c
Normal file
@@ -0,0 +1,282 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_iwdg.c
|
||||
* @author MCD Application Team
|
||||
* @brief IWDG HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Independent Watchdog (IWDG) peripheral:
|
||||
* + Initialization and Start functions
|
||||
* + IO operation functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### IWDG Generic features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(+) The IWDG can be started by either software or hardware (configurable
|
||||
through option byte).
|
||||
|
||||
(+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays
|
||||
active even if the main clock fails.
|
||||
|
||||
(+) Once the IWDG is started, the LSI is forced ON and both cannot be
|
||||
disabled. The counter starts counting down from the reset value (0xFFF).
|
||||
When it reaches the end of count value (0x000) a reset signal is
|
||||
generated (IWDG reset).
|
||||
|
||||
(+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
|
||||
the IWDG_RLR value is reloaded into the counter and the watchdog reset
|
||||
is prevented.
|
||||
|
||||
(+) The IWDG is implemented in the VDD voltage domain that is still functional
|
||||
in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY).
|
||||
IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
|
||||
reset occurs.
|
||||
|
||||
(+) Debug mode: When the microcontroller enters debug mode (core halted),
|
||||
the IWDG counter either continues to work normally or stops, depending
|
||||
on DBG_IWDG_STOP configuration bit in DBG module, accessible through
|
||||
__HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros.
|
||||
|
||||
[..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
|
||||
The IWDG timeout may vary due to LSI clock frequency dispersion.
|
||||
STM32F0xx devices provide the capability to measure the LSI clock
|
||||
frequency (LSI clock is internally connected to TIM16 CH1 input capture).
|
||||
The measured value can be used to have an IWDG timeout with an
|
||||
acceptable accuracy.
|
||||
|
||||
[..] Default timeout value (necessary for IWDG_SR status register update):
|
||||
Constant LSI_VALUE is defined based on the nominal LSI clock frequency.
|
||||
This frequency being subject to variations as mentioned above, the
|
||||
default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT
|
||||
below) may become too short or too long.
|
||||
In such cases, this default timeout value can be tuned by redefining
|
||||
the constant LSI_VALUE at user-application level (based, for instance,
|
||||
on the measured LSI clock frequency as explained above).
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) Use IWDG using HAL_IWDG_Init() function to :
|
||||
(++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
|
||||
clock is forced ON and IWDG counter starts counting down.
|
||||
(++) Enable write access to configuration registers:
|
||||
IWDG_PR, IWDG_RLR and IWDG_WINR.
|
||||
(++) Configure the IWDG prescaler and counter reload value. This reload
|
||||
value will be loaded in the IWDG counter each time the watchdog is
|
||||
reloaded, then the IWDG will start counting down from this value.
|
||||
(++) Depending on window parameter:
|
||||
(+++) If Window Init parameter is same as Window register value,
|
||||
nothing more is done but reload counter value in order to exit
|
||||
function with exact time base.
|
||||
(+++) Else modify Window register. This will automatically reload
|
||||
watchdog counter.
|
||||
(++) Wait for status flags to be reset.
|
||||
|
||||
(#) Then the application program must refresh the IWDG counter at regular
|
||||
intervals during normal operation to prevent an MCU reset, using
|
||||
HAL_IWDG_Refresh() function.
|
||||
|
||||
*** IWDG HAL driver macros list ***
|
||||
====================================
|
||||
[..]
|
||||
Below the list of most used macros in IWDG HAL driver:
|
||||
(+) __HAL_IWDG_START: Enable the IWDG peripheral
|
||||
(+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
|
||||
the reload register
|
||||
|
||||
@endverbatim
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||
/** @addtogroup IWDG
|
||||
* @brief IWDG HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Private_Defines IWDG Private Defines
|
||||
* @{
|
||||
*/
|
||||
/* Status register needs up to 5 LSI clock periods divided by the clock
|
||||
prescaler to be updated. The number of LSI clock periods is upper-rounded to
|
||||
6 for the timeout value calculation.
|
||||
The timeout value is calculated using the highest prescaler (256) and
|
||||
the LSI_VALUE constant. The value of this constant can be changed by the user
|
||||
to take into account possible LSI clock period variations.
|
||||
The timeout value is multiplied by 1000 to be converted in milliseconds.
|
||||
LSI startup time is also considered here by adding LSI_STARTUP_TIME
|
||||
converted in milliseconds. */
|
||||
#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL))
|
||||
#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup IWDG_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IWDG_Exported_Functions_Group1
|
||||
* @brief Initialization and Start functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Start functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Initialize the IWDG according to the specified parameters in the
|
||||
IWDG_InitTypeDef of associated handle.
|
||||
(+) Manage Window option.
|
||||
(+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
|
||||
is reloaded in order to exit function with correct time base.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initialize the IWDG according to the specified parameters in the
|
||||
* IWDG_InitTypeDef and start watchdog. Before exiting function,
|
||||
* watchdog is refreshed in order to have correct time base.
|
||||
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified IWDG module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
|
||||
/* Check the IWDG handle allocation */
|
||||
if (hiwdg == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
|
||||
assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
|
||||
assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
|
||||
assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
|
||||
|
||||
/* Enable IWDG. LSI is turned on automatically */
|
||||
__HAL_IWDG_START(hiwdg);
|
||||
|
||||
/* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing
|
||||
0x5555 in KR */
|
||||
IWDG_ENABLE_WRITE_ACCESS(hiwdg);
|
||||
|
||||
/* Write to IWDG registers the Prescaler & Reload values to work with */
|
||||
hiwdg->Instance->PR = hiwdg->Init.Prescaler;
|
||||
hiwdg->Instance->RLR = hiwdg->Init.Reload;
|
||||
|
||||
/* Check pending flag, if previous update not done, return timeout */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait for register to be updated */
|
||||
while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
|
||||
{
|
||||
if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
|
||||
{
|
||||
if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* If window parameter is different than current value, modify window
|
||||
register */
|
||||
if (hiwdg->Instance->WINR != hiwdg->Init.Window)
|
||||
{
|
||||
/* Write to IWDG WINR the IWDG_Window value to compare with. In any case,
|
||||
even if window feature is disabled, Watchdog will be reloaded by writing
|
||||
windows register */
|
||||
hiwdg->Instance->WINR = hiwdg->Init.Window;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Reload IWDG counter with value defined in the reload register */
|
||||
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
|
||||
}
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup IWDG_Exported_Functions_Group2
|
||||
* @brief IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Refresh the IWDG.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Refresh the IWDG.
|
||||
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified IWDG module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
|
||||
{
|
||||
/* Reload IWDG counter with value defined in the reload register */
|
||||
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_IWDG_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
101
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_msp_template.c
Normal file
101
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_msp_template.c
Normal file
@@ -0,0 +1,101 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_msp_template.c
|
||||
* @author MCD Application Team
|
||||
* @brief HAL MSP module.
|
||||
* This file template is located in the HAL folder and should be copied
|
||||
* to the user folder.
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### How to use this driver #####
|
||||
===============================================================================
|
||||
[..]
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_MSP HAL MSP module driver
|
||||
* @brief HAL MSP module.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup HAL_MSP_Private_Functions HAL MSP Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the Global MSP.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_MspInit(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the Global MSP.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_MspDeInit(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the PPP MSP.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PPP_MspInit(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the PPP MSP.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PPP_MspDeInit(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
2243
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.c
Normal file
2243
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.c
Normal file
File diff suppressed because it is too large
Load Diff
333
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.c
Normal file
333
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.c
Normal file
@@ -0,0 +1,333 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_pcd_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief PCD Extended HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the USB Peripheral Controller:
|
||||
* + Extended features functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PCDEx PCDEx
|
||||
* @brief PCD Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_PCD_MODULE_ENABLED
|
||||
|
||||
#if defined (USB)
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
|
||||
* @brief PCDEx control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extended features functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Update FIFO configuration
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configure PMA for EP
|
||||
* @param hpcd Device instance
|
||||
* @param ep_addr endpoint address
|
||||
* @param ep_kind endpoint Kind
|
||||
* USB_SNG_BUF: Single Buffer used
|
||||
* USB_DBL_BUF: Double Buffer used
|
||||
* @param pmaadress: EP address in The PMA: In case of single buffer endpoint
|
||||
* this parameter is 16-bit value providing the address
|
||||
* in PMA allocated to endpoint.
|
||||
* In case of double buffer endpoint this parameter
|
||||
* is a 32-bit value providing the endpoint buffer 0 address
|
||||
* in the LSB part of 32-bit value and endpoint buffer 1 address
|
||||
* in the MSB part of 32-bit value.
|
||||
* @retval HAL status
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
|
||||
uint16_t ep_kind, uint32_t pmaadress)
|
||||
{
|
||||
PCD_EPTypeDef *ep;
|
||||
|
||||
/* initialize ep structure*/
|
||||
if ((0x80U & ep_addr) == 0x80U)
|
||||
{
|
||||
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
||||
}
|
||||
else
|
||||
{
|
||||
ep = &hpcd->OUT_ep[ep_addr];
|
||||
}
|
||||
|
||||
/* Here we check if the endpoint is single or double Buffer*/
|
||||
if (ep_kind == PCD_SNG_BUF)
|
||||
{
|
||||
/* Single Buffer */
|
||||
ep->doublebuffer = 0U;
|
||||
/* Configure the PMA */
|
||||
ep->pmaadress = (uint16_t)pmaadress;
|
||||
}
|
||||
#if (USE_USB_DOUBLE_BUFFER == 1U)
|
||||
else /* USB_DBL_BUF */
|
||||
{
|
||||
/* Double Buffer Endpoint */
|
||||
ep->doublebuffer = 1U;
|
||||
/* Configure the PMA */
|
||||
ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU);
|
||||
ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16);
|
||||
}
|
||||
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Activate BatteryCharging feature.
|
||||
* @param hpcd PCD handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
|
||||
{
|
||||
USB_TypeDef *USBx = hpcd->Instance;
|
||||
hpcd->battery_charging_active = 1U;
|
||||
|
||||
/* Enable BCD feature */
|
||||
USBx->BCDR |= USB_BCDR_BCDEN;
|
||||
|
||||
/* Enable DCD : Data Contact Detect */
|
||||
USBx->BCDR &= ~(USB_BCDR_PDEN);
|
||||
USBx->BCDR &= ~(USB_BCDR_SDEN);
|
||||
USBx->BCDR |= USB_BCDR_DCDEN;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deactivate BatteryCharging feature.
|
||||
* @param hpcd PCD handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
|
||||
{
|
||||
USB_TypeDef *USBx = hpcd->Instance;
|
||||
hpcd->battery_charging_active = 0U;
|
||||
|
||||
/* Disable BCD feature */
|
||||
USBx->BCDR &= ~(USB_BCDR_BCDEN);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handle BatteryCharging Process.
|
||||
* @param hpcd PCD handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
|
||||
{
|
||||
USB_TypeDef *USBx = hpcd->Instance;
|
||||
uint32_t tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait for Min DCD Timeout */
|
||||
HAL_Delay(300U);
|
||||
|
||||
/* Data Pin Contact ? Check Detect flag */
|
||||
if ((USBx->BCDR & USB_BCDR_DCDET) == USB_BCDR_DCDET)
|
||||
{
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION);
|
||||
#else
|
||||
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
}
|
||||
/* Primary detection: checks if connected to Standard Downstream Port
|
||||
(without charging capability) */
|
||||
USBx->BCDR &= ~(USB_BCDR_DCDEN);
|
||||
HAL_Delay(50U);
|
||||
USBx->BCDR |= (USB_BCDR_PDEN);
|
||||
HAL_Delay(50U);
|
||||
|
||||
/* If Charger detect ? */
|
||||
if ((USBx->BCDR & USB_BCDR_PDET) == USB_BCDR_PDET)
|
||||
{
|
||||
/* Start secondary detection to check connection to Charging Downstream
|
||||
Port or Dedicated Charging Port */
|
||||
USBx->BCDR &= ~(USB_BCDR_PDEN);
|
||||
HAL_Delay(50U);
|
||||
USBx->BCDR |= (USB_BCDR_SDEN);
|
||||
HAL_Delay(50U);
|
||||
|
||||
/* If CDP ? */
|
||||
if ((USBx->BCDR & USB_BCDR_SDET) == USB_BCDR_SDET)
|
||||
{
|
||||
/* Dedicated Downstream Port DCP */
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
|
||||
#else
|
||||
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Charging Downstream Port CDP */
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
|
||||
#else
|
||||
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
}
|
||||
}
|
||||
else /* NO */
|
||||
{
|
||||
/* Standard Downstream Port */
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
|
||||
#else
|
||||
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
}
|
||||
|
||||
/* Battery Charging capability discovery finished Start Enumeration */
|
||||
(void)HAL_PCDEx_DeActivateBCD(hpcd);
|
||||
|
||||
/* Check for the Timeout, else start USB Device */
|
||||
if ((HAL_GetTick() - tickstart) > 1000U)
|
||||
{
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);
|
||||
#else
|
||||
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
}
|
||||
else
|
||||
{
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
|
||||
#else
|
||||
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Activate LPM feature.
|
||||
* @param hpcd PCD handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
|
||||
{
|
||||
|
||||
USB_TypeDef *USBx = hpcd->Instance;
|
||||
hpcd->lpm_active = 1U;
|
||||
hpcd->LPM_State = LPM_L0;
|
||||
|
||||
USBx->LPMCSR |= USB_LPMCSR_LMPEN;
|
||||
USBx->LPMCSR |= USB_LPMCSR_LPMACK;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deactivate LPM feature.
|
||||
* @param hpcd PCD handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
|
||||
{
|
||||
USB_TypeDef *USBx = hpcd->Instance;
|
||||
|
||||
hpcd->lpm_active = 0U;
|
||||
|
||||
USBx->LPMCSR &= ~(USB_LPMCSR_LMPEN);
|
||||
USBx->LPMCSR &= ~(USB_LPMCSR_LPMACK);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Send LPM message to user layer callback.
|
||||
* @param hpcd PCD handle
|
||||
* @param msg LPM message
|
||||
* @retval HAL status
|
||||
*/
|
||||
__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hpcd);
|
||||
UNUSED(msg);
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_PCDEx_LPM_Callback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Send BatteryCharging message to user layer callback.
|
||||
* @param hpcd PCD handle
|
||||
* @param msg LPM message
|
||||
* @retval HAL status
|
||||
*/
|
||||
__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hpcd);
|
||||
UNUSED(msg);
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_PCDEx_BCD_Callback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* defined (USB) */
|
||||
#endif /* HAL_PCD_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
450
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c
Normal file
450
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c
Normal file
@@ -0,0 +1,450 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_pwr.c
|
||||
* @author MCD Application Team
|
||||
* @brief PWR HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Power Controller (PWR) peripheral:
|
||||
* + Initialization/de-initialization function
|
||||
* + Peripheral Control function
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR PWR
|
||||
* @brief PWR HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWR_Exported_Functions PWR Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and de-initialization functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
After reset, the backup domain (RTC registers, RTC backup data
|
||||
registers) is protected against possible unwanted
|
||||
write accesses.
|
||||
To enable access to the RTC Domain and RTC registers, proceed as follows:
|
||||
(+) Enable the Power Controller (PWR) APB1 interface clock using the
|
||||
__HAL_RCC_PWR_CLK_ENABLE() macro.
|
||||
(+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the PWR peripheral registers to their default reset values.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DeInit(void)
|
||||
{
|
||||
__HAL_RCC_PWR_FORCE_RESET();
|
||||
__HAL_RCC_PWR_RELEASE_RESET();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables access to the backup domain (RTC registers, RTC
|
||||
* backup data registers when present).
|
||||
* @note If the HSE divided by 32 is used as the RTC clock, the
|
||||
* Backup Domain Access should be kept enabled.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableBkUpAccess(void)
|
||||
{
|
||||
PWR->CR |= (uint32_t)PWR_CR_DBP;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables access to the backup domain (RTC registers, RTC
|
||||
* backup data registers when present).
|
||||
* @note If the HSE divided by 32 is used as the RTC clock, the
|
||||
* Backup Domain Access should be kept enabled.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableBkUpAccess(void)
|
||||
{
|
||||
PWR->CR &= ~((uint32_t)PWR_CR_DBP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief Low Power modes configuration functions
|
||||
*
|
||||
@verbatim
|
||||
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
|
||||
*** WakeUp pin configuration ***
|
||||
================================
|
||||
[..]
|
||||
(+) WakeUp pin is used to wakeup the system from Standby mode. This pin is
|
||||
forced in input pull down configuration and is active on rising edges.
|
||||
(+) There are two WakeUp pins, and up to eight Wakeup pins on STM32F07x & STM32F09x devices.
|
||||
(++)WakeUp Pin 1 on PA.00.
|
||||
(++)WakeUp Pin 2 on PC.13.
|
||||
(++)WakeUp Pin 3 on PE.06.(STM32F07x/STM32F09x)
|
||||
(++)WakeUp Pin 4 on PA.02.(STM32F07x/STM32F09x)
|
||||
(++)WakeUp Pin 5 on PC.05.(STM32F07x/STM32F09x)
|
||||
(++)WakeUp Pin 6 on PB.05.(STM32F07x/STM32F09x)
|
||||
(++)WakeUp Pin 7 on PB.15.(STM32F07x/STM32F09x)
|
||||
(++)WakeUp Pin 8 on PF.02.(STM32F07x/STM32F09x)
|
||||
|
||||
*** Low Power modes configuration ***
|
||||
=====================================
|
||||
[..]
|
||||
The devices feature 3 low-power modes:
|
||||
(+) Sleep mode: Cortex-M0 core stopped, peripherals kept running.
|
||||
(+) Stop mode: all clocks are stopped, regulator running, regulator
|
||||
in low power mode
|
||||
(+) Standby mode: 1.2V domain powered off (mode not available on STM32F0x8 devices).
|
||||
|
||||
*** Sleep mode ***
|
||||
==================
|
||||
[..]
|
||||
(+) Entry:
|
||||
The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
|
||||
functions with
|
||||
(++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
|
||||
(++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
|
||||
|
||||
(+) Exit:
|
||||
(++) Any peripheral interrupt acknowledged by the nested vectored interrupt
|
||||
controller (NVIC) can wake up the device from Sleep mode.
|
||||
|
||||
*** Stop mode ***
|
||||
=================
|
||||
[..]
|
||||
In Stop mode, all clocks in the 1.8V domain are stopped, the PLL, the HSI,
|
||||
and the HSE RC oscillators are disabled. Internal SRAM and register contents
|
||||
are preserved.
|
||||
The voltage regulator can be configured either in normal or low-power mode.
|
||||
To minimize the consumption.
|
||||
|
||||
(+) Entry:
|
||||
The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFI )
|
||||
function with:
|
||||
(++) Main regulator ON.
|
||||
(++) Low Power regulator ON.
|
||||
(++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction
|
||||
(++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction
|
||||
(+) Exit:
|
||||
(++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
|
||||
(++) Some specific communication peripherals (CEC, USART, I2C) interrupts,
|
||||
when programmed in wakeup mode (the peripheral must be
|
||||
programmed in wakeup mode and the corresponding interrupt vector
|
||||
must be enabled in the NVIC)
|
||||
|
||||
*** Standby mode ***
|
||||
====================
|
||||
[..]
|
||||
The Standby mode allows to achieve the lowest power consumption. It is based
|
||||
on the Cortex-M0 deep sleep mode, with the voltage regulator disabled.
|
||||
The 1.8V domain is consequently powered off. The PLL, the HSI oscillator and
|
||||
the HSE oscillator are also switched off. SRAM and register contents are lost
|
||||
except for the RTC registers, RTC backup registers and Standby circuitry.
|
||||
The voltage regulator is OFF.
|
||||
|
||||
(+) Entry:
|
||||
(++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
|
||||
(+) Exit:
|
||||
(++) WKUP pin rising edge, RTC alarm (Alarm A), RTC wakeup,
|
||||
tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
|
||||
|
||||
*** Auto-wakeup (AWU) from low-power mode ***
|
||||
=============================================
|
||||
[..]
|
||||
The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
|
||||
Wakeup event, a tamper event, a time-stamp event, or a comparator event,
|
||||
without depending on an external interrupt (Auto-wakeup mode).
|
||||
|
||||
(+) RTC auto-wakeup (AWU) from the Stop and Standby modes
|
||||
|
||||
(++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
|
||||
configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
|
||||
|
||||
(++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
|
||||
is necessary to configure the RTC to detect the tamper or time stamp event using the
|
||||
HAL_RTC_SetTimeStamp_IT() or HAL_RTC_SetTamper_IT() functions.
|
||||
|
||||
(++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
|
||||
configure the RTC to generate the RTC WakeUp event using the HAL_RTC_SetWakeUpTimer_IT() function.
|
||||
|
||||
(+) Comparator auto-wakeup (AWU) from the Stop mode
|
||||
|
||||
(++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to:
|
||||
(+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for comparator 2)
|
||||
to be sensitive to to the selected edges (falling, rising or falling
|
||||
and rising) (Interrupt or Event modes) using the EXTI_Init() function.
|
||||
(+++) Configure the comparator to generate the event.
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables the WakeUp PINx functionality.
|
||||
* @param WakeUpPinx Specifies the Power Wake-Up pin to enable.
|
||||
* This parameter can be value of :
|
||||
* @ref PWREx_WakeUp_Pins
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
|
||||
/* Enable the EWUPx pin */
|
||||
SET_BIT(PWR->CSR, WakeUpPinx);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the WakeUp PINx functionality.
|
||||
* @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
|
||||
* This parameter can be values of :
|
||||
* @ref PWREx_WakeUp_Pins
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
|
||||
/* Disable the EWUPx pin */
|
||||
CLEAR_BIT(PWR->CSR, WakeUpPinx);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters Sleep mode.
|
||||
* @note In Sleep mode, all I/O pins keep the same state as in Run mode.
|
||||
* @param Regulator Specifies the regulator state in SLEEP mode.
|
||||
* On STM32F0 devices, this parameter is a dummy value and it is ignored
|
||||
* as regulator can't be modified in this mode. Parameter is kept for platform
|
||||
* compatibility.
|
||||
* @param SLEEPEntry Specifies if SLEEP mode is entered with WFI or WFE instruction.
|
||||
* When WFI entry is used, tick interrupt have to be disabled if not desired as
|
||||
* the interrupt wake up source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
|
||||
* @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_REGULATOR(Regulator));
|
||||
assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
|
||||
|
||||
/* Clear SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
|
||||
|
||||
/* Select SLEEP mode entry -------------------------------------------------*/
|
||||
if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
|
||||
{
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Request Wait For Event */
|
||||
__SEV();
|
||||
__WFE();
|
||||
__WFE();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters STOP mode.
|
||||
* @note In Stop mode, all I/O pins keep the same state as in Run mode.
|
||||
* @note When exiting Stop mode by issuing an interrupt or a wakeup event,
|
||||
* the HSI RC oscillator is selected as system clock.
|
||||
* @note When the voltage regulator operates in low power mode, an additional
|
||||
* startup delay is incurred when waking up from Stop mode.
|
||||
* By keeping the internal regulator ON during Stop mode, the consumption
|
||||
* is higher although the startup time is reduced.
|
||||
* @param Regulator Specifies the regulator state in STOP mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON
|
||||
* @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON
|
||||
* @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction
|
||||
* @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_REGULATOR(Regulator));
|
||||
assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
|
||||
|
||||
/* Select the regulator state in STOP mode ---------------------------------*/
|
||||
tmpreg = PWR->CR;
|
||||
|
||||
/* Clear PDDS and LPDS bits */
|
||||
tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS);
|
||||
|
||||
/* Set LPDS bit according to Regulator value */
|
||||
tmpreg |= Regulator;
|
||||
|
||||
/* Store the new value */
|
||||
PWR->CR = tmpreg;
|
||||
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||||
|
||||
/* Select STOP mode entry --------------------------------------------------*/
|
||||
if(STOPEntry == PWR_STOPENTRY_WFI)
|
||||
{
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Request Wait For Event */
|
||||
__SEV();
|
||||
__WFE();
|
||||
__WFE();
|
||||
}
|
||||
|
||||
/* Reset SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters STANDBY mode.
|
||||
* @note In Standby mode, all I/O pins are high impedance except for:
|
||||
* - Reset pad (still available)
|
||||
* - RTC alternate function pins if configured for tamper, time-stamp, RTC
|
||||
* Alarm out, or RTC clock calibration out.
|
||||
* - WKUP pins if enabled.
|
||||
* STM32F0x8 devices, the Stop mode is available, but it is
|
||||
* aningless to distinguish between voltage regulator in Low power
|
||||
* mode and voltage regulator in Run mode because the regulator
|
||||
* not used and the core is supplied directly from an external source.
|
||||
* Consequently, the Standby mode is not available on those devices.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnterSTANDBYMode(void)
|
||||
{
|
||||
/* Select STANDBY mode */
|
||||
PWR->CR |= (uint32_t)PWR_CR_PDDS;
|
||||
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||||
|
||||
/* This option is used to ensure that store operations are completed */
|
||||
#if defined ( __CC_ARM)
|
||||
__force_stores();
|
||||
#endif
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
|
||||
* @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
|
||||
* re-enters SLEEP mode when an interruption handling is over.
|
||||
* Setting this bit is useful when the processor is expected to run only on
|
||||
* interruptions handling.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableSleepOnExit(void)
|
||||
{
|
||||
/* Set SLEEPONEXIT bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
|
||||
* @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
|
||||
* re-enters SLEEP mode when an interruption handling is over.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableSleepOnExit(void)
|
||||
{
|
||||
/* Clear SLEEPONEXIT bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enables CORTEX M4 SEVONPEND bit.
|
||||
* @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
|
||||
* WFE to wake up when an interrupt moves from inactive to pended.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableSEVOnPend(void)
|
||||
{
|
||||
/* Set SEVONPEND bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disables CORTEX M4 SEVONPEND bit.
|
||||
* @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
|
||||
* WFE to wake up when an interrupt moves from inactive to pended.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableSEVOnPend(void)
|
||||
{
|
||||
/* Clear SEVONPEND bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
271
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c
Normal file
271
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c
Normal file
@@ -0,0 +1,271 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_pwr_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief Extended PWR HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Power Controller (PWR) peripheral:
|
||||
* + Extended Initialization and de-initialization functions
|
||||
* + Extended Peripheral Control functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx PWREx
|
||||
* @brief PWREx HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @defgroup PWREx_Private_Constants PWREx Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define PVD_MODE_IT (0x00010000U)
|
||||
#define PVD_MODE_EVT (0x00020000U)
|
||||
#define PVD_RISING_EDGE (0x00000001U)
|
||||
#define PVD_FALLING_EDGE (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWREx_Exported_Functions PWREx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended Control Functions
|
||||
* @brief Extended Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
|
||||
===============================================================================
|
||||
##### Peripheral extended control functions #####
|
||||
===============================================================================
|
||||
|
||||
*** PVD configuration ***
|
||||
=========================
|
||||
[..]
|
||||
(+) The PVD is used to monitor the VDD power supply by comparing it to a
|
||||
threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
|
||||
(+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
|
||||
than the PVD threshold. This event is internally connected to the EXTI
|
||||
line16 and can generate an interrupt if enabled. This is done through
|
||||
HAL_PWR_ConfigPVD(), HAL_PWR_EnablePVD() functions.
|
||||
(+) The PVD is stopped in Standby mode.
|
||||
-@- PVD is not available on STM32F030x4/x6/x8
|
||||
|
||||
*** VDDIO2 Monitor Configuration ***
|
||||
====================================
|
||||
[..]
|
||||
(+) VDDIO2 monitor is used to monitor the VDDIO2 power supply by comparing it
|
||||
to VREFInt Voltage
|
||||
(+) This monitor is internally connected to the EXTI line31
|
||||
and can generate an interrupt if enabled. This is done through
|
||||
HAL_PWREx_EnableVddio2Monitor() function.
|
||||
-@- VDDIO2 is available on STM32F07x/09x/04x
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (STM32F031x6) || defined (STM32F051x8) || \
|
||||
defined (STM32F071xB) || defined (STM32F091xC) || \
|
||||
defined (STM32F042x6) || defined (STM32F072xB)
|
||||
/**
|
||||
* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
|
||||
* @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration
|
||||
* information for the PVD.
|
||||
* @note Refer to the electrical characteristics of your device datasheet for
|
||||
* more details about the voltage threshold corresponding to each
|
||||
* detection level.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
|
||||
assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
|
||||
|
||||
/* Set PLS[7:5] bits according to PVDLevel value */
|
||||
MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
|
||||
|
||||
/* Clear any previous config. Keep it clear if no event or IT mode is selected */
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_EVENT();
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_IT();
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
|
||||
|
||||
/* Configure interrupt mode */
|
||||
if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_IT();
|
||||
}
|
||||
|
||||
/* Configure event mode */
|
||||
if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_EVENT();
|
||||
}
|
||||
|
||||
/* Configure the edge */
|
||||
if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
|
||||
}
|
||||
|
||||
if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the Power Voltage Detector(PVD).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnablePVD(void)
|
||||
{
|
||||
PWR->CR |= (uint32_t)PWR_CR_PVDE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the Power Voltage Detector(PVD).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisablePVD(void)
|
||||
{
|
||||
PWR->CR &= ~((uint32_t)PWR_CR_PVDE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles the PWR PVD interrupt request.
|
||||
* @note This API should be called under the PVD_IRQHandler() or PVD_VDDIO2_IRQHandler().
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_PVD_IRQHandler(void)
|
||||
{
|
||||
/* Check PWR exti flag */
|
||||
if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
|
||||
{
|
||||
/* PWR PVD interrupt user callback */
|
||||
HAL_PWR_PVDCallback();
|
||||
|
||||
/* Clear PWR Exti pending bit */
|
||||
__HAL_PWR_PVD_EXTI_CLEAR_FLAG();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief PWR PVD interrupt callback
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_PWR_PVDCallback(void)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_PWR_PVDCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
#endif /* defined (STM32F031x6) || defined (STM32F051x8) || */
|
||||
/* defined (STM32F071xB) || defined (STM32F091xC) || */
|
||||
/* defined (STM32F042x6) || defined (STM32F072xB) */
|
||||
|
||||
#if defined (STM32F042x6) || defined (STM32F048xx) || \
|
||||
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
|
||||
defined (STM32F091xC) || defined (STM32F098xx)
|
||||
/**
|
||||
* @brief Enable VDDIO2 monitor: enable Exti 31 and falling edge detection.
|
||||
* @note If Exti 31 is enable correlty and VDDIO2 voltage goes below Vrefint,
|
||||
an interrupt is generated Irq line 1.
|
||||
NVIS has to be enable by user.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWREx_EnableVddio2Monitor(void)
|
||||
{
|
||||
__HAL_PWR_VDDIO2_EXTI_ENABLE_IT();
|
||||
__HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Vddio2 Monitor.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWREx_DisableVddio2Monitor(void)
|
||||
{
|
||||
__HAL_PWR_VDDIO2_EXTI_DISABLE_IT();
|
||||
__HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE();
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles the PWR Vddio2 monitor interrupt request.
|
||||
* @note This API should be called under the VDDIO2_IRQHandler() PVD_VDDIO2_IRQHandler().
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWREx_Vddio2Monitor_IRQHandler(void)
|
||||
{
|
||||
/* Check PWR exti flag */
|
||||
if(__HAL_PWR_VDDIO2_EXTI_GET_FLAG() != RESET)
|
||||
{
|
||||
/* PWR Vddio2 monitor interrupt user callback */
|
||||
HAL_PWREx_Vddio2MonitorCallback();
|
||||
|
||||
/* Clear PWR Exti pending bit */
|
||||
__HAL_PWR_VDDIO2_EXTI_CLEAR_FLAG();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief PWR Vddio2 Monitor interrupt callback
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_PWREx_Vddio2MonitorCallback(void)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_PWREx_Vddio2MonitorCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
|
||||
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
|
||||
defined (STM32F091xC) || defined (STM32F098xx) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
1365
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c
Normal file
1365
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c
Normal file
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user